[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nva3_pm.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_bios.h"
#include "nouveau_pm.h"

static u32 read_clk(struct drm_device *, int, bool);
static u32 read_pll(struct drm_device *, int, u32);

static u32
read_vco(struct drm_device *dev, int clk)
{
	u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
	if ((sctl & 0x00000030) != 0x00000030)
		return read_pll(dev, 0x41, 0x00e820);
	return read_pll(dev, 0x42, 0x00e8a0);
}

static u32
read_clk(struct drm_device *dev, int clk, bool ignore_en)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 sctl, sdiv, sclk;

	/* refclk for the 0xe8xx plls is a fixed frequency */
	if (clk >= 0x40)
		return dev_priv->crystal;

	sctl = nv_rd32(dev, 0x4120 + (clk * 4));
	if (!ignore_en && !(sctl & 0x00000100))
		return 0;

	switch (sctl & 0x00003000) {
	case 0x00000000:
		return dev_priv->crystal;
	case 0x00002000:
		if (sctl & 0x00000040)
			return 108000;
		return 100000;
	case 0x00003000:
		sclk = read_vco(dev, clk);
		sdiv = ((sctl & 0x003f0000) >> 16) + 2;
		return (sclk * 2) / sdiv;
	default:
		return 0;
	}
}

static u32
read_pll(struct drm_device *dev, int clk, u32 pll)
{
	u32 ctrl = nv_rd32(dev, pll + 0);
	u32 sclk = 0, P = 1, N = 1, M = 1;

	if (!(ctrl & 0x00000008)) {
		if (ctrl & 0x00000001) {
			u32 coef = nv_rd32(dev, pll + 4);
			M = (coef & 0x000000ff) >> 0;
			N = (coef & 0x0000ff00) >> 8;
			P = (coef & 0x003f0000) >> 16;

			/* no post-divider on these.. */
			if ((pll & 0x00ff00) == 0x00e800)
				P = 1;

			sclk = read_clk(dev, 0x00 + clk, false);
		}
	} else {
		sclk = read_clk(dev, 0x10 + clk, false);
	}

	return sclk * N / (M * P);
}

struct creg {
	u32 clk;
	u32 pll;
};

static int
calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
{
	struct pll_lims limits;
	u32 oclk, sclk, sdiv;
	int P, N, M, diff;
	int ret;

	reg->pll = 0;
	reg->clk = 0;
	if (!khz) {
		NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk);
		return 0;
	}

	switch (khz) {
	case 27000:
		reg->clk = 0x00000100;
		return khz;
	case 100000:
		reg->clk = 0x00002100;
		return khz;
	case 108000:
		reg->clk = 0x00002140;
		return khz;
	default:
		sclk = read_vco(dev, clk);
		sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
		/* if the clock has a PLL attached, and we can get a within
		 * [-2, 3) MHz of a divider, we'll disable the PLL and use
		 * the divider instead.
		 *
		 * divider can go as low as 2, limited here because NVIDIA
		 * and the VBIOS on my NVA8 seem to prefer using the PLL
		 * for 810MHz - is there a good reason?
		 */
		if (sdiv > 4) {
			oclk = (sclk * 2) / sdiv;
			diff = khz - oclk;
			if (!pll || (diff >= -2000 && diff < 3000)) {
				reg->clk = (((sdiv - 2) << 16) | 0x00003100);
				return oclk;
			}
		}

		if (!pll) {
			NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk);
			return -ERANGE;
		}

		break;
	}

	ret = get_pll_limits(dev, pll, &limits);
	if (ret)
		return ret;

	limits.refclk = read_clk(dev, clk - 0x10, true);
	if (!limits.refclk)
		return -EINVAL;

	ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
	if (ret >= 0) {
		reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
		reg->pll = (P << 16) | (N << 8) | M;
	}
	return ret;
}

static void
prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
{
	const u32 src0 = 0x004120 + (clk * 4);
	const u32 src1 = 0x004160 + (clk * 4);
	const u32 ctrl = pll + 0;
	const u32 coef = pll + 4;
	u32 cntl;

	if (!reg->clk && !reg->pll) {
		NV_DEBUG(dev, "no clock for %02x\n", clk);
		return;
	}

	cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
	if (reg->pll) {
		nv_mask(dev, src0, 0x00000101, 0x00000101);
		nv_wr32(dev, coef, reg->pll);
		nv_wr32(dev, ctrl, cntl | 0x00000015);
		nv_mask(dev, src1, 0x00000100, 0x00000000);
		nv_mask(dev, src1, 0x00000001, 0x00000000);
	} else {
		nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
		nv_wr32(dev, ctrl, cntl | 0x0000001d);
		nv_mask(dev, ctrl, 0x00000001, 0x00000000);
		nv_mask(dev, src0, 0x00000100, 0x00000000);
		nv_mask(dev, src0, 0x00000001, 0x00000000);
	}
}

static void
prog_clk(struct drm_device *dev, int clk, struct creg *reg)
{
	if (!reg->clk) {
		NV_DEBUG(dev, "no clock for %02x\n", clk);
		return;
	}

	nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
}

int
nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
	perflvl->core   = read_pll(dev, 0x00, 0x4200);
	perflvl->shader = read_pll(dev, 0x01, 0x4220);
	perflvl->memory = read_pll(dev, 0x02, 0x4000);
	perflvl->unka0  = read_clk(dev, 0x20, false);
	perflvl->vdec   = read_clk(dev, 0x21, false);
	perflvl->daemon = read_clk(dev, 0x25, false);
	perflvl->copy   = perflvl->core;
	return 0;
}

struct nva3_pm_state {
	struct creg nclk;
	struct creg sclk;
	struct creg mclk;
	struct creg vdec;
	struct creg unka0;
};

void *
nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
	struct nva3_pm_state *info;
	int ret;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info)
		return ERR_PTR(-ENOMEM);

	ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk);
	if (ret < 0)
		goto out;

	ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk);
	if (ret < 0)
		goto out;

	ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk);
	if (ret < 0)
		goto out;

	ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0);
	if (ret < 0)
		goto out;

	ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec);
	if (ret < 0)
		goto out;

out:
	if (ret < 0) {
		kfree(info);
		info = ERR_PTR(ret);
	}
	return info;
}

static bool
nva3_pm_grcp_idle(void *data)
{
	struct drm_device *dev = data;

	if (!(nv_rd32(dev, 0x400304) & 0x00000001))
		return true;
	if (nv_rd32(dev, 0x400308) == 0x0050001c)
		return true;
	return false;
}

void
nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nva3_pm_state *info = pre_state;
	unsigned long flags;

	/* prevent any new grctx switches from starting */
	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv_wr32(dev, 0x400324, 0x00000000);
	nv_wr32(dev, 0x400328, 0x0050001c); /* wait flag 0x1c */
	/* wait for any pending grctx switches to complete */
	if (!nv_wait_cb(dev, nva3_pm_grcp_idle, dev)) {
		NV_ERROR(dev, "pm: ctxprog didn't go idle\n");
		goto cleanup;
	}
	/* freeze PFIFO */
	nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
	if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) {
		NV_ERROR(dev, "pm: fifo didn't go idle\n");
		goto cleanup;
	}

	prog_pll(dev, 0x00, 0x004200, &info->nclk);
	prog_pll(dev, 0x01, 0x004220, &info->sclk);
	prog_clk(dev, 0x20, &info->unka0);
	prog_clk(dev, 0x21, &info->vdec);

	if (info->mclk.clk || info->mclk.pll) {
		nv_wr32(dev, 0x100210, 0);
		nv_wr32(dev, 0x1002dc, 1);
		nv_wr32(dev, 0x004018, 0x00001000);
		prog_pll(dev, 0x02, 0x004000, &info->mclk);
		if (nv_rd32(dev, 0x4000) & 0x00000008)
			nv_wr32(dev, 0x004018, 0x1000d000);
		else
			nv_wr32(dev, 0x004018, 0x10005000);
		nv_wr32(dev, 0x1002dc, 0);
		nv_wr32(dev, 0x100210, 0x80000000);
	}

cleanup:
	/* unfreeze PFIFO */
	nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
	/* restore ctxprog to normal */
	nv_wr32(dev, 0x400324, 0x00000000);
	nv_wr32(dev, 0x400328, 0x0070009c); /* set flag 0x1c */
	/* unblock it if necessary */
	if (nv_rd32(dev, 0x400308) == 0x0050001c)
		nv_mask(dev, 0x400824, 0x10000000, 0x10000000);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	kfree(info);
}
Commit	Line	Data
fade7ad5 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26	#include "nouveau_drv.h"
	27	#include "nouveau_bios.h"
	28	#include "nouveau_pm.h"
	29
ca94a71f	30	static u32 read_clk(struct drm_device *, int, bool);
cec2a270	31	static u32 read_pll(struct drm_device *, int, u32);
3b0582d3 BS	32
3b0582d3 BS	33	static u32
ca94a71f BS	34	read_vco(struct drm_device *dev, int clk)
	35	{
	36	u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
	37	if ((sctl & 0x00000030) != 0x00000030)
cec2a270 BS	38	return read_pll(dev, 0x41, 0x00e820);
cec2a270 BS	39	return read_pll(dev, 0x42, 0x00e8a0);
ca94a71f BS	40	}
	41
	42	static u32
	43	read_clk(struct drm_device *dev, int clk, bool ignore_en)
3b0582d3	44	{
64e740bb	45	struct drm_nouveau_private *dev_priv = dev->dev_private;
3b0582d3 BS	46	u32 sctl, sdiv, sclk;
3b0582d3 BS	47
64e740bb	48	/* refclk for the 0xe8xx plls is a fixed frequency */
3b0582d3	49	if (clk >= 0x40)
64e740bb	50	return dev_priv->crystal;
3b0582d3 BS	51
3b0582d3 BS	52	sctl = nv_rd32(dev, 0x4120 + (clk * 4));
ca94a71f BS	53	if (!ignore_en && !(sctl & 0x00000100))
	54	return 0;
	55
	56	switch (sctl & 0x00003000) {
	57	case 0x00000000:
64e740bb	58	return dev_priv->crystal;
ca94a71f	59	case 0x00002000:
3b0582d3 BS	60	if (sctl & 0x00000040)
	61	return 108000;
	62	return 100000;
ca94a71f BS	63	case 0x00003000:
ca94a71f BS	64	sclk = read_vco(dev, clk);
3b0582d3	65	sdiv = ((sctl & 0x003f0000) >> 16) + 2;
3b0582d3 BS	66	return (sclk * 2) / sdiv;
	67	default:
	68	return 0;
	69	}
	70	}
	71
	72	static u32
cec2a270	73	read_pll(struct drm_device *dev, int clk, u32 pll)
3b0582d3 BS	74	{
3b0582d3 BS	75	u32 ctrl = nv_rd32(dev, pll + 0);
93e692dc	76	u32 sclk = 0, P = 1, N = 1, M = 1;
3b0582d3 BS	77
3b0582d3 BS	78	if (!(ctrl & 0x00000008)) {
93e692dc BS	79	if (ctrl & 0x00000001) {
	80	u32 coef = nv_rd32(dev, pll + 4);
	81	M = (coef & 0x000000ff) >> 0;
	82	N = (coef & 0x0000ff00) >> 8;
	83	P = (coef & 0x003f0000) >> 16;
cec2a270	84
93e692dc BS	85	/* no post-divider on these.. */
	86	if ((pll & 0x00ff00) == 0x00e800)
	87	P = 1;
3b0582d3	88
93e692dc BS	89	sclk = read_clk(dev, 0x00 + clk, false);
93e692dc BS	90	}
3b0582d3	91	} else {
ca94a71f	92	sclk = read_clk(dev, 0x10 + clk, false);
3b0582d3 BS	93	}
	94
	95	return sclk * N / (M * P);
	96	}
fade7ad5	97
ca94a71f BS	98	struct creg {
	99	u32 clk;
	100	u32 pll;
fade7ad5 BS	101	};
fade7ad5 BS	102
215f902e	103	static int
cec2a270	104	calc_clk(struct drm_device dev, int clk, u32 pll, u32 khz, struct creg reg)
215f902e	105	{
ca94a71f BS	106	struct pll_lims limits;
	107	u32 oclk, sclk, sdiv;
	108	int P, N, M, diff;
	109	int ret;
	110
	111	reg->pll = 0;
	112	reg->clk = 0;
cec2a270 BS	113	if (!khz) {
	114	NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk);
	115	return 0;
	116	}
ca94a71f BS	117
	118	switch (khz) {
	119	case 27000:
	120	reg->clk = 0x00000100;
	121	return khz;
	122	case 100000:
	123	reg->clk = 0x00002100;
	124	return khz;
	125	case 108000:
	126	reg->clk = 0x00002140;
	127	return khz;
	128	default:
	129	sclk = read_vco(dev, clk);
	130	sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
cec2a270 BS	131	/* if the clock has a PLL attached, and we can get a within
	132	* [-2, 3) MHz of a divider, we'll disable the PLL and use
	133	* the divider instead.
	134	*
	135	* divider can go as low as 2, limited here because NVIDIA
	136	* and the VBIOS on my NVA8 seem to prefer using the PLL
	137	* for 810MHz - is there a good reason?
	138	*/
ca94a71f BS	139	if (sdiv > 4) {
	140	oclk = (sclk * 2) / sdiv;
	141	diff = khz - oclk;
	142	if (!pll \|\| (diff >= -2000 && diff < 3000)) {
	143	reg->clk = (((sdiv - 2) << 16) \| 0x00003100);
	144	return oclk;
	145	}
	146	}
cec2a270 BS	147
	148	if (!pll) {
	149	NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk);
	150	return -ERANGE;
	151	}
	152
ca94a71f	153	break;
215f902e BS	154	}
215f902e BS	155
ca94a71f BS	156	ret = get_pll_limits(dev, pll, &limits);
	157	if (ret)
	158	return ret;
	159
	160	limits.refclk = read_clk(dev, clk - 0x10, true);
	161	if (!limits.refclk)
	162	return -EINVAL;
	163
	164	ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
	165	if (ret >= 0) {
	166	reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
	167	reg->pll = (P << 16) \| (N << 8) \| M;
	168	}
	169	return ret;
215f902e BS	170	}
215f902e BS	171
cec2a270 BS	172	static void
	173	prog_pll(struct drm_device dev, int clk, u32 pll, struct creg reg)
	174	{
	175	const u32 src0 = 0x004120 + (clk * 4);
	176	const u32 src1 = 0x004160 + (clk * 4);
	177	const u32 ctrl = pll + 0;
	178	const u32 coef = pll + 4;
	179	u32 cntl;
	180
	181	if (!reg->clk && !reg->pll) {
	182	NV_DEBUG(dev, "no clock for %02x\n", clk);
	183	return;
	184	}
	185
	186	cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
	187	if (reg->pll) {
	188	nv_mask(dev, src0, 0x00000101, 0x00000101);
	189	nv_wr32(dev, coef, reg->pll);
	190	nv_wr32(dev, ctrl, cntl \| 0x00000015);
	191	nv_mask(dev, src1, 0x00000100, 0x00000000);
	192	nv_mask(dev, src1, 0x00000001, 0x00000000);
	193	} else {
	194	nv_mask(dev, src1, 0x003f3141, 0x00000101 \| reg->clk);
	195	nv_wr32(dev, ctrl, cntl \| 0x0000001d);
	196	nv_mask(dev, ctrl, 0x00000001, 0x00000000);
	197	nv_mask(dev, src0, 0x00000100, 0x00000000);
	198	nv_mask(dev, src0, 0x00000001, 0x00000000);
	199	}
	200	}
	201
	202	static void
	203	prog_clk(struct drm_device dev, int clk, struct creg reg)
	204	{
	205	if (!reg->clk) {
	206	NV_DEBUG(dev, "no clock for %02x\n", clk);
	207	return;
	208	}
	209
	210	nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 \| reg->clk);
	211	}
	212
fade7ad5	213	int
ca94a71f	214	nva3_pm_clocks_get(struct drm_device dev, struct nouveau_pm_level perflvl)
fade7ad5	215	{
cec2a270 BS	216	perflvl->core = read_pll(dev, 0x00, 0x4200);
	217	perflvl->shader = read_pll(dev, 0x01, 0x4220);
	218	perflvl->memory = read_pll(dev, 0x02, 0x4000);
4fd2847e BS	219	perflvl->unka0 = read_clk(dev, 0x20, false);
4fd2847e BS	220	perflvl->vdec = read_clk(dev, 0x21, false);
9698b9a6 BS	221	perflvl->daemon = read_clk(dev, 0x25, false);
9698b9a6 BS	222	perflvl->copy = perflvl->core;
ca94a71f	223	return 0;
fade7ad5 BS	224	}
fade7ad5 BS	225
ca94a71f BS	226	struct nva3_pm_state {
	227	struct creg nclk;
	228	struct creg sclk;
	229	struct creg mclk;
4fd2847e BS	230	struct creg vdec;
4fd2847e BS	231	struct creg unka0;
ca94a71f BS	232	};
ca94a71f BS	233
fade7ad5	234	void *
ca94a71f	235	nva3_pm_clocks_pre(struct drm_device dev, struct nouveau_pm_level perflvl)
fade7ad5	236	{
ca94a71f BS	237	struct nva3_pm_state *info;
ca94a71f BS	238	int ret;
fade7ad5	239
ca94a71f BS	240	info = kzalloc(sizeof(*info), GFP_KERNEL);
	241	if (!info)
	242	return ERR_PTR(-ENOMEM);
	243
cec2a270	244	ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk);
dac55b58	245	if (ret < 0)
ca94a71f	246	goto out;
dac55b58	247
cec2a270	248	ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk);
ca94a71f BS	249	if (ret < 0)
ca94a71f BS	250	goto out;
dac55b58	251
cec2a270	252	ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk);
ca94a71f BS	253	if (ret < 0)
ca94a71f BS	254	goto out;
dac55b58	255
cec2a270	256	ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0);
4fd2847e BS	257	if (ret < 0)
	258	goto out;
	259
cec2a270	260	ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec);
4fd2847e BS	261	if (ret < 0)
	262	goto out;
	263
ca94a71f BS	264	out:
	265	if (ret < 0) {
	266	kfree(info);
	267	info = ERR_PTR(ret);
fade7ad5	268	}
ca94a71f BS	269	return info;
ca94a71f BS	270	}
fade7ad5	271
d0f67a48 BS	272	static bool
	273	nva3_pm_grcp_idle(void *data)
	274	{
	275	struct drm_device *dev = data;
	276
	277	if (!(nv_rd32(dev, 0x400304) & 0x00000001))
	278	return true;
	279	if (nv_rd32(dev, 0x400308) == 0x0050001c)
	280	return true;
	281	return false;
	282	}
	283
fade7ad5	284	void
ca94a71f	285	nva3_pm_clocks_set(struct drm_device dev, void pre_state)
fade7ad5	286	{
d0f67a48	287	struct drm_nouveau_private *dev_priv = dev->dev_private;
ca94a71f	288	struct nva3_pm_state *info = pre_state;
d0f67a48 BS	289	unsigned long flags;
	290
	291	/* prevent any new grctx switches from starting */
	292	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	293	nv_wr32(dev, 0x400324, 0x00000000);
	294	nv_wr32(dev, 0x400328, 0x0050001c); /* wait flag 0x1c */
	295	/* wait for any pending grctx switches to complete */
	296	if (!nv_wait_cb(dev, nva3_pm_grcp_idle, dev)) {
	297	NV_ERROR(dev, "pm: ctxprog didn't go idle\n");
	298	goto cleanup;
	299	}
	300	/* freeze PFIFO */
	301	nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
	302	if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) {
	303	NV_ERROR(dev, "pm: fifo didn't go idle\n");
	304	goto cleanup;
	305	}
ca94a71f	306
cec2a270 BS	307	prog_pll(dev, 0x00, 0x004200, &info->nclk);
cec2a270 BS	308	prog_pll(dev, 0x01, 0x004220, &info->sclk);
4fd2847e BS	309	prog_clk(dev, 0x20, &info->unka0);
4fd2847e BS	310	prog_clk(dev, 0x21, &info->vdec);
ca94a71f	311
93e692dc BS	312	if (info->mclk.clk \|\| info->mclk.pll) {
	313	nv_wr32(dev, 0x100210, 0);
	314	nv_wr32(dev, 0x1002dc, 1);
	315	nv_wr32(dev, 0x004018, 0x00001000);
	316	prog_pll(dev, 0x02, 0x004000, &info->mclk);
	317	if (nv_rd32(dev, 0x4000) & 0x00000008)
	318	nv_wr32(dev, 0x004018, 0x1000d000);
	319	else
	320	nv_wr32(dev, 0x004018, 0x10005000);
	321	nv_wr32(dev, 0x1002dc, 0);
	322	nv_wr32(dev, 0x100210, 0x80000000);
	323	}
ca94a71f	324
d0f67a48 BS	325	cleanup:
	326	/* unfreeze PFIFO */
	327	nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
	328	/* restore ctxprog to normal */
	329	nv_wr32(dev, 0x400324, 0x00000000);
	330	nv_wr32(dev, 0x400328, 0x0070009c); /* set flag 0x1c */
	331	/* unblock it if necessary */
	332	if (nv_rd32(dev, 0x400308) == 0x0050001c)
	333	nv_mask(dev, 0x400824, 0x10000000, 0x10000000);
	334	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
ca94a71f	335	kfree(info);
fade7ad5	336	}