[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nv84_fence.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"

#include "nv50_display.h"

u64
nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
{
	struct nv84_fence_chan *fctx = chan->fence;
	return fctx->dispc_vma[crtc].offset;
}

static int
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
	int ret = RING_SPACE(chan, 8);
	if (ret == 0) {
		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
		OUT_RING  (chan, chan->vram.handle);
		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
		OUT_RING  (chan, upper_32_bits(virtual));
		OUT_RING  (chan, lower_32_bits(virtual));
		OUT_RING  (chan, sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
		OUT_RING  (chan, 0x00000000);
		FIRE_RING (chan);
	}
	return ret;
}

static int
nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
	int ret = RING_SPACE(chan, 7);
	if (ret == 0) {
		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
		OUT_RING  (chan, chan->vram.handle);
		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
		OUT_RING  (chan, upper_32_bits(virtual));
		OUT_RING  (chan, lower_32_bits(virtual));
		OUT_RING  (chan, sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
		FIRE_RING (chan);
	}
	return ret;
}

static int
nv84_fence_emit(struct nouveau_fence *fence)
{
	struct nouveau_channel *chan = fence->channel;
	struct nv84_fence_chan *fctx = chan->fence;
	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);
	u64 addr = fifo->chid * 16;

	if (fence->sysmem)
		addr += fctx->vma_gart.offset;
	else
		addr += fctx->vma.offset;

	return fctx->base.emit32(chan, addr, fence->sequence);
}

static int
nv84_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	struct nv84_fence_chan *fctx = chan->fence;
	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(prev);
	u64 addr = fifo->chid * 16;

	if (fence->sysmem)
		addr += fctx->vma_gart.offset;
	else
		addr += fctx->vma.offset;

	return fctx->base.sync32(chan, addr, fence->sequence);
}

static u32
nv84_fence_read(struct nouveau_channel *chan)
{
	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);
	struct nv84_fence_priv *priv = chan->drm->fence;
	return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4);
}

static void
nv84_fence_context_del(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->drm->dev;
	struct nv84_fence_priv *priv = chan->drm->fence;
	struct nv84_fence_chan *fctx = chan->fence;
	int i;

	for (i = 0; i < dev->mode_config.num_crtc; i++) {
		struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
		nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
	}

	nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
	nouveau_bo_vma_del(priv->bo, &fctx->vma);
	nouveau_fence_context_del(&fctx->base);
	chan->fence = NULL;
	kfree(fctx);
}

int
nv84_fence_context_new(struct nouveau_channel *chan)
{
	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);
	struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base);
	struct nv84_fence_priv *priv = chan->drm->fence;
	struct nv84_fence_chan *fctx;
	int ret, i;

	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);
	fctx->base.emit = nv84_fence_emit;
	fctx->base.sync = nv84_fence_sync;
	fctx->base.read = nv84_fence_read;
	fctx->base.emit32 = nv84_fence_emit32;
	fctx->base.sync32 = nv84_fence_sync32;

	ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
	if (ret == 0) {
		ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
					&fctx->vma_gart);
	}

	/* map display semaphore buffers into channel's vm */
	for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
		struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
		ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]);
	}

	nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000);

	if (ret)
		nv84_fence_context_del(chan);
	return ret;
}

static bool
nv84_fence_suspend(struct nouveau_drm *drm)
{
	struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
	struct nv84_fence_priv *priv = drm->fence;
	int i;

	priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
	if (priv->suspend) {
		for (i = 0; i <= pfifo->max; i++)
			priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
	}

	return priv->suspend != NULL;
}

static void
nv84_fence_resume(struct nouveau_drm *drm)
{
	struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
	struct nv84_fence_priv *priv = drm->fence;
	int i;

	if (priv->suspend) {
		for (i = 0; i <= pfifo->max; i++)
			nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
		vfree(priv->suspend);
		priv->suspend = NULL;
	}
}

static void
nv84_fence_destroy(struct nouveau_drm *drm)
{
	struct nv84_fence_priv *priv = drm->fence;
	nouveau_bo_unmap(priv->bo_gart);
	if (priv->bo_gart)
		nouveau_bo_unpin(priv->bo_gart);
	nouveau_bo_ref(NULL, &priv->bo_gart);
	nouveau_bo_unmap(priv->bo);
	if (priv->bo)
		nouveau_bo_unpin(priv->bo);
	nouveau_bo_ref(NULL, &priv->bo);
	drm->fence = NULL;
	kfree(priv);
}

int
nv84_fence_create(struct nouveau_drm *drm)
{
	struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
	struct nv84_fence_priv *priv;
	int ret;

	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base.dtor = nv84_fence_destroy;
	priv->base.suspend = nv84_fence_suspend;
	priv->base.resume = nv84_fence_resume;
	priv->base.context_new = nv84_fence_context_new;
	priv->base.context_del = nv84_fence_context_del;

	init_waitqueue_head(&priv->base.waiting);
	priv->base.uevent = true;

	ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
			     TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
	if (ret == 0) {
		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
		if (ret == 0) {
			ret = nouveau_bo_map(priv->bo);
			if (ret)
				nouveau_bo_unpin(priv->bo);
		}
		if (ret)
			nouveau_bo_ref(NULL, &priv->bo);
	}

	if (ret == 0)
		ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
				     TTM_PL_FLAG_TT, 0, 0, NULL,
				     &priv->bo_gart);
	if (ret == 0) {
		ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT);
		if (ret == 0) {
			ret = nouveau_bo_map(priv->bo_gart);
			if (ret)
				nouveau_bo_unpin(priv->bo_gart);
		}
		if (ret)
			nouveau_bo_ref(NULL, &priv->bo_gart);
	}

	if (ret)
		nv84_fence_destroy(drm);
	return ret;
}
Commit	Line	Data
5e120f6e BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
ebb945a9 BS	25	#include "nouveau_drm.h"
ebb945a9 BS	26	#include "nouveau_dma.h"
5e120f6e BS	27	#include "nouveau_fence.h"
5e120f6e BS	28
77145f1c BS	29	#include "nv50_display.h"
77145f1c BS	30
a34caf78 BS	31	u64
	32	nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
	33	{
	34	struct nv84_fence_chan *fctx = chan->fence;
	35	return fctx->dispc_vma[crtc].offset;
	36	}
5e120f6e BS	37
5e120f6e BS	38	static int
bba9852f	39	nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
5e120f6e	40	{
bba9852f	41	int ret = RING_SPACE(chan, 8);
5e120f6e BS	42	if (ret == 0) {
5e120f6e BS	43	BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
0ad72863	44	OUT_RING (chan, chan->vram.handle);
e18c080f	45	BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
bba9852f BS	46	OUT_RING (chan, upper_32_bits(virtual));
	47	OUT_RING (chan, lower_32_bits(virtual));
	48	OUT_RING (chan, sequence);
5e120f6e	49	OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
e18c080f	50	OUT_RING (chan, 0x00000000);
5e120f6e BS	51	FIRE_RING (chan);
	52	}
	53	return ret;
	54	}
	55
	56	static int
bba9852f	57	nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
5e120f6e	58	{
bba9852f	59	int ret = RING_SPACE(chan, 7);
5e120f6e BS	60	if (ret == 0) {
5e120f6e BS	61	BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
0ad72863	62	OUT_RING (chan, chan->vram.handle);
5e120f6e	63	BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
bba9852f BS	64	OUT_RING (chan, upper_32_bits(virtual));
	65	OUT_RING (chan, lower_32_bits(virtual));
	66	OUT_RING (chan, sequence);
5e120f6e BS	67	OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
	68	FIRE_RING (chan);
	69	}
	70	return ret;
	71	}
	72
264ce192	73	static int
bba9852f BS	74	nv84_fence_emit(struct nouveau_fence *fence)
	75	{
	76	struct nouveau_channel *chan = fence->channel;
bba9852f	77	struct nv84_fence_chan *fctx = chan->fence;
967e7bde	78	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);
264ce192 BS	79	u64 addr = fifo->chid * 16;
	80
	81	if (fence->sysmem)
	82	addr += fctx->vma_gart.offset;
	83	else
	84	addr += fctx->vma.offset;
	85
827520ce	86	return fctx->base.emit32(chan, addr, fence->sequence);
bba9852f BS	87	}
bba9852f BS	88
264ce192	89	static int
bba9852f BS	90	nv84_fence_sync(struct nouveau_fence *fence,
	91	struct nouveau_channel prev, struct nouveau_channel chan)
	92	{
bba9852f	93	struct nv84_fence_chan *fctx = chan->fence;
967e7bde	94	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(prev);
264ce192 BS	95	u64 addr = fifo->chid * 16;
	96
	97	if (fence->sysmem)
	98	addr += fctx->vma_gart.offset;
	99	else
	100	addr += fctx->vma.offset;
	101
827520ce	102	return fctx->base.sync32(chan, addr, fence->sequence);
bba9852f BS	103	}
bba9852f BS	104
264ce192	105	static u32
5e120f6e BS	106	nv84_fence_read(struct nouveau_channel *chan)
5e120f6e BS	107	{
967e7bde	108	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);
ebb945a9	109	struct nv84_fence_priv *priv = chan->drm->fence;
a34caf78	110	return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4);
5e120f6e BS	111	}
5e120f6e BS	112
264ce192	113	static void
e193b1d4	114	nv84_fence_context_del(struct nouveau_channel *chan)
5e120f6e	115	{
a34caf78 BS	116	struct drm_device *dev = chan->drm->dev;
a34caf78 BS	117	struct nv84_fence_priv *priv = chan->drm->fence;
e193b1d4	118	struct nv84_fence_chan *fctx = chan->fence;
a34caf78 BS	119	int i;
	120
	121	for (i = 0; i < dev->mode_config.num_crtc; i++) {
	122	struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
	123	nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
	124	}
	125
264ce192	126	nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
a34caf78	127	nouveau_bo_vma_del(priv->bo, &fctx->vma);
5e120f6e	128	nouveau_fence_context_del(&fctx->base);
e193b1d4	129	chan->fence = NULL;
5e120f6e BS	130	kfree(fctx);
	131	}
	132
a34caf78	133	int
e193b1d4	134	nv84_fence_context_new(struct nouveau_channel *chan)
5e120f6e	135	{
967e7bde	136	struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);
0ad72863	137	struct nouveau_cli cli = (void )nvif_client(&chan->device->base);
ebb945a9	138	struct nv84_fence_priv *priv = chan->drm->fence;
5e120f6e	139	struct nv84_fence_chan *fctx;
f589be88	140	int ret, i;
5e120f6e	141
e193b1d4	142	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
5e120f6e BS	143	if (!fctx)
	144	return -ENOMEM;
	145
	146	nouveau_fence_context_new(&fctx->base);
827520ce BS	147	fctx->base.emit = nv84_fence_emit;
	148	fctx->base.sync = nv84_fence_sync;
	149	fctx->base.read = nv84_fence_read;
	150	fctx->base.emit32 = nv84_fence_emit32;
	151	fctx->base.sync32 = nv84_fence_sync32;
5e120f6e	152
3ee6f5b5	153	ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
264ce192	154	if (ret == 0) {
3ee6f5b5	155	ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
264ce192 BS	156	&fctx->vma_gart);
264ce192 BS	157	}
ebb945a9	158
a34caf78 BS	159	/* map display semaphore buffers into channel's vm */
	160	for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
	161	struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
3ee6f5b5	162	ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]);
f589be88 BS	163	}
f589be88 BS	164
a34caf78	165	nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000);
264ce192 BS	166
	167	if (ret)
	168	nv84_fence_context_del(chan);
5e120f6e BS	169	return ret;
	170	}
	171
264ce192	172	static bool
a34caf78 BS	173	nv84_fence_suspend(struct nouveau_drm *drm)
a34caf78 BS	174	{
967e7bde	175	struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
a34caf78 BS	176	struct nv84_fence_priv *priv = drm->fence;
	177	int i;
	178
	179	priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
	180	if (priv->suspend) {
	181	for (i = 0; i <= pfifo->max; i++)
	182	priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
	183	}
	184
	185	return priv->suspend != NULL;
	186	}
	187
264ce192	188	static void
a34caf78 BS	189	nv84_fence_resume(struct nouveau_drm *drm)
a34caf78 BS	190	{
967e7bde	191	struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
a34caf78 BS	192	struct nv84_fence_priv *priv = drm->fence;
	193	int i;
	194
	195	if (priv->suspend) {
	196	for (i = 0; i <= pfifo->max; i++)
	197	nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
	198	vfree(priv->suspend);
	199	priv->suspend = NULL;
	200	}
	201	}
	202
264ce192	203	static void
ebb945a9	204	nv84_fence_destroy(struct nouveau_drm *drm)
5e120f6e	205	{
ebb945a9	206	struct nv84_fence_priv *priv = drm->fence;
264ce192 BS	207	nouveau_bo_unmap(priv->bo_gart);
	208	if (priv->bo_gart)
	209	nouveau_bo_unpin(priv->bo_gart);
	210	nouveau_bo_ref(NULL, &priv->bo_gart);
a34caf78 BS	211	nouveau_bo_unmap(priv->bo);
	212	if (priv->bo)
	213	nouveau_bo_unpin(priv->bo);
	214	nouveau_bo_ref(NULL, &priv->bo);
ebb945a9	215	drm->fence = NULL;
5e120f6e BS	216	kfree(priv);
	217	}
	218
	219	int
ebb945a9	220	nv84_fence_create(struct nouveau_drm *drm)
5e120f6e	221	{
967e7bde	222	struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
5e120f6e BS	223	struct nv84_fence_priv *priv;
	224	int ret;
	225
ebb945a9	226	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
5e120f6e BS	227	if (!priv)
	228	return -ENOMEM;
	229
e193b1d4	230	priv->base.dtor = nv84_fence_destroy;
a34caf78 BS	231	priv->base.suspend = nv84_fence_suspend;
a34caf78 BS	232	priv->base.resume = nv84_fence_resume;
e193b1d4 BS	233	priv->base.context_new = nv84_fence_context_new;
e193b1d4 BS	234	priv->base.context_del = nv84_fence_context_del;
5e120f6e	235
e18c080f BS	236	init_waitqueue_head(&priv->base.waiting);
	237	priv->base.uevent = true;
	238
a34caf78 BS	239	ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
	240	TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
	241	if (ret == 0) {
	242	ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
	243	if (ret == 0) {
	244	ret = nouveau_bo_map(priv->bo);
	245	if (ret)
	246	nouveau_bo_unpin(priv->bo);
	247	}
	248	if (ret)
	249	nouveau_bo_ref(NULL, &priv->bo);
	250	}
	251
264ce192 BS	252	if (ret == 0)
	253	ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
	254	TTM_PL_FLAG_TT, 0, 0, NULL,
	255	&priv->bo_gart);
	256	if (ret == 0) {
	257	ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT);
	258	if (ret == 0) {
	259	ret = nouveau_bo_map(priv->bo_gart);
	260	if (ret)
	261	nouveau_bo_unpin(priv->bo_gart);
	262	}
	263	if (ret)
	264	nouveau_bo_ref(NULL, &priv->bo_gart);
	265	}
	266
5e120f6e	267	if (ret)
ebb945a9	268	nv84_fence_destroy(drm);
5e120f6e BS	269	return ret;
5e120f6e BS	270	}