treewide: Use array_size() in vmalloc()
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nv84_fence.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
4dc28134 25#include "nouveau_drv.h"
ebb945a9 26#include "nouveau_dma.h"
5e120f6e 27#include "nouveau_fence.h"
24e8375b 28#include "nouveau_vmm.h"
5e120f6e 29
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30#include "nv50_display.h"
31
5e120f6e 32static int
bba9852f 33nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
5e120f6e 34{
bba9852f 35 int ret = RING_SPACE(chan, 8);
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36 if (ret == 0) {
37 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
0ad72863 38 OUT_RING (chan, chan->vram.handle);
e18c080f 39 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
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40 OUT_RING (chan, upper_32_bits(virtual));
41 OUT_RING (chan, lower_32_bits(virtual));
42 OUT_RING (chan, sequence);
5e120f6e 43 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
e18c080f 44 OUT_RING (chan, 0x00000000);
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45 FIRE_RING (chan);
46 }
47 return ret;
48}
49
50static int
bba9852f 51nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
5e120f6e 52{
bba9852f 53 int ret = RING_SPACE(chan, 7);
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54 if (ret == 0) {
55 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
0ad72863 56 OUT_RING (chan, chan->vram.handle);
5e120f6e 57 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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58 OUT_RING (chan, upper_32_bits(virtual));
59 OUT_RING (chan, lower_32_bits(virtual));
60 OUT_RING (chan, sequence);
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61 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
62 FIRE_RING (chan);
63 }
64 return ret;
65}
66
264ce192 67static int
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68nv84_fence_emit(struct nouveau_fence *fence)
69{
70 struct nouveau_channel *chan = fence->channel;
bba9852f 71 struct nv84_fence_chan *fctx = chan->fence;
24e8375b 72 u64 addr = fctx->vma->addr + chan->chid * 16;
264ce192 73
29ba89b2 74 return fctx->base.emit32(chan, addr, fence->base.seqno);
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75}
76
264ce192 77static int
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78nv84_fence_sync(struct nouveau_fence *fence,
79 struct nouveau_channel *prev, struct nouveau_channel *chan)
80{
bba9852f 81 struct nv84_fence_chan *fctx = chan->fence;
24e8375b 82 u64 addr = fctx->vma->addr + prev->chid * 16;
264ce192 83
29ba89b2 84 return fctx->base.sync32(chan, addr, fence->base.seqno);
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85}
86
264ce192 87static u32
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88nv84_fence_read(struct nouveau_channel *chan)
89{
ebb945a9 90 struct nv84_fence_priv *priv = chan->drm->fence;
bbf8906b 91 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
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92}
93
264ce192 94static void
e193b1d4 95nv84_fence_context_del(struct nouveau_channel *chan)
5e120f6e 96{
a34caf78 97 struct nv84_fence_priv *priv = chan->drm->fence;
e193b1d4 98 struct nv84_fence_chan *fctx = chan->fence;
a34caf78 99
1dadba87 100 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
96692b09 101 mutex_lock(&priv->mutex);
24e8375b 102 nouveau_vma_del(&fctx->vma);
96692b09 103 mutex_unlock(&priv->mutex);
5e120f6e 104 nouveau_fence_context_del(&fctx->base);
e193b1d4 105 chan->fence = NULL;
15a996bb 106 nouveau_fence_context_free(&fctx->base);
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107}
108
a34caf78 109int
e193b1d4 110nv84_fence_context_new(struct nouveau_channel *chan)
5e120f6e 111{
a01ca78c 112 struct nouveau_cli *cli = (void *)chan->user.client;
ebb945a9 113 struct nv84_fence_priv *priv = chan->drm->fence;
5e120f6e 114 struct nv84_fence_chan *fctx;
e1ef6b42 115 int ret;
5e120f6e 116
e193b1d4 117 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
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118 if (!fctx)
119 return -ENOMEM;
120
29ba89b2 121 nouveau_fence_context_new(chan, &fctx->base);
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122 fctx->base.emit = nv84_fence_emit;
123 fctx->base.sync = nv84_fence_sync;
124 fctx->base.read = nv84_fence_read;
125 fctx->base.emit32 = nv84_fence_emit32;
126 fctx->base.sync32 = nv84_fence_sync32;
29ba89b2 127 fctx->base.sequence = nv84_fence_read(chan);
5e120f6e 128
96692b09 129 mutex_lock(&priv->mutex);
24e8375b 130 ret = nouveau_vma_new(priv->bo, &cli->vmm, &fctx->vma);
96692b09 131 mutex_unlock(&priv->mutex);
ebb945a9 132
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133 if (ret)
134 nv84_fence_context_del(chan);
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135 return ret;
136}
137
264ce192 138static bool
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139nv84_fence_suspend(struct nouveau_drm *drm)
140{
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141 struct nv84_fence_priv *priv = drm->fence;
142 int i;
143
42bc47b3 144 priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan.nr));
a34caf78 145 if (priv->suspend) {
eb47db4f 146 for (i = 0; i < drm->chan.nr; i++)
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147 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
148 }
149
150 return priv->suspend != NULL;
151}
152
264ce192 153static void
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154nv84_fence_resume(struct nouveau_drm *drm)
155{
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156 struct nv84_fence_priv *priv = drm->fence;
157 int i;
158
159 if (priv->suspend) {
eb47db4f 160 for (i = 0; i < drm->chan.nr; i++)
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161 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
162 vfree(priv->suspend);
163 priv->suspend = NULL;
164 }
165}
166
264ce192 167static void
ebb945a9 168nv84_fence_destroy(struct nouveau_drm *drm)
5e120f6e 169{
ebb945a9 170 struct nv84_fence_priv *priv = drm->fence;
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171 nouveau_bo_unmap(priv->bo);
172 if (priv->bo)
173 nouveau_bo_unpin(priv->bo);
174 nouveau_bo_ref(NULL, &priv->bo);
ebb945a9 175 drm->fence = NULL;
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176 kfree(priv);
177}
178
179int
ebb945a9 180nv84_fence_create(struct nouveau_drm *drm)
5e120f6e 181{
5e120f6e 182 struct nv84_fence_priv *priv;
eaecf032 183 u32 domain;
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184 int ret;
185
ebb945a9 186 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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187 if (!priv)
188 return -ENOMEM;
189
e193b1d4 190 priv->base.dtor = nv84_fence_destroy;
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191 priv->base.suspend = nv84_fence_suspend;
192 priv->base.resume = nv84_fence_resume;
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193 priv->base.context_new = nv84_fence_context_new;
194 priv->base.context_del = nv84_fence_context_del;
5e120f6e 195
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196 priv->base.uevent = true;
197
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198 mutex_init(&priv->mutex);
199
eaecf032 200 /* Use VRAM if there is any ; otherwise fallback to system memory */
1167c6bc 201 domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
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202 /*
203 * fences created in sysmem must be non-cached or we
204 * will lose CPU/GPU coherency!
205 */
206 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
eb47db4f 207 ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0,
bab7cc18 208 domain, 0, 0, NULL, NULL, &priv->bo);
a34caf78 209 if (ret == 0) {
eaecf032 210 ret = nouveau_bo_pin(priv->bo, domain, false);
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211 if (ret == 0) {
212 ret = nouveau_bo_map(priv->bo);
213 if (ret)
214 nouveau_bo_unpin(priv->bo);
215 }
216 if (ret)
217 nouveau_bo_ref(NULL, &priv->bo);
218 }
219
5e120f6e 220 if (ret)
ebb945a9 221 nv84_fence_destroy(drm);
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222 return ret;
223}