[linux-block.git] / drivers / gpu / drm / nouveau / nv50_graph.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"

#include "nouveau_grctx.h"

#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)

static void
nv50_graph_init_reset(struct drm_device *dev)
{
	uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);

	NV_DEBUG(dev, "\n");

	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
}

static void
nv50_graph_init_intr(struct drm_device *dev)
{
	NV_DEBUG(dev, "\n");

	nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
	nv_wr32(dev, 0x400138, 0xffffffff);
	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
}

static void
nv50_graph_init_regs__nv(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t units = nv_rd32(dev, 0x1540);
	int i;

	NV_DEBUG(dev, "\n");

	nv_wr32(dev, 0x400804, 0xc0000000);
	nv_wr32(dev, 0x406800, 0xc0000000);
	nv_wr32(dev, 0x400c04, 0xc0000000);
	nv_wr32(dev, 0x401800, 0xc0000000);
	nv_wr32(dev, 0x405018, 0xc0000000);
	nv_wr32(dev, 0x402000, 0xc0000000);

	for (i = 0; i < 16; i++) {
		if (units & 1 << i) {
			if (dev_priv->chipset < 0xa0) {
				nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
				nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
				nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
			} else {
				nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
				nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
				nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
			}
		}
	}

	nv_wr32(dev, 0x400108, 0xffffffff);

	nv_wr32(dev, 0x400824, 0x00004000);
	nv_wr32(dev, 0x400500, 0x00010001);
}

static void
nv50_graph_init_regs(struct drm_device *dev)
{
	NV_DEBUG(dev, "\n");

	nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
				(1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
	nv_wr32(dev, 0x402ca8, 0x800);
}

static int
nv50_graph_init_ctxctl(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	NV_DEBUG(dev, "\n");

	if (nouveau_ctxfw) {
		nouveau_grctx_prog_load(dev);
		dev_priv->engine.graph.grctx_size = 0x70000;
	}
	if (!dev_priv->engine.graph.ctxprog) {
		struct nouveau_grctx ctx = {};
		uint32_t *cp = kmalloc(512 * 4, GFP_KERNEL);
		int i;
		if (!cp) {
			NV_ERROR(dev, "Couldn't alloc ctxprog! Disabling acceleration.\n");
			dev_priv->engine.graph.accel_blocked = true;
			return 0;
		}
		ctx.dev = dev;
		ctx.mode = NOUVEAU_GRCTX_PROG;
		ctx.data = cp;
		ctx.ctxprog_max = 512;
		if (!nv50_grctx_init(&ctx)) {
			dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;

			nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
			for (i = 0; i < ctx.ctxprog_len; i++)
				nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
		} else {
			dev_priv->engine.graph.accel_blocked = true;
		}
		kfree(cp);
	}

	nv_wr32(dev, 0x400320, 4);
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
	return 0;
}

int
nv50_graph_init(struct drm_device *dev)
{
	int ret;

	NV_DEBUG(dev, "\n");

	nv50_graph_init_reset(dev);
	nv50_graph_init_regs__nv(dev);
	nv50_graph_init_regs(dev);
	nv50_graph_init_intr(dev);

	ret = nv50_graph_init_ctxctl(dev);
	if (ret)
		return ret;

	return 0;
}

void
nv50_graph_takedown(struct drm_device *dev)
{
	NV_DEBUG(dev, "\n");
	nouveau_grctx_fini(dev);
}

void
nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
{
	const uint32_t mask = 0x00010001;

	if (enabled)
		nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
	else
		nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
}

struct nouveau_channel *
nv50_graph_channel(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t inst;
	int i;

	/* Be sure we're not in the middle of a context switch or bad things
	 * will happen, such as unloading the wrong pgraph context.
	 */
	if (!nv_wait(0x400300, 0x00000001, 0x00000000))
		NV_ERROR(dev, "Ctxprog is still running\n");

	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
		return NULL;
	inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->fifos[i];

		if (chan && chan->ramin && chan->ramin->instance == inst)
			return chan;
	}

	return NULL;
}

int
nv50_graph_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
	struct nouveau_gpuobj *obj;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	int hdr, ret;

	NV_DEBUG(dev, "ch%d\n", chan->id);

	ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
				     0x1000, NVOBJ_FLAG_ZERO_ALLOC |
				     NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
	if (ret)
		return ret;
	obj = chan->ramin_grctx->gpuobj;

	hdr = IS_G80 ? 0x200 : 0x20;
	nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002);
	nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
					   pgraph->grctx_size - 1);
	nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
	nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0);
	nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
	nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000);

	if (!pgraph->ctxprog) {
		struct nouveau_grctx ctx = {};
		ctx.dev = chan->dev;
		ctx.mode = NOUVEAU_GRCTX_VALS;
		ctx.data = obj;
		nv50_grctx_init(&ctx);
	} else {
		nouveau_grctx_vals_load(dev, obj);
	}
	nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);

	dev_priv->engine.instmem.flush(dev);
	return 0;
}

void
nv50_graph_destroy_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i, hdr = IS_G80 ? 0x200 : 0x20;

	NV_DEBUG(dev, "ch%d\n", chan->id);

	if (!chan->ramin || !chan->ramin->gpuobj)
		return;

	for (i = hdr; i < hdr + 24; i += 4)
		nv_wo32(dev, chan->ramin->gpuobj, i/4, 0);
	dev_priv->engine.instmem.flush(dev);

	nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
}

static int
nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
{
	uint32_t fifo = nv_rd32(dev, 0x400500);

	nv_wr32(dev, 0x400500, fifo & ~1);
	nv_wr32(dev, 0x400784, inst);
	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
	nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
	nv_wr32(dev, 0x400040, 0xffffffff);
	(void)nv_rd32(dev, 0x400040);
	nv_wr32(dev, 0x400040, 0x00000000);
	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);

	if (nouveau_wait_for_idle(dev))
		nv_wr32(dev, 0x40032c, inst | (1<<31));
	nv_wr32(dev, 0x400500, fifo);

	return 0;
}

int
nv50_graph_load_context(struct nouveau_channel *chan)
{
	uint32_t inst = chan->ramin->instance >> 12;

	NV_DEBUG(chan->dev, "ch%d\n", chan->id);
	return nv50_graph_do_load_context(chan->dev, inst);
}

int
nv50_graph_unload_context(struct drm_device *dev)
{
	uint32_t inst;

	inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
		return 0;
	inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;

	nouveau_wait_for_idle(dev);
	nv_wr32(dev, 0x400784, inst);
	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
	nouveau_wait_for_idle(dev);

	nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
	return 0;
}

void
nv50_graph_context_switch(struct drm_device *dev)
{
	uint32_t inst;

	nv50_graph_unload_context(dev);

	inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
	inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
	nv50_graph_do_load_context(dev, inst);

	nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
		NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
}

static int
nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass,
			   int mthd, uint32_t data)
{
	struct nouveau_gpuobj_ref *ref = NULL;

	if (nouveau_gpuobj_ref_find(chan, data, &ref))
		return -ENOENT;

	if (nouveau_notifier_offset(ref->gpuobj, NULL))
		return -EINVAL;

	chan->nvsw.vblsem = ref->gpuobj;
	chan->nvsw.vblsem_offset = ~0;
	return 0;
}

static int
nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, int grclass,
			      int mthd, uint32_t data)
{
	if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
		return -ERANGE;

	chan->nvsw.vblsem_offset = data >> 2;
	return 0;
}

static int
nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, int grclass,
				   int mthd, uint32_t data)
{
	chan->nvsw.vblsem_rval = data;
	return 0;
}

static int
nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, int grclass,
			       int mthd, uint32_t data)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
		return -EINVAL;

	if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN) &
		      NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data))) {
		nv_wr32(dev, NV50_PDISPLAY_INTR_1,
			NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data));
		nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
			NV50_PDISPLAY_INTR_EN) |
			NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data));
	}

	list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
	return 0;
}

static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = {
	{ 0x018c, nv50_graph_nvsw_dma_vblsem },
	{ 0x0400, nv50_graph_nvsw_vblsem_offset },
	{ 0x0404, nv50_graph_nvsw_vblsem_release_val },
	{ 0x0408, nv50_graph_nvsw_vblsem_release },
	{}
};

struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
	{ 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */
	{ 0x0030, false, NULL }, /* null */
	{ 0x5039, false, NULL }, /* m2mf */
	{ 0x502d, false, NULL }, /* 2d */
	{ 0x50c0, false, NULL }, /* compute */
	{ 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */
	{ 0x5097, false, NULL }, /* tesla (nv50) */
	{ 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */
	{ 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */
	{ 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
	{}
};
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
	30
d5f3c90d	31	#include "nouveau_grctx.h"
6ee73861 BS	32
	33	#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
	34
	35	static void
	36	nv50_graph_init_reset(struct drm_device *dev)
	37	{
	38	uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH \| (1 << 21);
	39
	40	NV_DEBUG(dev, "\n");
	41
	42	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
	43	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \| pmc_e);
	44	}
	45
	46	static void
	47	nv50_graph_init_intr(struct drm_device *dev)
	48	{
	49	NV_DEBUG(dev, "\n");
	50
	51	nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
	52	nv_wr32(dev, 0x400138, 0xffffffff);
	53	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
	54	}
	55
	56	static void
	57	nv50_graph_init_regs__nv(struct drm_device *dev)
	58	{
304424e1 MK	59	struct drm_nouveau_private *dev_priv = dev->dev_private;
	60	uint32_t units = nv_rd32(dev, 0x1540);
	61	int i;
	62
6ee73861 BS	63	NV_DEBUG(dev, "\n");
	64
	65	nv_wr32(dev, 0x400804, 0xc0000000);
	66	nv_wr32(dev, 0x406800, 0xc0000000);
	67	nv_wr32(dev, 0x400c04, 0xc0000000);
716abaa8	68	nv_wr32(dev, 0x401800, 0xc0000000);
6ee73861 BS	69	nv_wr32(dev, 0x405018, 0xc0000000);
	70	nv_wr32(dev, 0x402000, 0xc0000000);
	71
304424e1 MK	72	for (i = 0; i < 16; i++) {
	73	if (units & 1 << i) {
	74	if (dev_priv->chipset < 0xa0) {
	75	nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
	76	nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
	77	nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
	78	} else {
	79	nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
	80	nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
	81	nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
	82	}
	83	}
	84	}
	85
6ee73861 BS	86	nv_wr32(dev, 0x400108, 0xffffffff);
	87
	88	nv_wr32(dev, 0x400824, 0x00004000);
	89	nv_wr32(dev, 0x400500, 0x00010001);
	90	}
	91
	92	static void
	93	nv50_graph_init_regs(struct drm_device *dev)
	94	{
	95	NV_DEBUG(dev, "\n");
	96
	97	nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
	98	(1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
	99	nv_wr32(dev, 0x402ca8, 0x800);
	100	}
	101
	102	static int
	103	nv50_graph_init_ctxctl(struct drm_device *dev)
	104	{
054b93e4 BS	105	struct drm_nouveau_private *dev_priv = dev->dev_private;
054b93e4 BS	106
6ee73861 BS	107	NV_DEBUG(dev, "\n");
6ee73861 BS	108
d5f3c90d MK	109	if (nouveau_ctxfw) {
	110	nouveau_grctx_prog_load(dev);
	111	dev_priv->engine.graph.grctx_size = 0x70000;
	112	}
	113	if (!dev_priv->engine.graph.ctxprog) {
	114	struct nouveau_grctx ctx = {};
	115	uint32_t cp = kmalloc(512 4, GFP_KERNEL);
	116	int i;
	117	if (!cp) {
	118	NV_ERROR(dev, "Couldn't alloc ctxprog! Disabling acceleration.\n");
	119	dev_priv->engine.graph.accel_blocked = true;
	120	return 0;
	121	}
	122	ctx.dev = dev;
	123	ctx.mode = NOUVEAU_GRCTX_PROG;
	124	ctx.data = cp;
	125	ctx.ctxprog_max = 512;
	126	if (!nv50_grctx_init(&ctx)) {
	127	dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
	128
	129	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	130	for (i = 0; i < ctx.ctxprog_len; i++)
	131	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
	132	} else {
	133	dev_priv->engine.graph.accel_blocked = true;
	134	}
	135	kfree(cp);
	136	}
6ee73861 BS	137
	138	nv_wr32(dev, 0x400320, 4);
	139	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
	140	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
	141	return 0;
	142	}
	143
	144	int
	145	nv50_graph_init(struct drm_device *dev)
	146	{
	147	int ret;
	148
	149	NV_DEBUG(dev, "\n");
	150
	151	nv50_graph_init_reset(dev);
	152	nv50_graph_init_regs__nv(dev);
	153	nv50_graph_init_regs(dev);
	154	nv50_graph_init_intr(dev);
	155
	156	ret = nv50_graph_init_ctxctl(dev);
	157	if (ret)
	158	return ret;
	159
	160	return 0;
	161	}
	162
	163	void
	164	nv50_graph_takedown(struct drm_device *dev)
	165	{
	166	NV_DEBUG(dev, "\n");
054b93e4	167	nouveau_grctx_fini(dev);
6ee73861 BS	168	}
	169
	170	void
	171	nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
	172	{
	173	const uint32_t mask = 0x00010001;
	174
	175	if (enabled)
	176	nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) \| mask);
	177	else
	178	nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
	179	}
	180
	181	struct nouveau_channel *
	182	nv50_graph_channel(struct drm_device *dev)
	183	{
	184	struct drm_nouveau_private *dev_priv = dev->dev_private;
	185	uint32_t inst;
	186	int i;
	187
a51a3bf5 MM	188	/* Be sure we're not in the middle of a context switch or bad things
	189	* will happen, such as unloading the wrong pgraph context.
	190	*/
	191	if (!nv_wait(0x400300, 0x00000001, 0x00000000))
	192	NV_ERROR(dev, "Ctxprog is still running\n");
	193
6ee73861 BS	194	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	195	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
	196	return NULL;
	197	inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
	198
	199	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
	200	struct nouveau_channel *chan = dev_priv->fifos[i];
	201
	202	if (chan && chan->ramin && chan->ramin->instance == inst)
	203	return chan;
	204	}
	205
	206	return NULL;
	207	}
	208
	209	int
	210	nv50_graph_create_context(struct nouveau_channel *chan)
	211	{
	212	struct drm_device *dev = chan->dev;
	213	struct drm_nouveau_private *dev_priv = dev->dev_private;
	214	struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
6e86e041	215	struct nouveau_gpuobj *obj;
d5f3c90d	216	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
6ee73861 BS	217	int hdr, ret;
	218
	219	NV_DEBUG(dev, "ch%d\n", chan->id);
	220
d5f3c90d MK	221	ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
d5f3c90d MK	222	0x1000, NVOBJ_FLAG_ZERO_ALLOC \|
6ee73861 BS	223	NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
	224	if (ret)
	225	return ret;
6e86e041	226	obj = chan->ramin_grctx->gpuobj;
6ee73861 BS	227
6ee73861 BS	228	hdr = IS_G80 ? 0x200 : 0x20;
6ee73861 BS	229	nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002);
6ee73861 BS	230	nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
d5f3c90d	231	pgraph->grctx_size - 1);
6ee73861 BS	232	nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
	233	nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0);
	234	nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
	235	nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000);
6ee73861	236
d5f3c90d MK	237	if (!pgraph->ctxprog) {
	238	struct nouveau_grctx ctx = {};
	239	ctx.dev = chan->dev;
	240	ctx.mode = NOUVEAU_GRCTX_VALS;
6e86e041	241	ctx.data = obj;
d5f3c90d MK	242	nv50_grctx_init(&ctx);
d5f3c90d MK	243	} else {
6e86e041	244	nouveau_grctx_vals_load(dev, obj);
d5f3c90d	245	}
6e86e041	246	nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);
6ee73861	247
f56cb86f	248	dev_priv->engine.instmem.flush(dev);
6ee73861 BS	249	return 0;
	250	}
	251
	252	void
	253	nv50_graph_destroy_context(struct nouveau_channel *chan)
	254	{
	255	struct drm_device *dev = chan->dev;
	256	struct drm_nouveau_private *dev_priv = dev->dev_private;
	257	int i, hdr = IS_G80 ? 0x200 : 0x20;
	258
	259	NV_DEBUG(dev, "ch%d\n", chan->id);
	260
	261	if (!chan->ramin \|\| !chan->ramin->gpuobj)
	262	return;
	263
6ee73861 BS	264	for (i = hdr; i < hdr + 24; i += 4)
6ee73861 BS	265	nv_wo32(dev, chan->ramin->gpuobj, i/4, 0);
f56cb86f	266	dev_priv->engine.instmem.flush(dev);
6ee73861 BS	267
	268	nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
	269	}
	270
	271	static int
	272	nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
	273	{
	274	uint32_t fifo = nv_rd32(dev, 0x400500);
	275
	276	nv_wr32(dev, 0x400500, fifo & ~1);
	277	nv_wr32(dev, 0x400784, inst);
	278	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) \| 0x40);
	279	nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) \| 0x11);
	280	nv_wr32(dev, 0x400040, 0xffffffff);
	281	(void)nv_rd32(dev, 0x400040);
	282	nv_wr32(dev, 0x400040, 0x00000000);
	283	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) \| 1);
	284
	285	if (nouveau_wait_for_idle(dev))
	286	nv_wr32(dev, 0x40032c, inst \| (1<<31));
	287	nv_wr32(dev, 0x400500, fifo);
	288
	289	return 0;
	290	}
	291
	292	int
	293	nv50_graph_load_context(struct nouveau_channel *chan)
	294	{
	295	uint32_t inst = chan->ramin->instance >> 12;
	296
	297	NV_DEBUG(chan->dev, "ch%d\n", chan->id);
	298	return nv50_graph_do_load_context(chan->dev, inst);
	299	}
	300
	301	int
	302	nv50_graph_unload_context(struct drm_device *dev)
	303	{
a51a3bf5	304	uint32_t inst;
6ee73861 BS	305
	306	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	307	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
	308	return 0;
	309	inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
	310
0a90dc51	311	nouveau_wait_for_idle(dev);
6ee73861 BS	312	nv_wr32(dev, 0x400784, inst);
	313	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) \| 0x20);
	314	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) \| 0x01);
	315	nouveau_wait_for_idle(dev);
6ee73861 BS	316
	317	nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
	318	return 0;
	319	}
	320
	321	void
	322	nv50_graph_context_switch(struct drm_device *dev)
	323	{
	324	uint32_t inst;
	325
	326	nv50_graph_unload_context(dev);
	327
	328	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
	329	inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
	330	nv50_graph_do_load_context(dev, inst);
	331
	332	nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
	333	NV40_PGRAPH_INTR_EN) \| NV_PGRAPH_INTR_CONTEXT_SWITCH);
	334	}
	335
	336	static int
	337	nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass,
	338	int mthd, uint32_t data)
	339	{
	340	struct nouveau_gpuobj_ref *ref = NULL;
	341
	342	if (nouveau_gpuobj_ref_find(chan, data, &ref))
	343	return -ENOENT;
	344
	345	if (nouveau_notifier_offset(ref->gpuobj, NULL))
	346	return -EINVAL;
	347
	348	chan->nvsw.vblsem = ref->gpuobj;
	349	chan->nvsw.vblsem_offset = ~0;
	350	return 0;
	351	}
	352
	353	static int
	354	nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, int grclass,
	355	int mthd, uint32_t data)
	356	{
	357	if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
	358	return -ERANGE;
	359
	360	chan->nvsw.vblsem_offset = data >> 2;
	361	return 0;
	362	}
	363
	364	static int
	365	nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, int grclass,
	366	int mthd, uint32_t data)
	367	{
	368	chan->nvsw.vblsem_rval = data;
	369	return 0;
	370	}
	371
	372	static int
	373	nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, int grclass,
	374	int mthd, uint32_t data)
	375	{
	376	struct drm_device *dev = chan->dev;
	377	struct drm_nouveau_private *dev_priv = dev->dev_private;
	378
	379	if (!chan->nvsw.vblsem \|\| chan->nvsw.vblsem_offset == ~0 \|\| data > 1)
380	return -EINVAL;
381
382	if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN) &
383	NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data))) {
384	nv_wr32(dev, NV50_PDISPLAY_INTR_1,
385	NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data));
386	nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
387	NV50_PDISPLAY_INTR_EN) \|
388	NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data));
389	}
390
391	list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
392	return 0;
393	}
394
395	static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = {
396	{ 0x018c, nv50_graph_nvsw_dma_vblsem },
397	{ 0x0400, nv50_graph_nvsw_vblsem_offset },
398	{ 0x0404, nv50_graph_nvsw_vblsem_release_val },
399	{ 0x0408, nv50_graph_nvsw_vblsem_release },
400	{}
401	};
402
403	struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
404	{ 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */
405	{ 0x0030, false, NULL }, /* null */
406	{ 0x5039, false, NULL }, /* m2mf */
407	{ 0x502d, false, NULL }, /* 2d */
408	{ 0x50c0, false, NULL }, /* compute */
d327dd4e	409	{ 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */
6ee73861	410	{ 0x5097, false, NULL }, /* tesla (nv50) */
d327dd4e MK	411	{ 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */
	412	{ 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */
	413	{ 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
6ee73861 BS	414	{}
6ee73861 BS	415	};