Commit | Line | Data |
---|---|---|
45284162 BS |
1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
6c06d608 | 25 | #include <linux/dmi.h> |
760285e7 | 26 | #include <drm/drmP.h> |
45284162 BS |
27 | #include "nouveau_drv.h" |
28 | #include "nouveau_hw.h" | |
a0b25635 | 29 | #include "nouveau_gpio.h" |
45284162 | 30 | |
19b7fc7b BS |
31 | #include "nv50_display.h" |
32 | ||
45284162 | 33 | static int |
a0b25635 | 34 | nv50_gpio_location(int line, u32 *reg, u32 *shift) |
45284162 BS |
35 | { |
36 | const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; | |
37 | ||
a0b25635 | 38 | if (line >= 32) |
45284162 BS |
39 | return -EINVAL; |
40 | ||
a0b25635 BS |
41 | *reg = nv50_gpio_reg[line >> 3]; |
42 | *shift = (line & 7) << 2; | |
45284162 BS |
43 | return 0; |
44 | } | |
45 | ||
46 | int | |
a0b25635 | 47 | nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out) |
45284162 | 48 | { |
a0b25635 | 49 | u32 reg, shift; |
45284162 | 50 | |
a0b25635 | 51 | if (nv50_gpio_location(line, ®, &shift)) |
45284162 BS |
52 | return -EINVAL; |
53 | ||
a0b25635 BS |
54 | nv_mask(dev, reg, 7 << shift, (((dir ^ 1) << 1) | out) << shift); |
55 | return 0; | |
45284162 BS |
56 | } |
57 | ||
58 | int | |
a0b25635 | 59 | nv50_gpio_sense(struct drm_device *dev, int line) |
45284162 | 60 | { |
a0b25635 | 61 | u32 reg, shift; |
45284162 | 62 | |
a0b25635 | 63 | if (nv50_gpio_location(line, ®, &shift)) |
45284162 BS |
64 | return -EINVAL; |
65 | ||
a0b25635 | 66 | return !!(nv_rd32(dev, reg) & (4 << shift)); |
45284162 | 67 | } |
d0875edd | 68 | |
a0b25635 BS |
69 | void |
70 | nv50_gpio_irq_enable(struct drm_device *dev, int line, bool on) | |
d7f8172c | 71 | { |
a0b25635 BS |
72 | u32 reg = line < 16 ? 0xe050 : 0xe070; |
73 | u32 mask = 0x00010001 << (line & 0xf); | |
d7f8172c | 74 | |
a0b25635 BS |
75 | nv_wr32(dev, reg + 4, mask); |
76 | nv_mask(dev, reg + 0, mask, on ? mask : 0); | |
d7f8172c BS |
77 | } |
78 | ||
79 | int | |
a0b25635 | 80 | nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out) |
d7f8172c | 81 | { |
a0b25635 BS |
82 | u32 data = ((dir ^ 1) << 13) | (out << 12); |
83 | nv_mask(dev, 0x00d610 + (line * 4), 0x00003000, data); | |
84 | nv_mask(dev, 0x00d604, 0x00000001, 0x00000001); /* update? */ | |
d7f8172c BS |
85 | return 0; |
86 | } | |
87 | ||
fce2bad0 | 88 | int |
a0b25635 | 89 | nvd0_gpio_sense(struct drm_device *dev, int line) |
fce2bad0 | 90 | { |
a0b25635 | 91 | return !!(nv_rd32(dev, 0x00d610 + (line * 4)) & 0x00004000); |
fce2bad0 BS |
92 | } |
93 | ||
a0b25635 BS |
94 | static void |
95 | nv50_gpio_isr(struct drm_device *dev) | |
fce2bad0 BS |
96 | { |
97 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a0b25635 BS |
98 | u32 intr0, intr1 = 0; |
99 | u32 hi, lo; | |
fce2bad0 | 100 | |
a0b25635 BS |
101 | intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050); |
102 | if (dev_priv->chipset >= 0x90) | |
103 | intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070); | |
fce2bad0 | 104 | |
a0b25635 BS |
105 | hi = (intr0 & 0x0000ffff) | (intr1 << 16); |
106 | lo = (intr0 >> 16) | (intr1 & 0xffff0000); | |
107 | nouveau_gpio_isr(dev, 0, hi | lo); | |
fce2bad0 | 108 | |
a0b25635 BS |
109 | nv_wr32(dev, 0xe054, intr0); |
110 | if (dev_priv->chipset >= 0x90) | |
111 | nv_wr32(dev, 0xe074, intr1); | |
d0875edd | 112 | } |
ee2e0131 | 113 | |
6c06d608 DA |
114 | static struct dmi_system_id gpio_reset_ids[] = { |
115 | { | |
116 | .ident = "Apple Macbook 10,1", | |
117 | .matches = { | |
118 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
119 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro10,1"), | |
120 | } | |
121 | }, | |
122 | { } | |
123 | }; | |
124 | ||
ee2e0131 BS |
125 | int |
126 | nv50_gpio_init(struct drm_device *dev) | |
127 | { | |
128 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
129 | ||
6c06d608 DA |
130 | /* initialise gpios and routing to vbios defaults */ |
131 | if (dmi_check_system(gpio_reset_ids)) | |
132 | nouveau_gpio_reset(dev); | |
133 | ||
ee2e0131 BS |
134 | /* disable, and ack any pending gpio interrupts */ |
135 | nv_wr32(dev, 0xe050, 0x00000000); | |
136 | nv_wr32(dev, 0xe054, 0xffffffff); | |
137 | if (dev_priv->chipset >= 0x90) { | |
138 | nv_wr32(dev, 0xe070, 0x00000000); | |
139 | nv_wr32(dev, 0xe074, 0xffffffff); | |
140 | } | |
141 | ||
2cbd4c81 | 142 | nouveau_irq_register(dev, 21, nv50_gpio_isr); |
ee2e0131 BS |
143 | return 0; |
144 | } | |
2cbd4c81 BS |
145 | |
146 | void | |
147 | nv50_gpio_fini(struct drm_device *dev) | |
148 | { | |
149 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
150 | ||
151 | nv_wr32(dev, 0xe050, 0x00000000); | |
152 | if (dev_priv->chipset >= 0x90) | |
153 | nv_wr32(dev, 0xe070, 0x00000000); | |
154 | nouveau_irq_unregister(dev, 21); | |
2cbd4c81 | 155 | } |