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drm/ttm: add reservation_object as argument to ttm_bo_init
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
56d237d2 1/*
26f6d88b
BS		 2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
51beb428 25#include <linux/dma-mapping.h>
83fc083c 26
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/drm_crtc_helper.h>
4874322e 29#include <drm/drm_dp_helper.h>
26f6d88b 30
fdb751ef
BS		 31#include <nvif/class.h>
32
77145f1c
BS		 33#include "nouveau_drm.h"
34#include "nouveau_dma.h"
35#include "nouveau_gem.h"
26f6d88b
BS		 36#include "nouveau_connector.h"
37#include "nouveau_encoder.h"
38#include "nouveau_crtc.h"
f589be88 39#include "nouveau_fence.h"
3a89cd02 40#include "nv50_display.h"
26f6d88b 41
8a46438a
BS		 42#define EVO_DMA_NR 9
43
bdb8c212 44#define EVO_MASTER (0x00)
a63a97eb 45#define EVO_FLIP(c) (0x01 + (c))
8a46438a
BS		 46#define EVO_OVLY(c) (0x05 + (c))
47#define EVO_OIMM(c) (0x09 + (c))
bdb8c212
BS		 48#define EVO_CURS(c) (0x0d + (c))
49
816af2f2
BS		 50/* offsets in shared sync bo of various structures */
51#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
9f9bdaaf
BS		 52#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
53#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
54#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
816af2f2 55
b5a794b0
BS		 56/******************************************************************************
57 * EVO channel
58 *****************************************************************************/
59
e225f446 60struct nv50_chan {
0ad72863 61 struct nvif_object user;
b5a794b0
BS		 62};
63
64static int
410f3ec6 65nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
e225f446 66 void *data, u32 size, struct nv50_chan *chan)
b5a794b0 67{
410f3ec6
BS		 68 while (oclass[0]) {
69 int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head,
70 oclass[0], data, size,
71 &chan->user);
b76f1529
BS		 72 if (oclass++, ret == 0) {
73 nvif_object_map(&chan->user);
410f3ec6 74 return ret;
b76f1529 75 }
410f3ec6
BS		 76 }
77 return -ENOSYS;
b5a794b0
BS		 78}
79
80static void
0ad72863 81nv50_chan_destroy(struct nv50_chan *chan)
b5a794b0 82{
0ad72863 83 nvif_object_fini(&chan->user);
b5a794b0
BS		 84}
85
86/******************************************************************************
87 * PIO EVO channel
88 *****************************************************************************/
89
e225f446
BS		 90struct nv50_pioc {
91 struct nv50_chan base;
b5a794b0
BS		 92};
93
94static void
0ad72863 95nv50_pioc_destroy(struct nv50_pioc *pioc)
b5a794b0 96{
0ad72863 97 nv50_chan_destroy(&pioc->base);
b5a794b0
BS		 98}
99
100static int
410f3ec6 101nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
e225f446 102 void *data, u32 size, struct nv50_pioc *pioc)
b5a794b0 103{
410f3ec6
BS		 104 return nv50_chan_create(disp, oclass, head, data, size, &pioc->base);
105}
106
107/******************************************************************************
108 * Cursor Immediate
109 *****************************************************************************/
110
111struct nv50_curs {
112 struct nv50_pioc base;
113};
114
115static int
116nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
117{
648d4dfd 118 struct nv50_disp_cursor_v0 args = {
410f3ec6
BS		 119 .head = head,
120 };
121 static const u32 oclass[] = {
648d4dfd
BS		 122 GK104_DISP_CURSOR,
123 GF110_DISP_CURSOR,
124 GT214_DISP_CURSOR,
125 G82_DISP_CURSOR,
126 NV50_DISP_CURSOR,
410f3ec6
BS		 127 0
128 };
129
130 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
131 &curs->base);
132}
133
134/******************************************************************************
135 * Overlay Immediate
136 *****************************************************************************/
137
138struct nv50_oimm {
139 struct nv50_pioc base;
140};
141
142static int
143nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
144{
648d4dfd 145 struct nv50_disp_cursor_v0 args = {
410f3ec6
BS		 146 .head = head,
147 };
148 static const u32 oclass[] = {
648d4dfd
BS		 149 GK104_DISP_OVERLAY,
150 GF110_DISP_OVERLAY,
151 GT214_DISP_OVERLAY,
152 G82_DISP_OVERLAY,
153 NV50_DISP_OVERLAY,
410f3ec6
BS		 154 0
155 };
156
157 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
158 &oimm->base);
b5a794b0
BS		 159}
160
161/******************************************************************************
162 * DMA EVO channel
163 *****************************************************************************/
164
e225f446
BS		 165struct nv50_dmac {
166 struct nv50_chan base;
3376ee37
BS		 167 dma_addr_t handle;
168 u32 *ptr;
59ad1465 169
0ad72863
BS		 170 struct nvif_object sync;
171 struct nvif_object vram;
172
59ad1465
DV		 173 /* Protects against concurrent pushbuf access to this channel, lock is
174 * grabbed by evo_wait (if the pushbuf reservation is successful) and
175 * dropped again by evo_kick. */
176 struct mutex lock;
b5a794b0
BS		 177};
178
179static void
0ad72863 180nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
b5a794b0 181{
0ad72863
BS		 182 nvif_object_fini(&dmac->vram);
183 nvif_object_fini(&dmac->sync);
184
185 nv50_chan_destroy(&dmac->base);
186
b5a794b0 187 if (dmac->ptr) {
0ad72863 188 struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
b5a794b0
BS		 189 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
190 }
b5a794b0
BS		 191}
192
47057302 193static int
410f3ec6 194nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
47057302 195 void *data, u32 size, u64 syncbuf,
e225f446 196 struct nv50_dmac *dmac)
47057302 197{
f392ec4b 198 struct nvif_device *device = nvif_device(disp);
648d4dfd 199 struct nv50_disp_core_channel_dma_v0 *args = data;
0ad72863 200 struct nvif_object pushbuf;
47057302
BS		 201 int ret;
202
59ad1465
DV		 203 mutex_init(&dmac->lock);
204
f392ec4b 205 dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev,
0ad72863 206 PAGE_SIZE, &dmac->handle);
47057302
BS		 207 if (!dmac->ptr)
208 return -ENOMEM;
209
f392ec4b 210 ret = nvif_object_init(nvif_object(device), NULL,
648d4dfd 211 args->pushbuf, NV_DMA_FROM_MEMORY,
4acfd707
BS		 212 &(struct nv_dma_v0) {
213 .target = NV_DMA_V0_TARGET_PCI_US,
214 .access = NV_DMA_V0_ACCESS_RD,
47057302
BS		 215 .start = dmac->handle + 0x0000,
216 .limit = dmac->handle + 0x0fff,
4acfd707 217 }, sizeof(struct nv_dma_v0), &pushbuf);
b5a794b0 218 if (ret)
47057302 219 return ret;
b5a794b0 220
410f3ec6 221 ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base);
0ad72863 222 nvif_object_fini(&pushbuf);
47057302
BS		 223 if (ret)
224 return ret;
225
f45f55c4 226 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000,
4acfd707
BS		 227 NV_DMA_IN_MEMORY,
228 &(struct nv_dma_v0) {
229 .target = NV_DMA_V0_TARGET_VRAM,
230 .access = NV_DMA_V0_ACCESS_RDWR,
47057302
BS		 231 .start = syncbuf + 0x0000,
232 .limit = syncbuf + 0x0fff,
4acfd707 233 }, sizeof(struct nv_dma_v0),
0ad72863 234 &dmac->sync);
47057302
BS		 235 if (ret)
236 return ret;
237
f45f55c4 238 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001,
4acfd707
BS		 239 NV_DMA_IN_MEMORY,
240 &(struct nv_dma_v0) {
241 .target = NV_DMA_V0_TARGET_VRAM,
242 .access = NV_DMA_V0_ACCESS_RDWR,
b5a794b0 243 .start = 0,
f392ec4b 244 .limit = device->info.ram_user - 1,
4acfd707 245 }, sizeof(struct nv_dma_v0),
0ad72863 246 &dmac->vram);
b5a794b0 247 if (ret)
47057302
BS		 248 return ret;
249
b5a794b0
BS		 250 return ret;
251}
252
410f3ec6
BS		 253/******************************************************************************
254 * Core
255 *****************************************************************************/
256
e225f446
BS		 257struct nv50_mast {
258 struct nv50_dmac base;
b5a794b0
BS		 259};
260
410f3ec6
BS		 261static int
262nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
263{
648d4dfd
BS		 264 struct nv50_disp_core_channel_dma_v0 args = {
265 .pushbuf = 0xb0007d00,
410f3ec6
BS		 266 };
267 static const u32 oclass[] = {
648d4dfd
BS		 268 GM107_DISP_CORE_CHANNEL_DMA,
269 GK110_DISP_CORE_CHANNEL_DMA,
270 GK104_DISP_CORE_CHANNEL_DMA,
271 GF110_DISP_CORE_CHANNEL_DMA,
272 GT214_DISP_CORE_CHANNEL_DMA,
273 GT206_DISP_CORE_CHANNEL_DMA,
274 GT200_DISP_CORE_CHANNEL_DMA,
275 G82_DISP_CORE_CHANNEL_DMA,
276 NV50_DISP_CORE_CHANNEL_DMA,
410f3ec6
BS		 277 0
278 };
279
280 return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf,
281 &core->base);
282}
283
284/******************************************************************************
285 * Base
286 *****************************************************************************/
b5a794b0 287
e225f446
BS		 288struct nv50_sync {
289 struct nv50_dmac base;
9f9bdaaf
BS		 290 u32 addr;
291 u32 data;
3376ee37
BS		 292};
293
410f3ec6
BS		 294static int
295nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
296 struct nv50_sync *base)
297{
648d4dfd
BS		 298 struct nv50_disp_base_channel_dma_v0 args = {
299 .pushbuf = 0xb0007c00 | head,
410f3ec6
BS		 300 .head = head,
301 };
302 static const u32 oclass[] = {
648d4dfd
BS		 303 GK110_DISP_BASE_CHANNEL_DMA,
304 GK104_DISP_BASE_CHANNEL_DMA,
305 GF110_DISP_BASE_CHANNEL_DMA,
306 GT214_DISP_BASE_CHANNEL_DMA,
307 GT200_DISP_BASE_CHANNEL_DMA,
308 G82_DISP_BASE_CHANNEL_DMA,
309 NV50_DISP_BASE_CHANNEL_DMA,
410f3ec6
BS		 310 0
311 };
312
313 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
314 syncbuf, &base->base);
315}
316
317/******************************************************************************
318 * Overlay
319 *****************************************************************************/
320
e225f446
BS		 321struct nv50_ovly {
322 struct nv50_dmac base;
b5a794b0 323};
f20ce962 324
410f3ec6
BS		 325static int
326nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
327 struct nv50_ovly *ovly)
328{
648d4dfd
BS		 329 struct nv50_disp_overlay_channel_dma_v0 args = {
330 .pushbuf = 0xb0007e00 | head,
410f3ec6
BS		 331 .head = head,
332 };
333 static const u32 oclass[] = {
648d4dfd
BS		 334 GK104_DISP_OVERLAY_CONTROL_DMA,
335 GF110_DISP_OVERLAY_CONTROL_DMA,
336 GT214_DISP_OVERLAY_CHANNEL_DMA,
337 GT200_DISP_OVERLAY_CHANNEL_DMA,
338 G82_DISP_OVERLAY_CHANNEL_DMA,
339 NV50_DISP_OVERLAY_CHANNEL_DMA,
410f3ec6
BS		 340 0
341 };
342
343 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
344 syncbuf, &ovly->base);
345}
26f6d88b 346
e225f446 347struct nv50_head {
dd0e3d53 348 struct nouveau_crtc base;
8dda53fc 349 struct nouveau_bo *image;
e225f446
BS		 350 struct nv50_curs curs;
351 struct nv50_sync sync;
352 struct nv50_ovly ovly;
353 struct nv50_oimm oimm;
b5a794b0
BS		 354};
355
e225f446
BS		 356#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
357#define nv50_curs(c) (&nv50_head(c)->curs)
358#define nv50_sync(c) (&nv50_head(c)->sync)
359#define nv50_ovly(c) (&nv50_head(c)->ovly)
360#define nv50_oimm(c) (&nv50_head(c)->oimm)
361#define nv50_chan(c) (&(c)->base.base)
0ad72863
BS		 362#define nv50_vers(c) nv50_chan(c)->user.oclass
363
364struct nv50_fbdma {
365 struct list_head head;
366 struct nvif_object core;
367 struct nvif_object base[4];
368};
b5a794b0 369
e225f446 370struct nv50_disp {
0ad72863 371 struct nvif_object *disp;
e225f446 372 struct nv50_mast mast;
b5a794b0 373
8a423647 374 struct list_head fbdma;
b5a794b0
BS		 375
376 struct nouveau_bo *sync;
dd0e3d53
BS		 377};
378
e225f446
BS		 379static struct nv50_disp *
380nv50_disp(struct drm_device *dev)
26f6d88b 381{
77145f1c 382 return nouveau_display(dev)->priv;
26f6d88b
BS		 383}
384
e225f446 385#define nv50_mast(d) (&nv50_disp(d)->mast)
b5a794b0 386
bdb8c212 387static struct drm_crtc *
e225f446 388nv50_display_crtc_get(struct drm_encoder *encoder)
bdb8c212
BS		 389{
390 return nouveau_encoder(encoder)->crtc;
391}
392
393/******************************************************************************
394 * EVO channel helpers
395 *****************************************************************************/
51beb428 396static u32 *
b5a794b0 397evo_wait(void *evoc, int nr)
51beb428 398{
e225f446 399 struct nv50_dmac *dmac = evoc;
0ad72863 400 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
51beb428 401
59ad1465 402 mutex_lock(&dmac->lock);
de8268c5 403 if (put + nr >= (PAGE_SIZE / 4) - 8) {
b5a794b0 404 dmac->ptr[put] = 0x20000000;
51beb428 405
0ad72863
BS		 406 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
407 if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
59ad1465 408 mutex_unlock(&dmac->lock);
0ad72863 409 nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
51beb428
BS		 410 return NULL;
411 }
412
413 put = 0;
414 }
415
b5a794b0 416 return dmac->ptr + put;
51beb428
BS		 417}
418
419static void
b5a794b0 420evo_kick(u32 *push, void *evoc)
51beb428 421{
e225f446 422 struct nv50_dmac *dmac = evoc;
0ad72863 423 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
59ad1465 424 mutex_unlock(&dmac->lock);
51beb428
BS		 425}
426
427#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
428#define evo_data(p,d) *((p)++) = (d)
429
3376ee37
BS		 430static bool
431evo_sync_wait(void *data)
432{
5cc027f6
BS		 433 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
434 return true;
435 usleep_range(1, 2);
436 return false;
3376ee37
BS		 437}
438
439static int
b5a794b0 440evo_sync(struct drm_device *dev)
3376ee37 441{
967e7bde 442 struct nvif_device *device = &nouveau_drm(dev)->device;
e225f446
BS		 443 struct nv50_disp *disp = nv50_disp(dev);
444 struct nv50_mast *mast = nv50_mast(dev);
b5a794b0 445 u32 *push = evo_wait(mast, 8);
3376ee37 446 if (push) {
816af2f2 447 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
3376ee37 448 evo_mthd(push, 0x0084, 1);
816af2f2 449 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
3376ee37
BS		 450 evo_mthd(push, 0x0080, 2);
451 evo_data(push, 0x00000000);
452 evo_data(push, 0x00000000);
b5a794b0 453 evo_kick(push, mast);
967e7bde 454 if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
3376ee37
BS		 455 return 0;
456 }
457
458 return -EBUSY;
459}
460
461/******************************************************************************
a63a97eb 462 * Page flipping channel
3376ee37
BS		 463 *****************************************************************************/
464struct nouveau_bo *
e225f446 465nv50_display_crtc_sema(struct drm_device *dev, int crtc)
3376ee37 466{
e225f446 467 return nv50_disp(dev)->sync;
3376ee37
BS		 468}
469
9f9bdaaf
BS		 470struct nv50_display_flip {
471 struct nv50_disp *disp;
472 struct nv50_sync *chan;
473};
474
475static bool
476nv50_display_flip_wait(void *data)
477{
478 struct nv50_display_flip *flip = data;
479 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
b1ea3e6e 480 flip->chan->data)
9f9bdaaf
BS		 481 return true;
482 usleep_range(1, 2);
483 return false;
484}
485
3376ee37 486void
e225f446 487nv50_display_flip_stop(struct drm_crtc *crtc)
3376ee37 488{
967e7bde 489 struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
9f9bdaaf
BS		 490 struct nv50_display_flip flip = {
491 .disp = nv50_disp(crtc->dev),
492 .chan = nv50_sync(crtc),
493 };
3376ee37
BS		 494 u32 *push;
495
9f9bdaaf 496 push = evo_wait(flip.chan, 8);
3376ee37
BS		 497 if (push) {
498 evo_mthd(push, 0x0084, 1);
499 evo_data(push, 0x00000000);
500 evo_mthd(push, 0x0094, 1);
501 evo_data(push, 0x00000000);
502 evo_mthd(push, 0x00c0, 1);
503 evo_data(push, 0x00000000);
504 evo_mthd(push, 0x0080, 1);
505 evo_data(push, 0x00000000);
9f9bdaaf 506 evo_kick(push, flip.chan);
3376ee37 507 }
9f9bdaaf 508
967e7bde 509 nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
3376ee37
BS		 510}
511
512int
e225f446 513nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3376ee37
BS		 514 struct nouveau_channel *chan, u32 swap_interval)
515{
516 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
3376ee37 517 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
8dda53fc 518 struct nv50_head *head = nv50_head(crtc);
e225f446 519 struct nv50_sync *sync = nv50_sync(crtc);
3376ee37 520 u32 *push;
8dda53fc 521 int ret;
3376ee37
BS		 522
523 swap_interval <<= 4;
524 if (swap_interval == 0)
525 swap_interval |= 0x100;
f60b6e7a
BS		 526 if (chan == NULL)
527 evo_sync(crtc->dev);
3376ee37 528
b5a794b0 529 push = evo_wait(sync, 128);
3376ee37
BS		 530 if (unlikely(push == NULL))
531 return -EBUSY;
532
bbf8906b 533 if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) {
9f9bdaaf
BS		 534 ret = RING_SPACE(chan, 8);
535 if (ret)
536 return ret;
537
538 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
8dda53fc 539 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
9f9bdaaf
BS		 540 OUT_RING (chan, sync->addr ^ 0x10);
541 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
542 OUT_RING (chan, sync->data + 1);
543 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
544 OUT_RING (chan, sync->addr);
545 OUT_RING (chan, sync->data);
546 } else
bbf8906b 547 if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) {
8dda53fc 548 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 549 ret = RING_SPACE(chan, 12);
550 if (ret)
551 return ret;
552
553 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
0ad72863 554 OUT_RING (chan, chan->vram.handle);
9f9bdaaf
BS		 555 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
556 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
557 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
558 OUT_RING (chan, sync->data + 1);
559 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
560 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
561 OUT_RING (chan, upper_32_bits(addr));
562 OUT_RING (chan, lower_32_bits(addr));
563 OUT_RING (chan, sync->data);
564 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
565 } else
566 if (chan) {
8dda53fc 567 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 568 ret = RING_SPACE(chan, 10);
569 if (ret)
570 return ret;
571
572 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
573 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
574 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
575 OUT_RING (chan, sync->data + 1);
576 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
577 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
578 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
579 OUT_RING (chan, upper_32_bits(addr));
580 OUT_RING (chan, lower_32_bits(addr));
581 OUT_RING (chan, sync->data);
582 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
583 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
584 }
35bcf5d5 585
9f9bdaaf
BS		 586 if (chan) {
587 sync->addr ^= 0x10;
588 sync->data++;
3376ee37 589 FIRE_RING (chan);
3376ee37
BS		 590 }
591
592 /* queue the flip */
593 evo_mthd(push, 0x0100, 1);
594 evo_data(push, 0xfffe0000);
595 evo_mthd(push, 0x0084, 1);
596 evo_data(push, swap_interval);
597 if (!(swap_interval & 0x00000100)) {
598 evo_mthd(push, 0x00e0, 1);
599 evo_data(push, 0x40000000);
600 }
601 evo_mthd(push, 0x0088, 4);
9f9bdaaf
BS		 602 evo_data(push, sync->addr);
603 evo_data(push, sync->data++);
604 evo_data(push, sync->data);
f45f55c4 605 evo_data(push, sync->base.sync.handle);
3376ee37
BS		 606 evo_mthd(push, 0x00a0, 2);
607 evo_data(push, 0x00000000);
608 evo_data(push, 0x00000000);
609 evo_mthd(push, 0x00c0, 1);
8a423647 610 evo_data(push, nv_fb->r_handle);
3376ee37
BS		 611 evo_mthd(push, 0x0110, 2);
612 evo_data(push, 0x00000000);
613 evo_data(push, 0x00000000);
648d4dfd 614 if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
ed5085a5
BS		 615 evo_mthd(push, 0x0800, 5);
616 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
617 evo_data(push, 0);
618 evo_data(push, (fb->height << 16) | fb->width);
619 evo_data(push, nv_fb->r_pitch);
620 evo_data(push, nv_fb->r_format);
621 } else {
622 evo_mthd(push, 0x0400, 5);
623 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
624 evo_data(push, 0);
625 evo_data(push, (fb->height << 16) | fb->width);
626 evo_data(push, nv_fb->r_pitch);
627 evo_data(push, nv_fb->r_format);
628 }
3376ee37
BS		 629 evo_mthd(push, 0x0080, 1);
630 evo_data(push, 0x00000000);
b5a794b0 631 evo_kick(push, sync);
8dda53fc
BS		 632
633 nouveau_bo_ref(nv_fb->nvbo, &head->image);
3376ee37
BS		 634 return 0;
635}
636
438d99e3
BS		 637/******************************************************************************
638 * CRTC
639 *****************************************************************************/
640static int
e225f446 641nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 642{
e225f446 643 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de691855
BS		 644 struct nouveau_connector *nv_connector;
645 struct drm_connector *connector;
646 u32 *push, mode = 0x00;
438d99e3 647
488ff207 648 nv_connector = nouveau_crtc_connector_get(nv_crtc);
de691855
BS		 649 connector = &nv_connector->base;
650 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
f4510a27 651 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
de691855
BS		 652 mode = DITHERING_MODE_DYNAMIC2X2;
653 } else {
654 mode = nv_connector->dithering_mode;
655 }
656
657 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
658 if (connector->display_info.bpc >= 8)
659 mode |= DITHERING_DEPTH_8BPC;
660 } else {
661 mode |= nv_connector->dithering_depth;
438d99e3
BS		 662 }
663
de8268c5 664 push = evo_wait(mast, 4);
438d99e3 665 if (push) {
648d4dfd 666 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 667 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
668 evo_data(push, mode);
669 } else
648d4dfd 670 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 671 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
672 evo_data(push, mode);
673 } else {
674 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
675 evo_data(push, mode);
676 }
677
438d99e3
BS		 678 if (update) {
679 evo_mthd(push, 0x0080, 1);
680 evo_data(push, 0x00000000);
681 }
de8268c5 682 evo_kick(push, mast);
438d99e3
BS		 683 }
684
685 return 0;
686}
687
688static int
e225f446 689nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 690{
e225f446 691 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
92854622 692 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
3376ee37 693 struct drm_crtc *crtc = &nv_crtc->base;
f3fdc52d 694 struct nouveau_connector *nv_connector;
92854622
BS		 695 int mode = DRM_MODE_SCALE_NONE;
696 u32 oX, oY, *push;
f3fdc52d 697
92854622
BS		 698 /* start off at the resolution we programmed the crtc for, this
699 * effectively handles NONE/FULL scaling
700 */
f3fdc52d 701 nv_connector = nouveau_crtc_connector_get(nv_crtc);
92854622
BS		 702 if (nv_connector && nv_connector->native_mode)
703 mode = nv_connector->scaling_mode;
704
705 if (mode != DRM_MODE_SCALE_NONE)
706 omode = nv_connector->native_mode;
707 else
708 omode = umode;
709
710 oX = omode->hdisplay;
711 oY = omode->vdisplay;
712 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
713 oY *= 2;
714
715 /* add overscan compensation if necessary, will keep the aspect
716 * ratio the same as the backend mode unless overridden by the
717 * user setting both hborder and vborder properties.
718 */
719 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
720 (nv_connector->underscan == UNDERSCAN_AUTO &&
721 nv_connector->edid &&
722 drm_detect_hdmi_monitor(nv_connector->edid)))) {
723 u32 bX = nv_connector->underscan_hborder;
724 u32 bY = nv_connector->underscan_vborder;
725 u32 aspect = (oY << 19) / oX;
726
727 if (bX) {
728 oX -= (bX * 2);
729 if (bY) oY -= (bY * 2);
730 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
731 } else {
732 oX -= (oX >> 4) + 32;
733 if (bY) oY -= (bY * 2);
734 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
735 }
736 }
737
738 /* handle CENTER/ASPECT scaling, taking into account the areas
739 * removed already for overscan compensation
740 */
741 switch (mode) {
742 case DRM_MODE_SCALE_CENTER:
743 oX = min((u32)umode->hdisplay, oX);
744 oY = min((u32)umode->vdisplay, oY);
745 /* fall-through */
746 case DRM_MODE_SCALE_ASPECT:
747 if (oY < oX) {
748 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
749 oX = ((oY * aspect) + (aspect / 2)) >> 19;
750 } else {
751 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
752 oY = ((oX * aspect) + (aspect / 2)) >> 19;
f3fdc52d 753 }
92854622
BS		 754 break;
755 default:
756 break;
f3fdc52d 757 }
438d99e3 758
de8268c5 759 push = evo_wait(mast, 8);
438d99e3 760 if (push) {
648d4dfd 761 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 762 /*XXX: SCALE_CTRL_ACTIVE??? */
763 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
764 evo_data(push, (oY << 16) | oX);
765 evo_data(push, (oY << 16) | oX);
766 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
767 evo_data(push, 0x00000000);
768 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
769 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
770 } else {
771 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
772 evo_data(push, (oY << 16) | oX);
773 evo_data(push, (oY << 16) | oX);
774 evo_data(push, (oY << 16) | oX);
775 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
776 evo_data(push, 0x00000000);
777 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
778 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
779 }
780
781 evo_kick(push, mast);
782
438d99e3 783 if (update) {
e225f446 784 nv50_display_flip_stop(crtc);
f4510a27
MR		 785 nv50_display_flip_next(crtc, crtc->primary->fb,
786 NULL, 1);
438d99e3 787 }
438d99e3
BS		 788 }
789
790 return 0;
791}
792
f9887d09 793static int
e225f446 794nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
f9887d09 795{
e225f446 796 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
f9887d09
BS		 797 u32 *push, hue, vib;
798 int adj;
799
800 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
801 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
802 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
803
804 push = evo_wait(mast, 16);
805 if (push) {
648d4dfd 806 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
f9887d09
BS		 807 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
808 evo_data(push, (hue << 20) | (vib << 8));
809 } else {
810 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
811 evo_data(push, (hue << 20) | (vib << 8));
812 }
813
814 if (update) {
815 evo_mthd(push, 0x0080, 1);
816 evo_data(push, 0x00000000);
817 }
818 evo_kick(push, mast);
819 }
820
821 return 0;
822}
823
438d99e3 824static int
e225f446 825nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
438d99e3
BS		 826 int x, int y, bool update)
827{
828 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
e225f446 829 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
438d99e3
BS		 830 u32 *push;
831
de8268c5 832 push = evo_wait(mast, 16);
438d99e3 833 if (push) {
648d4dfd 834 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 835 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
836 evo_data(push, nvfb->nvbo->bo.offset >> 8);
837 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
838 evo_data(push, (fb->height << 16) | fb->width);
839 evo_data(push, nvfb->r_pitch);
840 evo_data(push, nvfb->r_format);
841 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
842 evo_data(push, (y << 16) | x);
648d4dfd 843 if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
de8268c5 844 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 845 evo_data(push, nvfb->r_handle);
de8268c5
BS		 846 }
847 } else {
848 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
849 evo_data(push, nvfb->nvbo->bo.offset >> 8);
850 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
851 evo_data(push, (fb->height << 16) | fb->width);
852 evo_data(push, nvfb->r_pitch);
853 evo_data(push, nvfb->r_format);
8a423647 854 evo_data(push, nvfb->r_handle);
de8268c5
BS		 855 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
856 evo_data(push, (y << 16) | x);
857 }
858
a46232ee
BS		 859 if (update) {
860 evo_mthd(push, 0x0080, 1);
861 evo_data(push, 0x00000000);
862 }
de8268c5 863 evo_kick(push, mast);
438d99e3
BS		 864 }
865
8a423647 866 nv_crtc->fb.handle = nvfb->r_handle;
438d99e3
BS		 867 return 0;
868}
869
870static void
e225f446 871nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
438d99e3 872{
e225f446 873 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5 874 u32 *push = evo_wait(mast, 16);
438d99e3 875 if (push) {
648d4dfd 876 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 877 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
878 evo_data(push, 0x85000000);
879 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
880 } else
648d4dfd 881 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 882 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
883 evo_data(push, 0x85000000);
884 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
885 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
f45f55c4 886 evo_data(push, mast->base.vram.handle);
de8268c5 887 } else {
438d99e3
BS		 888 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
889 evo_data(push, 0x85000000);
890 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
891 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
f45f55c4 892 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 893 }
894 evo_kick(push, mast);
895 }
896}
897
898static void
e225f446 899nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
de8268c5 900{
e225f446 901 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 902 u32 *push = evo_wait(mast, 16);
903 if (push) {
648d4dfd 904 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 905 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
906 evo_data(push, 0x05000000);
907 } else
648d4dfd 908 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 909 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
910 evo_data(push, 0x05000000);
911 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
912 evo_data(push, 0x00000000);
438d99e3
BS		 913 } else {
914 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
915 evo_data(push, 0x05000000);
916 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
917 evo_data(push, 0x00000000);
918 }
de8268c5
BS		 919 evo_kick(push, mast);
920 }
921}
438d99e3 922
de8268c5 923static void
e225f446 924nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
de8268c5 925{
e225f446 926 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 927
928 if (show)
e225f446 929 nv50_crtc_cursor_show(nv_crtc);
de8268c5 930 else
e225f446 931 nv50_crtc_cursor_hide(nv_crtc);
de8268c5
BS		 932
933 if (update) {
934 u32 *push = evo_wait(mast, 2);
935 if (push) {
438d99e3
BS		 936 evo_mthd(push, 0x0080, 1);
937 evo_data(push, 0x00000000);
de8268c5 938 evo_kick(push, mast);
438d99e3 939 }
438d99e3
BS		 940 }
941}
942
943static void
e225f446 944nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
438d99e3
BS		 945{
946}
947
948static void
e225f446 949nv50_crtc_prepare(struct drm_crtc *crtc)
438d99e3
BS		 950{
951 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 952 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 953 u32 *push;
954
e225f446 955 nv50_display_flip_stop(crtc);
3376ee37 956
56d237d2 957 push = evo_wait(mast, 6);
438d99e3 958 if (push) {
648d4dfd 959 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 960 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
961 evo_data(push, 0x00000000);
962 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
963 evo_data(push, 0x40000000);
964 } else
648d4dfd 965 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 966 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
967 evo_data(push, 0x00000000);
968 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
969 evo_data(push, 0x40000000);
970 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
971 evo_data(push, 0x00000000);
972 } else {
973 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
974 evo_data(push, 0x00000000);
975 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
976 evo_data(push, 0x03000000);
977 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
978 evo_data(push, 0x00000000);
979 }
980
981 evo_kick(push, mast);
438d99e3
BS		 982 }
983
e225f446 984 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
438d99e3
BS		 985}
986
987static void
e225f446 988nv50_crtc_commit(struct drm_crtc *crtc)
438d99e3
BS		 989{
990 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 991 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 992 u32 *push;
993
de8268c5 994 push = evo_wait(mast, 32);
438d99e3 995 if (push) {
648d4dfd 996 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5 997 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 998 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 999 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1000 evo_data(push, 0xc0000000);
1001 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1002 } else
648d4dfd 1003 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5 1004 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 1005 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1006 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1007 evo_data(push, 0xc0000000);
1008 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1009 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
f45f55c4 1010 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 1011 } else {
1012 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
8a423647 1013 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1014 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1015 evo_data(push, 0x83000000);
1016 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1017 evo_data(push, 0x00000000);
1018 evo_data(push, 0x00000000);
1019 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
f45f55c4 1020 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 1021 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1022 evo_data(push, 0xffffff00);
1023 }
1024
1025 evo_kick(push, mast);
438d99e3
BS		 1026 }
1027
e225f446 1028 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
f4510a27 1029 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
438d99e3
BS		 1030}
1031
1032static bool
e225f446 1033nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
438d99e3
BS		 1034 struct drm_display_mode *adjusted_mode)
1035{
eb2e9686 1036 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
438d99e3
BS		 1037 return true;
1038}
1039
1040static int
e225f446 1041nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
438d99e3 1042{
f4510a27 1043 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
8dda53fc 1044 struct nv50_head *head = nv50_head(crtc);
438d99e3
BS		 1045 int ret;
1046
1047 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
8dda53fc
BS		 1048 if (ret == 0) {
1049 if (head->image)
1050 nouveau_bo_unpin(head->image);
1051 nouveau_bo_ref(nvfb->nvbo, &head->image);
438d99e3
BS		 1052 }
1053
8dda53fc 1054 return ret;
438d99e3
BS		 1055}
1056
1057static int
e225f446 1058nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
438d99e3
BS		 1059 struct drm_display_mode *mode, int x, int y,
1060 struct drm_framebuffer *old_fb)
1061{
e225f446 1062 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 1063 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1064 struct nouveau_connector *nv_connector;
2d1d898b
BS		 1065 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1066 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1067 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1068 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1dce6264 1069 u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
3488c57b 1070 u32 *push;
438d99e3
BS		 1071 int ret;
1072
2d1d898b
BS		 1073 hactive = mode->htotal;
1074 hsynce = mode->hsync_end - mode->hsync_start - 1;
1075 hbackp = mode->htotal - mode->hsync_end;
1076 hblanke = hsynce + hbackp;
1077 hfrontp = mode->hsync_start - mode->hdisplay;
1078 hblanks = mode->htotal - hfrontp - 1;
1079
1080 vactive = mode->vtotal * vscan / ilace;
1081 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1082 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1083 vblanke = vsynce + vbackp;
1084 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1085 vblanks = vactive - vfrontp - 1;
1dce6264
RS		 1086 /* XXX: Safe underestimate, even "0" works */
1087 vblankus = (vactive - mode->vdisplay - 2) * hactive;
1088 vblankus *= 1000;
1089 vblankus /= mode->clock;
1090
2d1d898b
BS		 1091 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1092 vblan2e = vactive + vsynce + vbackp;
1093 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1094 vactive = (vactive * 2) + 1;
2d1d898b
BS		 1095 }
1096
e225f446 1097 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1098 if (ret)
1099 return ret;
1100
de8268c5 1101 push = evo_wait(mast, 64);
438d99e3 1102 if (push) {
648d4dfd 1103 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 1104 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1105 evo_data(push, 0x00800000 | mode->clock);
1106 evo_data(push, (ilace == 2) ? 2 : 0);
1dce6264 1107 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 8);
de8268c5
BS		 1108 evo_data(push, 0x00000000);
1109 evo_data(push, (vactive << 16) | hactive);
1110 evo_data(push, ( vsynce << 16) | hsynce);
1111 evo_data(push, (vblanke << 16) | hblanke);
1112 evo_data(push, (vblanks << 16) | hblanks);
1113 evo_data(push, (vblan2e << 16) | vblan2s);
1dce6264 1114 evo_data(push, vblankus);
de8268c5
BS		 1115 evo_data(push, 0x00000000);
1116 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1117 evo_data(push, 0x00000311);
1118 evo_data(push, 0x00000100);
1119 } else {
1120 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1121 evo_data(push, 0x00000000);
1122 evo_data(push, (vactive << 16) | hactive);
1123 evo_data(push, ( vsynce << 16) | hsynce);
1124 evo_data(push, (vblanke << 16) | hblanke);
1125 evo_data(push, (vblanks << 16) | hblanks);
1126 evo_data(push, (vblan2e << 16) | vblan2s);
1127 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1128 evo_data(push, 0x00000000); /* ??? */
1129 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1130 evo_data(push, mode->clock * 1000);
1131 evo_data(push, 0x00200000); /* ??? */
1132 evo_data(push, mode->clock * 1000);
1133 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1134 evo_data(push, 0x00000311);
1135 evo_data(push, 0x00000100);
1136 }
1137
1138 evo_kick(push, mast);
438d99e3
BS		 1139 }
1140
1141 nv_connector = nouveau_crtc_connector_get(nv_crtc);
e225f446
BS		 1142 nv50_crtc_set_dither(nv_crtc, false);
1143 nv50_crtc_set_scale(nv_crtc, false);
1144 nv50_crtc_set_color_vibrance(nv_crtc, false);
f4510a27 1145 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
438d99e3
BS		 1146 return 0;
1147}
1148
1149static int
e225f446 1150nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
438d99e3
BS		 1151 struct drm_framebuffer *old_fb)
1152{
77145f1c 1153 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
438d99e3
BS		 1154 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1155 int ret;
1156
f4510a27 1157 if (!crtc->primary->fb) {
77145f1c 1158 NV_DEBUG(drm, "No FB bound\n");
84e2ad8b
BS		 1159 return 0;
1160 }
1161
e225f446 1162 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1163 if (ret)
1164 return ret;
1165
e225f446 1166 nv50_display_flip_stop(crtc);
f4510a27
MR		 1167 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1168 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
438d99e3
BS		 1169 return 0;
1170}
1171
1172static int
e225f446 1173nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
438d99e3
BS		 1174 struct drm_framebuffer *fb, int x, int y,
1175 enum mode_set_atomic state)
1176{
1177 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1178 nv50_display_flip_stop(crtc);
1179 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
438d99e3
BS		 1180 return 0;
1181}
1182
1183static void
e225f446 1184nv50_crtc_lut_load(struct drm_crtc *crtc)
438d99e3 1185{
e225f446 1186 struct nv50_disp *disp = nv50_disp(crtc->dev);
438d99e3
BS		 1187 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1188 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1189 int i;
1190
1191 for (i = 0; i < 256; i++) {
de8268c5
BS		 1192 u16 r = nv_crtc->lut.r[i] >> 2;
1193 u16 g = nv_crtc->lut.g[i] >> 2;
1194 u16 b = nv_crtc->lut.b[i] >> 2;
1195
648d4dfd 1196 if (disp->disp->oclass < GF110_DISP) {
de8268c5
BS		 1197 writew(r + 0x0000, lut + (i * 0x08) + 0);
1198 writew(g + 0x0000, lut + (i * 0x08) + 2);
1199 writew(b + 0x0000, lut + (i * 0x08) + 4);
1200 } else {
1201 writew(r + 0x6000, lut + (i * 0x20) + 0);
1202 writew(g + 0x6000, lut + (i * 0x20) + 2);
1203 writew(b + 0x6000, lut + (i * 0x20) + 4);
1204 }
438d99e3
BS		 1205 }
1206}
1207
8dda53fc
BS		 1208static void
1209nv50_crtc_disable(struct drm_crtc *crtc)
1210{
1211 struct nv50_head *head = nv50_head(crtc);
efa366fd 1212 evo_sync(crtc->dev);
8dda53fc
BS		 1213 if (head->image)
1214 nouveau_bo_unpin(head->image);
1215 nouveau_bo_ref(NULL, &head->image);
1216}
1217
438d99e3 1218static int
e225f446 1219nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
438d99e3
BS		 1220 uint32_t handle, uint32_t width, uint32_t height)
1221{
1222 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1223 struct drm_device *dev = crtc->dev;
1224 struct drm_gem_object *gem;
1225 struct nouveau_bo *nvbo;
1226 bool visible = (handle != 0);
1227 int i, ret = 0;
1228
1229 if (visible) {
1230 if (width != 64 || height != 64)
1231 return -EINVAL;
1232
1233 gem = drm_gem_object_lookup(dev, file_priv, handle);
1234 if (unlikely(!gem))
1235 return -ENOENT;
1236 nvbo = nouveau_gem_object(gem);
1237
1238 ret = nouveau_bo_map(nvbo);
1239 if (ret == 0) {
1240 for (i = 0; i < 64 * 64; i++) {
1241 u32 v = nouveau_bo_rd32(nvbo, i);
1242 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1243 }
1244 nouveau_bo_unmap(nvbo);
1245 }
1246
1247 drm_gem_object_unreference_unlocked(gem);
1248 }
1249
1250 if (visible != nv_crtc->cursor.visible) {
e225f446 1251 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
438d99e3
BS		 1252 nv_crtc->cursor.visible = visible;
1253 }
1254
1255 return ret;
1256}
1257
1258static int
e225f446 1259nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
438d99e3 1260{
e225f446
BS		 1261 struct nv50_curs *curs = nv50_curs(crtc);
1262 struct nv50_chan *chan = nv50_chan(curs);
0ad72863
BS		 1263 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1264 nvif_wr32(&chan->user, 0x0080, 0x00000000);
438d99e3
BS		 1265 return 0;
1266}
1267
1268static void
e225f446 1269nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
438d99e3
BS		 1270 uint32_t start, uint32_t size)
1271{
1272 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
bdefc8cb 1273 u32 end = min_t(u32, start + size, 256);
438d99e3
BS		 1274 u32 i;
1275
1276 for (i = start; i < end; i++) {
1277 nv_crtc->lut.r[i] = r[i];
1278 nv_crtc->lut.g[i] = g[i];
1279 nv_crtc->lut.b[i] = b[i];
1280 }
1281
e225f446 1282 nv50_crtc_lut_load(crtc);
438d99e3
BS		 1283}
1284
1285static void
e225f446 1286nv50_crtc_destroy(struct drm_crtc *crtc)
438d99e3
BS		 1287{
1288 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1289 struct nv50_disp *disp = nv50_disp(crtc->dev);
1290 struct nv50_head *head = nv50_head(crtc);
0ad72863 1291 struct nv50_fbdma *fbdma;
8dda53fc 1292
0ad72863
BS		 1293 list_for_each_entry(fbdma, &disp->fbdma, head) {
1294 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1295 }
1296
1297 nv50_dmac_destroy(&head->ovly.base, disp->disp);
1298 nv50_pioc_destroy(&head->oimm.base);
1299 nv50_dmac_destroy(&head->sync.base, disp->disp);
1300 nv50_pioc_destroy(&head->curs.base);
8dda53fc
BS		 1301
1302 /*XXX: this shouldn't be necessary, but the core doesn't call
1303 * disconnect() during the cleanup paths
1304 */
1305 if (head->image)
1306 nouveau_bo_unpin(head->image);
1307 nouveau_bo_ref(NULL, &head->image);
1308
438d99e3 1309 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
04c8c210
MS		 1310 if (nv_crtc->cursor.nvbo)
1311 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
438d99e3 1312 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
8dda53fc 1313
438d99e3 1314 nouveau_bo_unmap(nv_crtc->lut.nvbo);
04c8c210
MS		 1315 if (nv_crtc->lut.nvbo)
1316 nouveau_bo_unpin(nv_crtc->lut.nvbo);
438d99e3 1317 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
8dda53fc 1318
438d99e3
BS		 1319 drm_crtc_cleanup(crtc);
1320 kfree(crtc);
1321}
1322
e225f446
BS		 1323static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1324 .dpms = nv50_crtc_dpms,
1325 .prepare = nv50_crtc_prepare,
1326 .commit = nv50_crtc_commit,
1327 .mode_fixup = nv50_crtc_mode_fixup,
1328 .mode_set = nv50_crtc_mode_set,
1329 .mode_set_base = nv50_crtc_mode_set_base,
1330 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1331 .load_lut = nv50_crtc_lut_load,
8dda53fc 1332 .disable = nv50_crtc_disable,
438d99e3
BS		 1333};
1334
e225f446
BS		 1335static const struct drm_crtc_funcs nv50_crtc_func = {
1336 .cursor_set = nv50_crtc_cursor_set,
1337 .cursor_move = nv50_crtc_cursor_move,
1338 .gamma_set = nv50_crtc_gamma_set,
5addcf0a 1339 .set_config = nouveau_crtc_set_config,
e225f446 1340 .destroy = nv50_crtc_destroy,
3376ee37 1341 .page_flip = nouveau_crtc_page_flip,
438d99e3
BS		 1342};
1343
c20ab3e1 1344static void
e225f446 1345nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
c20ab3e1
BS		 1346{
1347}
1348
1349static void
e225f446 1350nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
c20ab3e1
BS		 1351{
1352}
1353
438d99e3 1354static int
0ad72863 1355nv50_crtc_create(struct drm_device *dev, int index)
438d99e3 1356{
e225f446
BS		 1357 struct nv50_disp *disp = nv50_disp(dev);
1358 struct nv50_head *head;
438d99e3
BS		 1359 struct drm_crtc *crtc;
1360 int ret, i;
1361
dd0e3d53
BS		 1362 head = kzalloc(sizeof(*head), GFP_KERNEL);
1363 if (!head)
438d99e3
BS		 1364 return -ENOMEM;
1365
dd0e3d53 1366 head->base.index = index;
e225f446
BS		 1367 head->base.set_dither = nv50_crtc_set_dither;
1368 head->base.set_scale = nv50_crtc_set_scale;
1369 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
f9887d09
BS		 1370 head->base.color_vibrance = 50;
1371 head->base.vibrant_hue = 0;
e225f446
BS		 1372 head->base.cursor.set_offset = nv50_cursor_set_offset;
1373 head->base.cursor.set_pos = nv50_cursor_set_pos;
438d99e3 1374 for (i = 0; i < 256; i++) {
dd0e3d53
BS		 1375 head->base.lut.r[i] = i << 8;
1376 head->base.lut.g[i] = i << 8;
1377 head->base.lut.b[i] = i << 8;
438d99e3
BS		 1378 }
1379
dd0e3d53 1380 crtc = &head->base.base;
e225f446
BS		 1381 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1382 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
438d99e3
BS		 1383 drm_mode_crtc_set_gamma_size(crtc, 256);
1384
b5a794b0
BS		 1385 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1386 0, 0x0000, NULL, &head->base.lut.nvbo);
1387 if (!ret) {
1388 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1389 if (!ret) {
b5a794b0 1390 ret = nouveau_bo_map(head->base.lut.nvbo);
04c8c210
MS		 1391 if (ret)
1392 nouveau_bo_unpin(head->base.lut.nvbo);
1393 }
b5a794b0
BS		 1394 if (ret)
1395 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1396 }
1397
1398 if (ret)
1399 goto out;
1400
e225f446 1401 nv50_crtc_lut_load(crtc);
b5a794b0
BS		 1402
1403 /* allocate cursor resources */
410f3ec6 1404 ret = nv50_curs_create(disp->disp, index, &head->curs);
b5a794b0
BS		 1405 if (ret)
1406 goto out;
1407
438d99e3 1408 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
dd0e3d53 1409 0, 0x0000, NULL, &head->base.cursor.nvbo);
438d99e3 1410 if (!ret) {
dd0e3d53 1411 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1412 if (!ret) {
dd0e3d53 1413 ret = nouveau_bo_map(head->base.cursor.nvbo);
04c8c210
MS		 1414 if (ret)
1415 nouveau_bo_unpin(head->base.lut.nvbo);
1416 }
438d99e3 1417 if (ret)
dd0e3d53 1418 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
438d99e3
BS		 1419 }
1420
1421 if (ret)
1422 goto out;
1423
b5a794b0 1424 /* allocate page flip / sync resources */
410f3ec6
BS		 1425 ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset,
1426 &head->sync);
b5a794b0
BS		 1427 if (ret)
1428 goto out;
1429
9f9bdaaf
BS		 1430 head->sync.addr = EVO_FLIP_SEM0(index);
1431 head->sync.data = 0x00000000;
438d99e3 1432
b5a794b0 1433 /* allocate overlay resources */
410f3ec6 1434 ret = nv50_oimm_create(disp->disp, index, &head->oimm);
438d99e3
BS		 1435 if (ret)
1436 goto out;
1437
410f3ec6
BS		 1438 ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset,
1439 &head->ovly);
b5a794b0
BS		 1440 if (ret)
1441 goto out;
438d99e3
BS		 1442
1443out:
1444 if (ret)
e225f446 1445 nv50_crtc_destroy(crtc);
438d99e3
BS		 1446 return ret;
1447}
1448
26f6d88b
BS		 1449/******************************************************************************
1450 * DAC
1451 *****************************************************************************/
8eaa9669 1452static void
e225f446 1453nv50_dac_dpms(struct drm_encoder *encoder, int mode)
8eaa9669
BS		 1454{
1455 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1456 struct nv50_disp *disp = nv50_disp(encoder->dev);
bf0eb898
BS		 1457 struct {
1458 struct nv50_disp_mthd_v1 base;
1459 struct nv50_disp_dac_pwr_v0 pwr;
1460 } args = {
1461 .base.version = 1,
1462 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1463 .base.hasht = nv_encoder->dcb->hasht,
1464 .base.hashm = nv_encoder->dcb->hashm,
1465 .pwr.state = 1,
1466 .pwr.data = 1,
1467 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1468 mode != DRM_MODE_DPMS_OFF),
1469 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1470 mode != DRM_MODE_DPMS_OFF),
1471 };
8eaa9669 1472
bf0eb898 1473 nvif_mthd(disp->disp, 0, &args, sizeof(args));
8eaa9669
BS		 1474}
1475
1476static bool
e225f446 1477nv50_dac_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1478 const struct drm_display_mode *mode,
8eaa9669
BS		 1479 struct drm_display_mode *adjusted_mode)
1480{
1481 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1482 struct nouveau_connector *nv_connector;
1483
1484 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1485 if (nv_connector && nv_connector->native_mode) {
1486 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1487 int id = adjusted_mode->base.id;
1488 *adjusted_mode = *nv_connector->native_mode;
1489 adjusted_mode->base.id = id;
1490 }
1491 }
1492
1493 return true;
1494}
1495
8eaa9669 1496static void
e225f446 1497nv50_dac_commit(struct drm_encoder *encoder)
8eaa9669
BS		 1498{
1499}
1500
1501static void
e225f446 1502nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
8eaa9669
BS		 1503 struct drm_display_mode *adjusted_mode)
1504{
e225f446 1505 struct nv50_mast *mast = nv50_mast(encoder->dev);
8eaa9669
BS		 1506 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1507 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
97b19b5c 1508 u32 *push;
8eaa9669 1509
e225f446 1510 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
8eaa9669 1511
97b19b5c 1512 push = evo_wait(mast, 8);
8eaa9669 1513 if (push) {
648d4dfd 1514 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
97b19b5c
BS		 1515 u32 syncs = 0x00000000;
1516
1517 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1518 syncs |= 0x00000001;
1519 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1520 syncs |= 0x00000002;
1521
1522 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1523 evo_data(push, 1 << nv_crtc->index);
1524 evo_data(push, syncs);
1525 } else {
1526 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1527 u32 syncs = 0x00000001;
1528
1529 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1530 syncs |= 0x00000008;
1531 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1532 syncs |= 0x00000010;
1533
1534 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1535 magic |= 0x00000001;
1536
1537 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1538 evo_data(push, syncs);
1539 evo_data(push, magic);
1540 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1541 evo_data(push, 1 << nv_crtc->index);
1542 }
1543
1544 evo_kick(push, mast);
8eaa9669
BS		 1545 }
1546
1547 nv_encoder->crtc = encoder->crtc;
1548}
1549
1550static void
e225f446 1551nv50_dac_disconnect(struct drm_encoder *encoder)
8eaa9669
BS		 1552{
1553 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1554 struct nv50_mast *mast = nv50_mast(encoder->dev);
97b19b5c 1555 const int or = nv_encoder->or;
8eaa9669
BS		 1556 u32 *push;
1557
1558 if (nv_encoder->crtc) {
e225f446 1559 nv50_crtc_prepare(nv_encoder->crtc);
8eaa9669 1560
97b19b5c 1561 push = evo_wait(mast, 4);
8eaa9669 1562 if (push) {
648d4dfd 1563 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
97b19b5c
BS		 1564 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1565 evo_data(push, 0x00000000);
1566 } else {
1567 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1568 evo_data(push, 0x00000000);
1569 }
97b19b5c 1570 evo_kick(push, mast);
8eaa9669 1571 }
8eaa9669 1572 }
97b19b5c
BS		 1573
1574 nv_encoder->crtc = NULL;
8eaa9669
BS		 1575}
1576
b6d8e7ec 1577static enum drm_connector_status
e225f446 1578nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
b6d8e7ec 1579{
c4abd317 1580 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1581 struct nv50_disp *disp = nv50_disp(encoder->dev);
c4abd317
BS		 1582 struct {
1583 struct nv50_disp_mthd_v1 base;
1584 struct nv50_disp_dac_load_v0 load;
1585 } args = {
1586 .base.version = 1,
1587 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1588 .base.hasht = nv_encoder->dcb->hasht,
1589 .base.hashm = nv_encoder->dcb->hashm,
1590 };
1591 int ret;
1592
1593 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1594 if (args.load.data == 0)
1595 args.load.data = 340;
b681993f 1596
c4abd317
BS		 1597 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1598 if (ret || !args.load.load)
35b21d39 1599 return connector_status_disconnected;
b681993f 1600
35b21d39 1601 return connector_status_connected;
b6d8e7ec
BS		 1602}
1603
8eaa9669 1604static void
e225f446 1605nv50_dac_destroy(struct drm_encoder *encoder)
8eaa9669
BS		 1606{
1607 drm_encoder_cleanup(encoder);
1608 kfree(encoder);
1609}
1610
e225f446
BS		 1611static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1612 .dpms = nv50_dac_dpms,
1613 .mode_fixup = nv50_dac_mode_fixup,
1614 .prepare = nv50_dac_disconnect,
1615 .commit = nv50_dac_commit,
1616 .mode_set = nv50_dac_mode_set,
1617 .disable = nv50_dac_disconnect,
1618 .get_crtc = nv50_display_crtc_get,
1619 .detect = nv50_dac_detect
8eaa9669
BS		 1620};
1621
e225f446
BS		 1622static const struct drm_encoder_funcs nv50_dac_func = {
1623 .destroy = nv50_dac_destroy,
8eaa9669
BS		 1624};
1625
1626static int
e225f446 1627nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
8eaa9669 1628{
5ed50209 1629 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 1630 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
8eaa9669
BS		 1631 struct nouveau_encoder *nv_encoder;
1632 struct drm_encoder *encoder;
5ed50209 1633 int type = DRM_MODE_ENCODER_DAC;
8eaa9669
BS		 1634
1635 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1636 if (!nv_encoder)
1637 return -ENOMEM;
1638 nv_encoder->dcb = dcbe;
1639 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 1640 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
8eaa9669
BS		 1641
1642 encoder = to_drm_encoder(nv_encoder);
1643 encoder->possible_crtcs = dcbe->heads;
1644 encoder->possible_clones = 0;
5ed50209 1645 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
e225f446 1646 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
8eaa9669
BS		 1647
1648 drm_mode_connector_attach_encoder(connector, encoder);
1649 return 0;
1650}
26f6d88b 1651
78951d22
BS		 1652/******************************************************************************
1653 * Audio
1654 *****************************************************************************/
1655static void
e225f446 1656nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22
BS		 1657{
1658 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
cc2a9071 1659 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
78951d22 1660 struct nouveau_connector *nv_connector;
e225f446 1661 struct nv50_disp *disp = nv50_disp(encoder->dev);
d889c524
BS		 1662 struct __packed {
1663 struct {
1664 struct nv50_disp_mthd_v1 mthd;
1665 struct nv50_disp_sor_hda_eld_v0 eld;
1666 } base;
120b0c39
BS		 1667 u8 data[sizeof(nv_connector->base.eld)];
1668 } args = {
d889c524
BS		 1669 .base.mthd.version = 1,
1670 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1671 .base.mthd.hasht = nv_encoder->dcb->hasht,
cc2a9071
BS		 1672 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1673 (0x0100 << nv_crtc->index),
120b0c39 1674 };
78951d22
BS		 1675
1676 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1677 if (!drm_detect_monitor_audio(nv_connector->edid))
1678 return;
1679
78951d22 1680 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
120b0c39 1681 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
78951d22 1682
d889c524 1683 nvif_mthd(disp->disp, 0, &args, sizeof(args.base) + args.data[2] * 4);
78951d22
BS		 1684}
1685
1686static void
cc2a9071 1687nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
78951d22
BS		 1688{
1689 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1690 struct nv50_disp *disp = nv50_disp(encoder->dev);
120b0c39
BS		 1691 struct {
1692 struct nv50_disp_mthd_v1 base;
1693 struct nv50_disp_sor_hda_eld_v0 eld;
1694 } args = {
1695 .base.version = 1,
1696 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1697 .base.hasht = nv_encoder->dcb->hasht,
cc2a9071
BS		 1698 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1699 (0x0100 << nv_crtc->index),
120b0c39 1700 };
78951d22 1701
120b0c39 1702 nvif_mthd(disp->disp, 0, &args, sizeof(args));
78951d22
BS		 1703}
1704
1705/******************************************************************************
1706 * HDMI
1707 *****************************************************************************/
1708static void
e225f446 1709nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22 1710{
64d9cc04
BS		 1711 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1712 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
e225f446 1713 struct nv50_disp *disp = nv50_disp(encoder->dev);
e00f2235
BS		 1714 struct {
1715 struct nv50_disp_mthd_v1 base;
1716 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1717 } args = {
1718 .base.version = 1,
1719 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1720 .base.hasht = nv_encoder->dcb->hasht,
1721 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1722 (0x0100 << nv_crtc->index),
1723 .pwr.state = 1,
1724 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1725 };
1726 struct nouveau_connector *nv_connector;
64d9cc04
BS		 1727 u32 max_ac_packet;
1728
1729 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1730 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1731 return;
1732
1733 max_ac_packet = mode->htotal - mode->hdisplay;
e00f2235 1734 max_ac_packet -= args.pwr.rekey;
64d9cc04 1735 max_ac_packet -= 18; /* constant from tegra */
e00f2235 1736 args.pwr.max_ac_packet = max_ac_packet / 32;
091e40cd 1737
e00f2235 1738 nvif_mthd(disp->disp, 0, &args, sizeof(args));
e225f446 1739 nv50_audio_mode_set(encoder, mode);
78951d22
BS		 1740}
1741
1742static void
e84a35a8 1743nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
78951d22 1744{
64d9cc04 1745 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1746 struct nv50_disp *disp = nv50_disp(encoder->dev);
e00f2235
BS		 1747 struct {
1748 struct nv50_disp_mthd_v1 base;
1749 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1750 } args = {
1751 .base.version = 1,
1752 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1753 .base.hasht = nv_encoder->dcb->hasht,
1754 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1755 (0x0100 << nv_crtc->index),
1756 };
64d9cc04 1757
e00f2235 1758 nvif_mthd(disp->disp, 0, &args, sizeof(args));
78951d22
BS		 1759}
1760
26f6d88b
BS		 1761/******************************************************************************
1762 * SOR
1763 *****************************************************************************/
83fc083c 1764static void
e225f446 1765nv50_sor_dpms(struct drm_encoder *encoder, int mode)
83fc083c
BS		 1766{
1767 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
d55b4af9
BS		 1768 struct nv50_disp *disp = nv50_disp(encoder->dev);
1769 struct {
1770 struct nv50_disp_mthd_v1 base;
1771 struct nv50_disp_sor_pwr_v0 pwr;
1772 } args = {
1773 .base.version = 1,
1774 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1775 .base.hasht = nv_encoder->dcb->hasht,
1776 .base.hashm = nv_encoder->dcb->hashm,
1777 .pwr.state = mode == DRM_MODE_DPMS_ON,
1778 };
c02ed2bf
BS		 1779 struct {
1780 struct nv50_disp_mthd_v1 base;
1781 struct nv50_disp_sor_dp_pwr_v0 pwr;
1782 } link = {
1783 .base.version = 1,
1784 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1785 .base.hasht = nv_encoder->dcb->hasht,
1786 .base.hashm = nv_encoder->dcb->hashm,
1787 .pwr.state = mode == DRM_MODE_DPMS_ON,
1788 };
83fc083c
BS		 1789 struct drm_device *dev = encoder->dev;
1790 struct drm_encoder *partner;
83fc083c
BS		 1791
1792 nv_encoder->last_dpms = mode;
1793
1794 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1795 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1796
1797 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1798 continue;
1799
1800 if (nv_partner != nv_encoder &&
26cfa813 1801 nv_partner->dcb->or == nv_encoder->dcb->or) {
83fc083c
BS		 1802 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1803 return;
1804 break;
1805 }
1806 }
1807
4874322e 1808 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
d55b4af9
BS		 1809 args.pwr.state = 1;
1810 nvif_mthd(disp->disp, 0, &args, sizeof(args));
c02ed2bf 1811 nvif_mthd(disp->disp, 0, &link, sizeof(link));
4874322e 1812 } else {
d55b4af9 1813 nvif_mthd(disp->disp, 0, &args, sizeof(args));
4874322e 1814 }
83fc083c
BS		 1815}
1816
1817static bool
e225f446 1818nv50_sor_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1819 const struct drm_display_mode *mode,
83fc083c
BS		 1820 struct drm_display_mode *adjusted_mode)
1821{
1822 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1823 struct nouveau_connector *nv_connector;
1824
1825 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1826 if (nv_connector && nv_connector->native_mode) {
1827 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1828 int id = adjusted_mode->base.id;
1829 *adjusted_mode = *nv_connector->native_mode;
1830 adjusted_mode->base.id = id;
1831 }
1832 }
1833
1834 return true;
1835}
1836
4cbb0f8d 1837static void
e84a35a8 1838nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
4cbb0f8d 1839{
e84a35a8
BS		 1840 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1841 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1842 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
648d4dfd 1843 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
e84a35a8
BS		 1844 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1845 evo_data(push, (nv_encoder->ctrl = temp));
1846 } else {
1847 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1848 evo_data(push, (nv_encoder->ctrl = temp));
4cbb0f8d 1849 }
e84a35a8 1850 evo_kick(push, mast);
4cbb0f8d 1851 }
e84a35a8
BS		 1852}
1853
1854static void
1855nv50_sor_disconnect(struct drm_encoder *encoder)
1856{
1857 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1858 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
419e8dc0
BS		 1859
1860 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1861 nv_encoder->crtc = NULL;
e84a35a8
BS		 1862
1863 if (nv_crtc) {
1864 nv50_crtc_prepare(&nv_crtc->base);
1865 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
cc2a9071 1866 nv50_audio_disconnect(encoder, nv_crtc);
e84a35a8
BS		 1867 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1868 }
4cbb0f8d
BS		 1869}
1870
83fc083c 1871static void
e225f446 1872nv50_sor_commit(struct drm_encoder *encoder)
83fc083c
BS		 1873{
1874}
1875
1876static void
e225f446 1877nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
3b6d83d1 1878 struct drm_display_mode *mode)
83fc083c 1879{
a3761fa2
BS		 1880 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1881 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1882 struct {
1883 struct nv50_disp_mthd_v1 base;
1884 struct nv50_disp_sor_lvds_script_v0 lvds;
1885 } lvds = {
1886 .base.version = 1,
1887 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1888 .base.hasht = nv_encoder->dcb->hasht,
1889 .base.hashm = nv_encoder->dcb->hashm,
1890 };
e225f446
BS		 1891 struct nv50_disp *disp = nv50_disp(encoder->dev);
1892 struct nv50_mast *mast = nv50_mast(encoder->dev);
78951d22 1893 struct drm_device *dev = encoder->dev;
77145f1c 1894 struct nouveau_drm *drm = nouveau_drm(dev);
3b6d83d1 1895 struct nouveau_connector *nv_connector;
77145f1c 1896 struct nvbios *bios = &drm->vbios;
a3761fa2 1897 u32 mask, ctrl;
419e8dc0
BS		 1898 u8 owner = 1 << nv_crtc->index;
1899 u8 proto = 0xf;
1900 u8 depth = 0x0;
83fc083c 1901
3b6d83d1 1902 nv_connector = nouveau_encoder_connector_get(nv_encoder);
e84a35a8
BS		 1903 nv_encoder->crtc = encoder->crtc;
1904
3b6d83d1 1905 switch (nv_encoder->dcb->type) {
cb75d97e 1906 case DCB_OUTPUT_TMDS:
3b6d83d1
BS		 1907 if (nv_encoder->dcb->sorconf.link & 1) {
1908 if (mode->clock < 165000)
419e8dc0 1909 proto = 0x1;
3b6d83d1 1910 else
419e8dc0 1911 proto = 0x5;
3b6d83d1 1912 } else {
419e8dc0 1913 proto = 0x2;
3b6d83d1
BS		 1914 }
1915
e84a35a8 1916 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
3b6d83d1 1917 break;
cb75d97e 1918 case DCB_OUTPUT_LVDS:
419e8dc0
BS		 1919 proto = 0x0;
1920
3b6d83d1
BS		 1921 if (bios->fp_no_ddc) {
1922 if (bios->fp.dual_link)
a3761fa2 1923 lvds.lvds.script |= 0x0100;
3b6d83d1 1924 if (bios->fp.if_is_24bit)
a3761fa2 1925 lvds.lvds.script |= 0x0200;
3b6d83d1 1926 } else {
befb51e9 1927 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3b6d83d1 1928 if (((u8 *)nv_connector->edid)[121] == 2)
a3761fa2 1929 lvds.lvds.script |= 0x0100;
3b6d83d1
BS		 1930 } else
1931 if (mode->clock >= bios->fp.duallink_transition_clk) {
a3761fa2 1932 lvds.lvds.script |= 0x0100;
3b6d83d1 1933 }
83fc083c 1934
a3761fa2 1935 if (lvds.lvds.script & 0x0100) {
3b6d83d1 1936 if (bios->fp.strapless_is_24bit & 2)
a3761fa2 1937 lvds.lvds.script |= 0x0200;
3b6d83d1
BS		 1938 } else {
1939 if (bios->fp.strapless_is_24bit & 1)
a3761fa2 1940 lvds.lvds.script |= 0x0200;
3b6d83d1
BS		 1941 }
1942
1943 if (nv_connector->base.display_info.bpc == 8)
a3761fa2 1944 lvds.lvds.script |= 0x0200;
3b6d83d1 1945 }
4a230fa6 1946
a3761fa2 1947 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3b6d83d1 1948 break;
cb75d97e 1949 case DCB_OUTPUT_DP:
3488c57b 1950 if (nv_connector->base.display_info.bpc == 6) {
6e83fda2 1951 nv_encoder->dp.datarate = mode->clock * 18 / 8;
419e8dc0 1952 depth = 0x2;
bf2c886a
BS		 1953 } else
1954 if (nv_connector->base.display_info.bpc == 8) {
6e83fda2 1955 nv_encoder->dp.datarate = mode->clock * 24 / 8;
419e8dc0 1956 depth = 0x5;
bf2c886a
BS		 1957 } else {
1958 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1959 depth = 0x6;
3488c57b 1960 }
6e83fda2
BS		 1961
1962 if (nv_encoder->dcb->sorconf.link & 1)
419e8dc0 1963 proto = 0x8;
6e83fda2 1964 else
419e8dc0 1965 proto = 0x9;
3eee8646 1966 nv50_audio_mode_set(encoder, mode);
6e83fda2 1967 break;
3b6d83d1
BS		 1968 default:
1969 BUG_ON(1);
1970 break;
1971 }
ff8ff503 1972
e84a35a8 1973 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
83fc083c 1974
648d4dfd 1975 if (nv50_vers(mast) >= GF110_DISP) {
e84a35a8
BS		 1976 u32 *push = evo_wait(mast, 3);
1977 if (push) {
419e8dc0
BS		 1978 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1979 u32 syncs = 0x00000001;
1980
1981 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1982 syncs |= 0x00000008;
1983 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1984 syncs |= 0x00000010;
1985
1986 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1987 magic |= 0x00000001;
1988
1989 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1990 evo_data(push, syncs | (depth << 6));
1991 evo_data(push, magic);
e84a35a8 1992 evo_kick(push, mast);
419e8dc0
BS		 1993 }
1994
e84a35a8
BS		 1995 ctrl = proto << 8;
1996 mask = 0x00000f00;
1997 } else {
1998 ctrl = (depth << 16) | (proto << 8);
1999 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2000 ctrl |= 0x00001000;
2001 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2002 ctrl |= 0x00002000;
2003 mask = 0x000f3f00;
83fc083c
BS		 2004 }
2005
e84a35a8 2006 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
83fc083c
BS		 2007}
2008
83fc083c 2009static void
e225f446 2010nv50_sor_destroy(struct drm_encoder *encoder)
83fc083c
BS		 2011{
2012 drm_encoder_cleanup(encoder);
2013 kfree(encoder);
2014}
2015
e225f446
BS		 2016static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2017 .dpms = nv50_sor_dpms,
2018 .mode_fixup = nv50_sor_mode_fixup,
5a885f0b 2019 .prepare = nv50_sor_disconnect,
e225f446
BS		 2020 .commit = nv50_sor_commit,
2021 .mode_set = nv50_sor_mode_set,
2022 .disable = nv50_sor_disconnect,
2023 .get_crtc = nv50_display_crtc_get,
83fc083c
BS		 2024};
2025
e225f446
BS		 2026static const struct drm_encoder_funcs nv50_sor_func = {
2027 .destroy = nv50_sor_destroy,
83fc083c
BS		 2028};
2029
2030static int
e225f446 2031nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
83fc083c 2032{
5ed50209 2033 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 2034 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
83fc083c
BS		 2035 struct nouveau_encoder *nv_encoder;
2036 struct drm_encoder *encoder;
5ed50209
BS		 2037 int type;
2038
2039 switch (dcbe->type) {
2040 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2041 case DCB_OUTPUT_TMDS:
2042 case DCB_OUTPUT_DP:
2043 default:
2044 type = DRM_MODE_ENCODER_TMDS;
2045 break;
2046 }
83fc083c
BS		 2047
2048 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2049 if (!nv_encoder)
2050 return -ENOMEM;
2051 nv_encoder->dcb = dcbe;
2052 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 2053 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
83fc083c
BS		 2054 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2055
2056 encoder = to_drm_encoder(nv_encoder);
2057 encoder->possible_crtcs = dcbe->heads;
2058 encoder->possible_clones = 0;
5ed50209 2059 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
e225f446 2060 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
83fc083c
BS		 2061
2062 drm_mode_connector_attach_encoder(connector, encoder);
2063 return 0;
2064}
26f6d88b 2065
eb6313ad
BS		 2066/******************************************************************************
2067 * PIOR
2068 *****************************************************************************/
2069
2070static void
2071nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2072{
2073 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2074 struct nv50_disp *disp = nv50_disp(encoder->dev);
67cb49c4
BS		 2075 struct {
2076 struct nv50_disp_mthd_v1 base;
2077 struct nv50_disp_pior_pwr_v0 pwr;
2078 } args = {
2079 .base.version = 1,
2080 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2081 .base.hasht = nv_encoder->dcb->hasht,
2082 .base.hashm = nv_encoder->dcb->hashm,
2083 .pwr.state = mode == DRM_MODE_DPMS_ON,
2084 .pwr.type = nv_encoder->dcb->type,
2085 };
2086
2087 nvif_mthd(disp->disp, 0, &args, sizeof(args));
eb6313ad
BS		 2088}
2089
2090static bool
2091nv50_pior_mode_fixup(struct drm_encoder *encoder,
2092 const struct drm_display_mode *mode,
2093 struct drm_display_mode *adjusted_mode)
2094{
2095 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2096 struct nouveau_connector *nv_connector;
2097
2098 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2099 if (nv_connector && nv_connector->native_mode) {
2100 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2101 int id = adjusted_mode->base.id;
2102 *adjusted_mode = *nv_connector->native_mode;
2103 adjusted_mode->base.id = id;
2104 }
2105 }
2106
2107 adjusted_mode->clock *= 2;
2108 return true;
2109}
2110
2111static void
2112nv50_pior_commit(struct drm_encoder *encoder)
2113{
2114}
2115
2116static void
2117nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2118 struct drm_display_mode *adjusted_mode)
2119{
2120 struct nv50_mast *mast = nv50_mast(encoder->dev);
2121 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2122 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2123 struct nouveau_connector *nv_connector;
2124 u8 owner = 1 << nv_crtc->index;
2125 u8 proto, depth;
2126 u32 *push;
2127
2128 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2129 switch (nv_connector->base.display_info.bpc) {
2130 case 10: depth = 0x6; break;
2131 case 8: depth = 0x5; break;
2132 case 6: depth = 0x2; break;
2133 default: depth = 0x0; break;
2134 }
2135
2136 switch (nv_encoder->dcb->type) {
2137 case DCB_OUTPUT_TMDS:
2138 case DCB_OUTPUT_DP:
2139 proto = 0x0;
2140 break;
2141 default:
2142 BUG_ON(1);
2143 break;
2144 }
2145
2146 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2147
2148 push = evo_wait(mast, 8);
2149 if (push) {
648d4dfd 2150 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
eb6313ad
BS		 2151 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2152 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2153 ctrl |= 0x00001000;
2154 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2155 ctrl |= 0x00002000;
2156 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2157 evo_data(push, ctrl);
2158 }
2159
2160 evo_kick(push, mast);
2161 }
2162
2163 nv_encoder->crtc = encoder->crtc;
2164}
2165
2166static void
2167nv50_pior_disconnect(struct drm_encoder *encoder)
2168{
2169 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2170 struct nv50_mast *mast = nv50_mast(encoder->dev);
2171 const int or = nv_encoder->or;
2172 u32 *push;
2173
2174 if (nv_encoder->crtc) {
2175 nv50_crtc_prepare(nv_encoder->crtc);
2176
2177 push = evo_wait(mast, 4);
2178 if (push) {
648d4dfd 2179 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
eb6313ad
BS		 2180 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2181 evo_data(push, 0x00000000);
2182 }
eb6313ad
BS		 2183 evo_kick(push, mast);
2184 }
2185 }
2186
2187 nv_encoder->crtc = NULL;
2188}
2189
2190static void
2191nv50_pior_destroy(struct drm_encoder *encoder)
2192{
2193 drm_encoder_cleanup(encoder);
2194 kfree(encoder);
2195}
2196
2197static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2198 .dpms = nv50_pior_dpms,
2199 .mode_fixup = nv50_pior_mode_fixup,
2200 .prepare = nv50_pior_disconnect,
2201 .commit = nv50_pior_commit,
2202 .mode_set = nv50_pior_mode_set,
2203 .disable = nv50_pior_disconnect,
2204 .get_crtc = nv50_display_crtc_get,
2205};
2206
2207static const struct drm_encoder_funcs nv50_pior_func = {
2208 .destroy = nv50_pior_destroy,
2209};
2210
2211static int
2212nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2213{
2214 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 2215 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
eb6313ad
BS		 2216 struct nouveau_i2c_port *ddc = NULL;
2217 struct nouveau_encoder *nv_encoder;
2218 struct drm_encoder *encoder;
2219 int type;
2220
2221 switch (dcbe->type) {
2222 case DCB_OUTPUT_TMDS:
2223 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2224 type = DRM_MODE_ENCODER_TMDS;
2225 break;
2226 case DCB_OUTPUT_DP:
2227 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2228 type = DRM_MODE_ENCODER_TMDS;
2229 break;
2230 default:
2231 return -ENODEV;
2232 }
2233
2234 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2235 if (!nv_encoder)
2236 return -ENOMEM;
2237 nv_encoder->dcb = dcbe;
2238 nv_encoder->or = ffs(dcbe->or) - 1;
2239 nv_encoder->i2c = ddc;
2240
2241 encoder = to_drm_encoder(nv_encoder);
2242 encoder->possible_crtcs = dcbe->heads;
2243 encoder->possible_clones = 0;
2244 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2245 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2246
2247 drm_mode_connector_attach_encoder(connector, encoder);
2248 return 0;
2249}
2250
ab0af559
BS		 2251/******************************************************************************
2252 * Framebuffer
2253 *****************************************************************************/
2254
8a423647 2255static void
0ad72863 2256nv50_fbdma_fini(struct nv50_fbdma *fbdma)
8a423647 2257{
0ad72863
BS		 2258 int i;
2259 for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2260 nvif_object_fini(&fbdma->base[i]);
2261 nvif_object_fini(&fbdma->core);
8a423647
BS		 2262 list_del(&fbdma->head);
2263 kfree(fbdma);
2264}
2265
2266static int
2267nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2268{
2269 struct nouveau_drm *drm = nouveau_drm(dev);
2270 struct nv50_disp *disp = nv50_disp(dev);
2271 struct nv50_mast *mast = nv50_mast(dev);
4acfd707
BS		 2272 struct __attribute__ ((packed)) {
2273 struct nv_dma_v0 base;
2274 union {
2275 struct nv50_dma_v0 nv50;
2276 struct gf100_dma_v0 gf100;
2277 struct gf110_dma_v0 gf110;
2278 };
2279 } args = {};
8a423647
BS		 2280 struct nv50_fbdma *fbdma;
2281 struct drm_crtc *crtc;
4acfd707 2282 u32 size = sizeof(args.base);
8a423647
BS		 2283 int ret;
2284
2285 list_for_each_entry(fbdma, &disp->fbdma, head) {
0ad72863 2286 if (fbdma->core.handle == name)
8a423647
BS		 2287 return 0;
2288 }
2289
2290 fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2291 if (!fbdma)
2292 return -ENOMEM;
2293 list_add(&fbdma->head, &disp->fbdma);
8a423647 2294
4acfd707
BS		 2295 args.base.target = NV_DMA_V0_TARGET_VRAM;
2296 args.base.access = NV_DMA_V0_ACCESS_RDWR;
2297 args.base.start = offset;
2298 args.base.limit = offset + length - 1;
8a423647 2299
967e7bde 2300 if (drm->device.info.chipset < 0x80) {
4acfd707
BS		 2301 args.nv50.part = NV50_DMA_V0_PART_256;
2302 size += sizeof(args.nv50);
8a423647 2303 } else
967e7bde 2304 if (drm->device.info.chipset < 0xc0) {
4acfd707
BS		 2305 args.nv50.part = NV50_DMA_V0_PART_256;
2306 args.nv50.kind = kind;
2307 size += sizeof(args.nv50);
8a423647 2308 } else
967e7bde 2309 if (drm->device.info.chipset < 0xd0) {
4acfd707
BS		 2310 args.gf100.kind = kind;
2311 size += sizeof(args.gf100);
8a423647 2312 } else {
4acfd707
BS		 2313 args.gf110.page = GF110_DMA_V0_PAGE_LP;
2314 args.gf110.kind = kind;
2315 size += sizeof(args.gf110);
8a423647
BS		 2316 }
2317
2318 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
0ad72863
BS		 2319 struct nv50_head *head = nv50_head(crtc);
2320 int ret = nvif_object_init(&head->sync.base.base.user, NULL,
4acfd707 2321 name, NV_DMA_IN_MEMORY, &args, size,
0ad72863 2322 &fbdma->base[head->base.index]);
8a423647 2323 if (ret) {
0ad72863 2324 nv50_fbdma_fini(fbdma);
8a423647
BS		 2325 return ret;
2326 }
2327 }
2328
0ad72863 2329 ret = nvif_object_init(&mast->base.base.user, NULL, name,
4acfd707 2330 NV_DMA_IN_MEMORY, &args, size,
0ad72863 2331 &fbdma->core);
8a423647 2332 if (ret) {
0ad72863 2333 nv50_fbdma_fini(fbdma);
8a423647
BS		 2334 return ret;
2335 }
2336
2337 return 0;
2338}
2339
ab0af559
BS		 2340static void
2341nv50_fb_dtor(struct drm_framebuffer *fb)
2342{
2343}
2344
2345static int
2346nv50_fb_ctor(struct drm_framebuffer *fb)
2347{
2348 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2349 struct nouveau_drm *drm = nouveau_drm(fb->dev);
2350 struct nouveau_bo *nvbo = nv_fb->nvbo;
8a423647 2351 struct nv50_disp *disp = nv50_disp(fb->dev);
8a423647
BS		 2352 u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2353 u8 tile = nvbo->tile_mode;
ab0af559
BS		 2354
2355 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
2356 NV_ERROR(drm, "framebuffer requires contiguous bo\n");
2357 return -EINVAL;
2358 }
2359
967e7bde 2360 if (drm->device.info.chipset >= 0xc0)
8a423647
BS		 2361 tile >>= 4; /* yep.. */
2362
ab0af559
BS		 2363 switch (fb->depth) {
2364 case 8: nv_fb->r_format = 0x1e00; break;
2365 case 15: nv_fb->r_format = 0xe900; break;
2366 case 16: nv_fb->r_format = 0xe800; break;
2367 case 24:
2368 case 32: nv_fb->r_format = 0xcf00; break;
2369 case 30: nv_fb->r_format = 0xd100; break;
2370 default:
2371 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2372 return -EINVAL;
2373 }
2374
648d4dfd 2375 if (disp->disp->oclass < G82_DISP) {
8a423647
BS		 2376 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2377 (fb->pitches[0] | 0x00100000);
2378 nv_fb->r_format |= kind << 16;
2379 } else
648d4dfd 2380 if (disp->disp->oclass < GF110_DISP) {
8a423647
BS		 2381 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2382 (fb->pitches[0] | 0x00100000);
ab0af559 2383 } else {
8a423647
BS		 2384 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2385 (fb->pitches[0] | 0x01000000);
ab0af559 2386 }
8a423647 2387 nv_fb->r_handle = 0xffff0000 | kind;
ab0af559 2388
f392ec4b
BS		 2389 return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2390 drm->device.info.ram_user, kind);
ab0af559
BS		 2391}
2392
26f6d88b
BS		 2393/******************************************************************************
2394 * Init
2395 *****************************************************************************/
ab0af559 2396
2a44e499 2397void
e225f446 2398nv50_display_fini(struct drm_device *dev)
26f6d88b 2399{
26f6d88b
BS		 2400}
2401
2402int
e225f446 2403nv50_display_init(struct drm_device *dev)
26f6d88b 2404{
9f9bdaaf
BS		 2405 struct nv50_disp *disp = nv50_disp(dev);
2406 struct drm_crtc *crtc;
2407 u32 *push;
2408
2409 push = evo_wait(nv50_mast(dev), 32);
2410 if (!push)
2411 return -EBUSY;
2412
2413 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2414 struct nv50_sync *sync = nv50_sync(crtc);
2415 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
bdb8c212 2416 }
efd272a7 2417
9f9bdaaf 2418 evo_mthd(push, 0x0088, 1);
f45f55c4 2419 evo_data(push, nv50_mast(dev)->base.sync.handle);
9f9bdaaf
BS		 2420 evo_kick(push, nv50_mast(dev));
2421 return 0;
26f6d88b
BS		 2422}
2423
2424void
e225f446 2425nv50_display_destroy(struct drm_device *dev)
26f6d88b 2426{
e225f446 2427 struct nv50_disp *disp = nv50_disp(dev);
8a423647
BS		 2428 struct nv50_fbdma *fbdma, *fbtmp;
2429
2430 list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
0ad72863 2431 nv50_fbdma_fini(fbdma);
8a423647 2432 }
bdb8c212 2433
0ad72863 2434 nv50_dmac_destroy(&disp->mast.base, disp->disp);
26f6d88b 2435
816af2f2 2436 nouveau_bo_unmap(disp->sync);
04c8c210
MS		 2437 if (disp->sync)
2438 nouveau_bo_unpin(disp->sync);
816af2f2 2439 nouveau_bo_ref(NULL, &disp->sync);
51beb428 2440
77145f1c 2441 nouveau_display(dev)->priv = NULL;
26f6d88b
BS		 2442 kfree(disp);
2443}
2444
2445int
e225f446 2446nv50_display_create(struct drm_device *dev)
26f6d88b 2447{
967e7bde 2448 struct nvif_device *device = &nouveau_drm(dev)->device;
77145f1c 2449 struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c 2450 struct dcb_table *dcb = &drm->vbios.dcb;
83fc083c 2451 struct drm_connector *connector, *tmp;
e225f446 2452 struct nv50_disp *disp;
cb75d97e 2453 struct dcb_output *dcbe;
7c5f6a87 2454 int crtcs, ret, i;
26f6d88b
BS		 2455
2456 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2457 if (!disp)
2458 return -ENOMEM;
8a423647 2459 INIT_LIST_HEAD(&disp->fbdma);
77145f1c
BS		 2460
2461 nouveau_display(dev)->priv = disp;
e225f446
BS		 2462 nouveau_display(dev)->dtor = nv50_display_destroy;
2463 nouveau_display(dev)->init = nv50_display_init;
2464 nouveau_display(dev)->fini = nv50_display_fini;
ab0af559
BS		 2465 nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2466 nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
0ad72863 2467 disp->disp = &nouveau_display(dev)->disp;
26f6d88b 2468
b5a794b0
BS		 2469 /* small shared memory area we use for notifiers and semaphores */
2470 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2471 0, 0x0000, NULL, &disp->sync);
2472 if (!ret) {
2473 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
04c8c210 2474 if (!ret) {
b5a794b0 2475 ret = nouveau_bo_map(disp->sync);
04c8c210
MS		 2476 if (ret)
2477 nouveau_bo_unpin(disp->sync);
2478 }
b5a794b0
BS		 2479 if (ret)
2480 nouveau_bo_ref(NULL, &disp->sync);
2481 }
2482
b5a794b0
BS		 2483 if (ret)
2484 goto out;
2485
2486 /* allocate master evo channel */
410f3ec6
BS		 2487 ret = nv50_core_create(disp->disp, disp->sync->bo.offset,
2488 &disp->mast);
b5a794b0
BS		 2489 if (ret)
2490 goto out;
2491
438d99e3 2492 /* create crtc objects to represent the hw heads */
648d4dfd 2493 if (disp->disp->oclass >= GF110_DISP)
db2bec18 2494 crtcs = nvif_rd32(device, 0x022448);
63718a07
BS		 2495 else
2496 crtcs = 2;
2497
7c5f6a87 2498 for (i = 0; i < crtcs; i++) {
0ad72863 2499 ret = nv50_crtc_create(dev, i);
438d99e3
BS		 2500 if (ret)
2501 goto out;
2502 }
2503
83fc083c
BS		 2504 /* create encoder/connector objects based on VBIOS DCB table */
2505 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2506 connector = nouveau_connector_create(dev, dcbe->connector);
2507 if (IS_ERR(connector))
2508 continue;
2509
eb6313ad
BS		 2510 if (dcbe->location == DCB_LOC_ON_CHIP) {
2511 switch (dcbe->type) {
2512 case DCB_OUTPUT_TMDS:
2513 case DCB_OUTPUT_LVDS:
2514 case DCB_OUTPUT_DP:
2515 ret = nv50_sor_create(connector, dcbe);
2516 break;
2517 case DCB_OUTPUT_ANALOG:
2518 ret = nv50_dac_create(connector, dcbe);
2519 break;
2520 default:
2521 ret = -ENODEV;
2522 break;
2523 }
2524 } else {
2525 ret = nv50_pior_create(connector, dcbe);
83fc083c
BS		 2526 }
2527
eb6313ad
BS		 2528 if (ret) {
2529 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2530 dcbe->location, dcbe->type,
2531 ffs(dcbe->or) - 1, ret);
94f54f53 2532 ret = 0;
83fc083c
BS		 2533 }
2534 }
2535
2536 /* cull any connectors we created that don't have an encoder */
2537 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2538 if (connector->encoder_ids[0])
2539 continue;
2540
77145f1c 2541 NV_WARN(drm, "%s has no encoders, removing\n",
8c6c361a 2542 connector->name);
83fc083c
BS		 2543 connector->funcs->destroy(connector);
2544 }
2545
26f6d88b
BS		 2546out:
2547 if (ret)
e225f446 2548 nv50_display_destroy(dev);
26f6d88b
BS		 2549 return ret;
2550}
Linux 6.x block layer and io_uring tree(s)