Commit | Line | Data |
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e225f446 | 1 | /* |
26f6d88b BS |
2 | * Copyright 2011 Red Hat Inc. |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
83fc083c | 26 | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/drm_crtc_helper.h> | |
26f6d88b | 29 | |
77145f1c BS |
30 | #include "nouveau_drm.h" |
31 | #include "nouveau_dma.h" | |
32 | #include "nouveau_gem.h" | |
26f6d88b BS |
33 | #include "nouveau_connector.h" |
34 | #include "nouveau_encoder.h" | |
35 | #include "nouveau_crtc.h" | |
f589be88 | 36 | #include "nouveau_fence.h" |
3a89cd02 | 37 | #include "nv50_display.h" |
26f6d88b | 38 | |
b5a794b0 | 39 | #include <core/client.h> |
77145f1c | 40 | #include <core/gpuobj.h> |
b5a794b0 | 41 | #include <core/class.h> |
77145f1c BS |
42 | |
43 | #include <subdev/timer.h> | |
44 | #include <subdev/bar.h> | |
45 | #include <subdev/fb.h> | |
5ed50209 | 46 | #include <subdev/i2c.h> |
77145f1c | 47 | |
8a46438a BS |
48 | #define EVO_DMA_NR 9 |
49 | ||
bdb8c212 | 50 | #define EVO_MASTER (0x00) |
a63a97eb | 51 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
52 | #define EVO_OVLY(c) (0x05 + (c)) |
53 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
54 | #define EVO_CURS(c) (0x0d + (c)) |
55 | ||
816af2f2 BS |
56 | /* offsets in shared sync bo of various structures */ |
57 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
9f9bdaaf BS |
58 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
59 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) | |
60 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) | |
816af2f2 | 61 | |
b5a794b0 BS |
62 | #define EVO_CORE_HANDLE (0xd1500000) |
63 | #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i)) | |
64 | #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff)) | |
65 | #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \ | |
66 | (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8)) | |
67 | ||
68 | /****************************************************************************** | |
69 | * EVO channel | |
70 | *****************************************************************************/ | |
71 | ||
e225f446 | 72 | struct nv50_chan { |
b5a794b0 BS |
73 | struct nouveau_object *user; |
74 | u32 handle; | |
75 | }; | |
76 | ||
77 | static int | |
e225f446 BS |
78 | nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head, |
79 | void *data, u32 size, struct nv50_chan *chan) | |
b5a794b0 BS |
80 | { |
81 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
82 | const u32 oclass = EVO_CHAN_OCLASS(bclass, core); | |
83 | const u32 handle = EVO_CHAN_HANDLE(bclass, head); | |
84 | int ret; | |
85 | ||
86 | ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle, | |
87 | oclass, data, size, &chan->user); | |
88 | if (ret) | |
89 | return ret; | |
90 | ||
91 | chan->handle = handle; | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static void | |
e225f446 | 96 | nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan) |
b5a794b0 BS |
97 | { |
98 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
99 | if (chan->handle) | |
100 | nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle); | |
101 | } | |
102 | ||
103 | /****************************************************************************** | |
104 | * PIO EVO channel | |
105 | *****************************************************************************/ | |
106 | ||
e225f446 BS |
107 | struct nv50_pioc { |
108 | struct nv50_chan base; | |
b5a794b0 BS |
109 | }; |
110 | ||
111 | static void | |
e225f446 | 112 | nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc) |
b5a794b0 | 113 | { |
e225f446 | 114 | nv50_chan_destroy(core, &pioc->base); |
b5a794b0 BS |
115 | } |
116 | ||
117 | static int | |
e225f446 BS |
118 | nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head, |
119 | void *data, u32 size, struct nv50_pioc *pioc) | |
b5a794b0 | 120 | { |
e225f446 | 121 | return nv50_chan_create(core, bclass, head, data, size, &pioc->base); |
b5a794b0 BS |
122 | } |
123 | ||
124 | /****************************************************************************** | |
125 | * DMA EVO channel | |
126 | *****************************************************************************/ | |
127 | ||
e225f446 BS |
128 | struct nv50_dmac { |
129 | struct nv50_chan base; | |
3376ee37 BS |
130 | dma_addr_t handle; |
131 | u32 *ptr; | |
59ad1465 DV |
132 | |
133 | /* Protects against concurrent pushbuf access to this channel, lock is | |
134 | * grabbed by evo_wait (if the pushbuf reservation is successful) and | |
135 | * dropped again by evo_kick. */ | |
136 | struct mutex lock; | |
b5a794b0 BS |
137 | }; |
138 | ||
139 | static void | |
e225f446 | 140 | nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac) |
b5a794b0 BS |
141 | { |
142 | if (dmac->ptr) { | |
143 | struct pci_dev *pdev = nv_device(core)->pdev; | |
144 | pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); | |
145 | } | |
146 | ||
e225f446 | 147 | nv50_chan_destroy(core, &dmac->base); |
b5a794b0 BS |
148 | } |
149 | ||
150 | static int | |
47057302 | 151 | nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
b5a794b0 BS |
152 | { |
153 | struct nouveau_fb *pfb = nouveau_fb(core); | |
154 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
155 | struct nouveau_object *object; | |
47057302 BS |
156 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
157 | NV_DMA_IN_MEMORY_CLASS, | |
158 | &(struct nv_dma_class) { | |
159 | .flags = NV_DMA_TARGET_VRAM | | |
160 | NV_DMA_ACCESS_RDWR, | |
161 | .start = 0, | |
162 | .limit = pfb->ram.size - 1, | |
163 | .conf0 = NV50_DMA_CONF0_ENABLE | | |
164 | NV50_DMA_CONF0_PART_256, | |
165 | }, sizeof(struct nv_dma_class), &object); | |
166 | if (ret) | |
167 | return ret; | |
b5a794b0 | 168 | |
47057302 BS |
169 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
170 | NV_DMA_IN_MEMORY_CLASS, | |
b5a794b0 | 171 | &(struct nv_dma_class) { |
47057302 BS |
172 | .flags = NV_DMA_TARGET_VRAM | |
173 | NV_DMA_ACCESS_RDWR, | |
174 | .start = 0, | |
175 | .limit = pfb->ram.size - 1, | |
176 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 | | |
177 | NV50_DMA_CONF0_PART_256, | |
b5a794b0 BS |
178 | }, sizeof(struct nv_dma_class), &object); |
179 | if (ret) | |
180 | return ret; | |
181 | ||
47057302 BS |
182 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
183 | NV_DMA_IN_MEMORY_CLASS, | |
184 | &(struct nv_dma_class) { | |
185 | .flags = NV_DMA_TARGET_VRAM | | |
186 | NV_DMA_ACCESS_RDWR, | |
187 | .start = 0, | |
188 | .limit = pfb->ram.size - 1, | |
189 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a | | |
190 | NV50_DMA_CONF0_PART_256, | |
191 | }, sizeof(struct nv_dma_class), &object); | |
192 | return ret; | |
193 | } | |
194 | ||
195 | static int | |
196 | nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) | |
197 | { | |
198 | struct nouveau_fb *pfb = nouveau_fb(core); | |
199 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
200 | struct nouveau_object *object; | |
201 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, | |
202 | NV_DMA_IN_MEMORY_CLASS, | |
203 | &(struct nv_dma_class) { | |
204 | .flags = NV_DMA_TARGET_VRAM | | |
205 | NV_DMA_ACCESS_RDWR, | |
206 | .start = 0, | |
207 | .limit = pfb->ram.size - 1, | |
208 | .conf0 = NVC0_DMA_CONF0_ENABLE, | |
209 | }, sizeof(struct nv_dma_class), &object); | |
b5a794b0 BS |
210 | if (ret) |
211 | return ret; | |
212 | ||
47057302 | 213 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
b5a794b0 BS |
214 | NV_DMA_IN_MEMORY_CLASS, |
215 | &(struct nv_dma_class) { | |
216 | .flags = NV_DMA_TARGET_VRAM | | |
217 | NV_DMA_ACCESS_RDWR, | |
47057302 BS |
218 | .start = 0, |
219 | .limit = pfb->ram.size - 1, | |
220 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, | |
b5a794b0 BS |
221 | }, sizeof(struct nv_dma_class), &object); |
222 | if (ret) | |
47057302 | 223 | return ret; |
b5a794b0 | 224 | |
47057302 | 225 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
b5a794b0 BS |
226 | NV_DMA_IN_MEMORY_CLASS, |
227 | &(struct nv_dma_class) { | |
228 | .flags = NV_DMA_TARGET_VRAM | | |
229 | NV_DMA_ACCESS_RDWR, | |
230 | .start = 0, | |
231 | .limit = pfb->ram.size - 1, | |
47057302 | 232 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, |
b5a794b0 | 233 | }, sizeof(struct nv_dma_class), &object); |
47057302 BS |
234 | return ret; |
235 | } | |
236 | ||
237 | static int | |
238 | nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) | |
239 | { | |
240 | struct nouveau_fb *pfb = nouveau_fb(core); | |
241 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
242 | struct nouveau_object *object; | |
243 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, | |
244 | NV_DMA_IN_MEMORY_CLASS, | |
245 | &(struct nv_dma_class) { | |
246 | .flags = NV_DMA_TARGET_VRAM | | |
247 | NV_DMA_ACCESS_RDWR, | |
248 | .start = 0, | |
249 | .limit = pfb->ram.size - 1, | |
250 | .conf0 = NVD0_DMA_CONF0_ENABLE | | |
251 | NVD0_DMA_CONF0_PAGE_LP, | |
252 | }, sizeof(struct nv_dma_class), &object); | |
b5a794b0 | 253 | if (ret) |
47057302 | 254 | return ret; |
b5a794b0 | 255 | |
47057302 | 256 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
b5a794b0 BS |
257 | NV_DMA_IN_MEMORY_CLASS, |
258 | &(struct nv_dma_class) { | |
259 | .flags = NV_DMA_TARGET_VRAM | | |
260 | NV_DMA_ACCESS_RDWR, | |
261 | .start = 0, | |
262 | .limit = pfb->ram.size - 1, | |
47057302 | 263 | .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe | |
b5a794b0 BS |
264 | NVD0_DMA_CONF0_PAGE_LP, |
265 | }, sizeof(struct nv_dma_class), &object); | |
47057302 BS |
266 | return ret; |
267 | } | |
268 | ||
269 | static int | |
e225f446 | 270 | nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head, |
47057302 | 271 | void *data, u32 size, u64 syncbuf, |
e225f446 | 272 | struct nv50_dmac *dmac) |
47057302 BS |
273 | { |
274 | struct nouveau_fb *pfb = nouveau_fb(core); | |
275 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
276 | struct nouveau_object *object; | |
277 | u32 pushbuf = *(u32 *)data; | |
278 | int ret; | |
279 | ||
59ad1465 DV |
280 | mutex_init(&dmac->lock); |
281 | ||
47057302 BS |
282 | dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE, |
283 | &dmac->handle); | |
284 | if (!dmac->ptr) | |
285 | return -ENOMEM; | |
286 | ||
287 | ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf, | |
288 | NV_DMA_FROM_MEMORY_CLASS, | |
289 | &(struct nv_dma_class) { | |
290 | .flags = NV_DMA_TARGET_PCI_US | | |
291 | NV_DMA_ACCESS_RD, | |
292 | .start = dmac->handle + 0x0000, | |
293 | .limit = dmac->handle + 0x0fff, | |
294 | }, sizeof(struct nv_dma_class), &object); | |
b5a794b0 | 295 | if (ret) |
47057302 | 296 | return ret; |
b5a794b0 | 297 | |
e225f446 | 298 | ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base); |
47057302 BS |
299 | if (ret) |
300 | return ret; | |
301 | ||
302 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync, | |
303 | NV_DMA_IN_MEMORY_CLASS, | |
304 | &(struct nv_dma_class) { | |
305 | .flags = NV_DMA_TARGET_VRAM | | |
306 | NV_DMA_ACCESS_RDWR, | |
307 | .start = syncbuf + 0x0000, | |
308 | .limit = syncbuf + 0x0fff, | |
309 | }, sizeof(struct nv_dma_class), &object); | |
310 | if (ret) | |
311 | return ret; | |
312 | ||
313 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM, | |
b5a794b0 BS |
314 | NV_DMA_IN_MEMORY_CLASS, |
315 | &(struct nv_dma_class) { | |
316 | .flags = NV_DMA_TARGET_VRAM | | |
317 | NV_DMA_ACCESS_RDWR, | |
318 | .start = 0, | |
319 | .limit = pfb->ram.size - 1, | |
b5a794b0 | 320 | }, sizeof(struct nv_dma_class), &object); |
b5a794b0 | 321 | if (ret) |
47057302 BS |
322 | return ret; |
323 | ||
324 | if (nv_device(core)->card_type < NV_C0) | |
325 | ret = nv50_dmac_create_fbdma(core, dmac->base.handle); | |
326 | else | |
327 | if (nv_device(core)->card_type < NV_D0) | |
328 | ret = nvc0_dmac_create_fbdma(core, dmac->base.handle); | |
329 | else | |
330 | ret = nvd0_dmac_create_fbdma(core, dmac->base.handle); | |
b5a794b0 BS |
331 | return ret; |
332 | } | |
333 | ||
e225f446 BS |
334 | struct nv50_mast { |
335 | struct nv50_dmac base; | |
b5a794b0 BS |
336 | }; |
337 | ||
e225f446 BS |
338 | struct nv50_curs { |
339 | struct nv50_pioc base; | |
b5a794b0 BS |
340 | }; |
341 | ||
e225f446 BS |
342 | struct nv50_sync { |
343 | struct nv50_dmac base; | |
9f9bdaaf BS |
344 | u32 addr; |
345 | u32 data; | |
3376ee37 BS |
346 | }; |
347 | ||
e225f446 BS |
348 | struct nv50_ovly { |
349 | struct nv50_dmac base; | |
b5a794b0 | 350 | }; |
f20ce962 | 351 | |
e225f446 BS |
352 | struct nv50_oimm { |
353 | struct nv50_pioc base; | |
26f6d88b BS |
354 | }; |
355 | ||
e225f446 | 356 | struct nv50_head { |
dd0e3d53 | 357 | struct nouveau_crtc base; |
e225f446 BS |
358 | struct nv50_curs curs; |
359 | struct nv50_sync sync; | |
360 | struct nv50_ovly ovly; | |
361 | struct nv50_oimm oimm; | |
b5a794b0 BS |
362 | }; |
363 | ||
e225f446 BS |
364 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
365 | #define nv50_curs(c) (&nv50_head(c)->curs) | |
366 | #define nv50_sync(c) (&nv50_head(c)->sync) | |
367 | #define nv50_ovly(c) (&nv50_head(c)->ovly) | |
368 | #define nv50_oimm(c) (&nv50_head(c)->oimm) | |
369 | #define nv50_chan(c) (&(c)->base.base) | |
370 | #define nv50_vers(c) nv_mclass(nv50_chan(c)->user) | |
b5a794b0 | 371 | |
e225f446 | 372 | struct nv50_disp { |
b5a794b0 | 373 | struct nouveau_object *core; |
e225f446 | 374 | struct nv50_mast mast; |
b5a794b0 | 375 | |
b5a794b0 BS |
376 | u32 modeset; |
377 | ||
378 | struct nouveau_bo *sync; | |
dd0e3d53 BS |
379 | }; |
380 | ||
e225f446 BS |
381 | static struct nv50_disp * |
382 | nv50_disp(struct drm_device *dev) | |
26f6d88b | 383 | { |
77145f1c | 384 | return nouveau_display(dev)->priv; |
26f6d88b BS |
385 | } |
386 | ||
e225f446 | 387 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
b5a794b0 | 388 | |
bdb8c212 | 389 | static struct drm_crtc * |
e225f446 | 390 | nv50_display_crtc_get(struct drm_encoder *encoder) |
bdb8c212 BS |
391 | { |
392 | return nouveau_encoder(encoder)->crtc; | |
393 | } | |
394 | ||
395 | /****************************************************************************** | |
396 | * EVO channel helpers | |
397 | *****************************************************************************/ | |
51beb428 | 398 | static u32 * |
b5a794b0 | 399 | evo_wait(void *evoc, int nr) |
51beb428 | 400 | { |
e225f446 | 401 | struct nv50_dmac *dmac = evoc; |
b5a794b0 | 402 | u32 put = nv_ro32(dmac->base.user, 0x0000) / 4; |
51beb428 | 403 | |
59ad1465 | 404 | mutex_lock(&dmac->lock); |
de8268c5 | 405 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
b5a794b0 | 406 | dmac->ptr[put] = 0x20000000; |
51beb428 | 407 | |
b5a794b0 BS |
408 | nv_wo32(dmac->base.user, 0x0000, 0x00000000); |
409 | if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) { | |
59ad1465 | 410 | mutex_unlock(&dmac->lock); |
b5a794b0 | 411 | NV_ERROR(dmac->base.user, "channel stalled\n"); |
51beb428 BS |
412 | return NULL; |
413 | } | |
414 | ||
415 | put = 0; | |
416 | } | |
417 | ||
b5a794b0 | 418 | return dmac->ptr + put; |
51beb428 BS |
419 | } |
420 | ||
421 | static void | |
b5a794b0 | 422 | evo_kick(u32 *push, void *evoc) |
51beb428 | 423 | { |
e225f446 | 424 | struct nv50_dmac *dmac = evoc; |
b5a794b0 | 425 | nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
59ad1465 | 426 | mutex_unlock(&dmac->lock); |
51beb428 BS |
427 | } |
428 | ||
429 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) | |
430 | #define evo_data(p,d) *((p)++) = (d) | |
431 | ||
3376ee37 BS |
432 | static bool |
433 | evo_sync_wait(void *data) | |
434 | { | |
5cc027f6 BS |
435 | if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) |
436 | return true; | |
437 | usleep_range(1, 2); | |
438 | return false; | |
3376ee37 BS |
439 | } |
440 | ||
441 | static int | |
b5a794b0 | 442 | evo_sync(struct drm_device *dev) |
3376ee37 | 443 | { |
77145f1c | 444 | struct nouveau_device *device = nouveau_dev(dev); |
e225f446 BS |
445 | struct nv50_disp *disp = nv50_disp(dev); |
446 | struct nv50_mast *mast = nv50_mast(dev); | |
b5a794b0 | 447 | u32 *push = evo_wait(mast, 8); |
3376ee37 | 448 | if (push) { |
816af2f2 | 449 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
3376ee37 | 450 | evo_mthd(push, 0x0084, 1); |
816af2f2 | 451 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
3376ee37 BS |
452 | evo_mthd(push, 0x0080, 2); |
453 | evo_data(push, 0x00000000); | |
454 | evo_data(push, 0x00000000); | |
b5a794b0 | 455 | evo_kick(push, mast); |
77145f1c | 456 | if (nv_wait_cb(device, evo_sync_wait, disp->sync)) |
3376ee37 BS |
457 | return 0; |
458 | } | |
459 | ||
460 | return -EBUSY; | |
461 | } | |
462 | ||
463 | /****************************************************************************** | |
a63a97eb | 464 | * Page flipping channel |
3376ee37 BS |
465 | *****************************************************************************/ |
466 | struct nouveau_bo * | |
e225f446 | 467 | nv50_display_crtc_sema(struct drm_device *dev, int crtc) |
3376ee37 | 468 | { |
e225f446 | 469 | return nv50_disp(dev)->sync; |
3376ee37 BS |
470 | } |
471 | ||
9f9bdaaf BS |
472 | struct nv50_display_flip { |
473 | struct nv50_disp *disp; | |
474 | struct nv50_sync *chan; | |
475 | }; | |
476 | ||
477 | static bool | |
478 | nv50_display_flip_wait(void *data) | |
479 | { | |
480 | struct nv50_display_flip *flip = data; | |
481 | if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == | |
482 | flip->chan->data); | |
483 | return true; | |
484 | usleep_range(1, 2); | |
485 | return false; | |
486 | } | |
487 | ||
3376ee37 | 488 | void |
e225f446 | 489 | nv50_display_flip_stop(struct drm_crtc *crtc) |
3376ee37 | 490 | { |
9f9bdaaf BS |
491 | struct nouveau_device *device = nouveau_dev(crtc->dev); |
492 | struct nv50_display_flip flip = { | |
493 | .disp = nv50_disp(crtc->dev), | |
494 | .chan = nv50_sync(crtc), | |
495 | }; | |
3376ee37 BS |
496 | u32 *push; |
497 | ||
9f9bdaaf | 498 | push = evo_wait(flip.chan, 8); |
3376ee37 BS |
499 | if (push) { |
500 | evo_mthd(push, 0x0084, 1); | |
501 | evo_data(push, 0x00000000); | |
502 | evo_mthd(push, 0x0094, 1); | |
503 | evo_data(push, 0x00000000); | |
504 | evo_mthd(push, 0x00c0, 1); | |
505 | evo_data(push, 0x00000000); | |
506 | evo_mthd(push, 0x0080, 1); | |
507 | evo_data(push, 0x00000000); | |
9f9bdaaf | 508 | evo_kick(push, flip.chan); |
3376ee37 | 509 | } |
9f9bdaaf BS |
510 | |
511 | nv_wait_cb(device, nv50_display_flip_wait, &flip); | |
3376ee37 BS |
512 | } |
513 | ||
514 | int | |
e225f446 | 515 | nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
3376ee37 BS |
516 | struct nouveau_channel *chan, u32 swap_interval) |
517 | { | |
518 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
3376ee37 | 519 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
e225f446 | 520 | struct nv50_sync *sync = nv50_sync(crtc); |
9f9bdaaf | 521 | int head = nv_crtc->index, ret; |
3376ee37 | 522 | u32 *push; |
3376ee37 BS |
523 | |
524 | swap_interval <<= 4; | |
525 | if (swap_interval == 0) | |
526 | swap_interval |= 0x100; | |
f60b6e7a BS |
527 | if (chan == NULL) |
528 | evo_sync(crtc->dev); | |
3376ee37 | 529 | |
b5a794b0 | 530 | push = evo_wait(sync, 128); |
3376ee37 BS |
531 | if (unlikely(push == NULL)) |
532 | return -EBUSY; | |
533 | ||
9f9bdaaf BS |
534 | if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) { |
535 | ret = RING_SPACE(chan, 8); | |
536 | if (ret) | |
537 | return ret; | |
538 | ||
539 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); | |
540 | OUT_RING (chan, NvEvoSema0 + head); | |
541 | OUT_RING (chan, sync->addr ^ 0x10); | |
542 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); | |
543 | OUT_RING (chan, sync->data + 1); | |
544 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); | |
545 | OUT_RING (chan, sync->addr); | |
546 | OUT_RING (chan, sync->data); | |
547 | } else | |
548 | if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) { | |
549 | u64 addr = nv84_fence_crtc(chan, head) + sync->addr; | |
550 | ret = RING_SPACE(chan, 12); | |
551 | if (ret) | |
552 | return ret; | |
553 | ||
554 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
555 | OUT_RING (chan, chan->vram); | |
556 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
557 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
558 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
559 | OUT_RING (chan, sync->data + 1); | |
560 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
561 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
562 | OUT_RING (chan, upper_32_bits(addr)); | |
563 | OUT_RING (chan, lower_32_bits(addr)); | |
564 | OUT_RING (chan, sync->data); | |
565 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); | |
566 | } else | |
567 | if (chan) { | |
568 | u64 addr = nv84_fence_crtc(chan, head) + sync->addr; | |
569 | ret = RING_SPACE(chan, 10); | |
570 | if (ret) | |
571 | return ret; | |
572 | ||
573 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
574 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
575 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
576 | OUT_RING (chan, sync->data + 1); | |
577 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | | |
578 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
579 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
580 | OUT_RING (chan, upper_32_bits(addr)); | |
581 | OUT_RING (chan, lower_32_bits(addr)); | |
582 | OUT_RING (chan, sync->data); | |
583 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | | |
584 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
585 | } | |
35bcf5d5 | 586 | |
9f9bdaaf BS |
587 | if (chan) { |
588 | sync->addr ^= 0x10; | |
589 | sync->data++; | |
3376ee37 | 590 | FIRE_RING (chan); |
3376ee37 BS |
591 | } |
592 | ||
593 | /* queue the flip */ | |
594 | evo_mthd(push, 0x0100, 1); | |
595 | evo_data(push, 0xfffe0000); | |
596 | evo_mthd(push, 0x0084, 1); | |
597 | evo_data(push, swap_interval); | |
598 | if (!(swap_interval & 0x00000100)) { | |
599 | evo_mthd(push, 0x00e0, 1); | |
600 | evo_data(push, 0x40000000); | |
601 | } | |
602 | evo_mthd(push, 0x0088, 4); | |
9f9bdaaf BS |
603 | evo_data(push, sync->addr); |
604 | evo_data(push, sync->data++); | |
605 | evo_data(push, sync->data); | |
3376ee37 BS |
606 | evo_data(push, NvEvoSync); |
607 | evo_mthd(push, 0x00a0, 2); | |
608 | evo_data(push, 0x00000000); | |
609 | evo_data(push, 0x00000000); | |
610 | evo_mthd(push, 0x00c0, 1); | |
611 | evo_data(push, nv_fb->r_dma); | |
612 | evo_mthd(push, 0x0110, 2); | |
613 | evo_data(push, 0x00000000); | |
614 | evo_data(push, 0x00000000); | |
e225f446 | 615 | if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) { |
ed5085a5 BS |
616 | evo_mthd(push, 0x0800, 5); |
617 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
618 | evo_data(push, 0); | |
619 | evo_data(push, (fb->height << 16) | fb->width); | |
620 | evo_data(push, nv_fb->r_pitch); | |
621 | evo_data(push, nv_fb->r_format); | |
622 | } else { | |
623 | evo_mthd(push, 0x0400, 5); | |
624 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
625 | evo_data(push, 0); | |
626 | evo_data(push, (fb->height << 16) | fb->width); | |
627 | evo_data(push, nv_fb->r_pitch); | |
628 | evo_data(push, nv_fb->r_format); | |
629 | } | |
3376ee37 BS |
630 | evo_mthd(push, 0x0080, 1); |
631 | evo_data(push, 0x00000000); | |
b5a794b0 | 632 | evo_kick(push, sync); |
3376ee37 BS |
633 | return 0; |
634 | } | |
635 | ||
438d99e3 BS |
636 | /****************************************************************************** |
637 | * CRTC | |
638 | *****************************************************************************/ | |
639 | static int | |
e225f446 | 640 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 641 | { |
e225f446 | 642 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de691855 BS |
643 | struct nouveau_connector *nv_connector; |
644 | struct drm_connector *connector; | |
645 | u32 *push, mode = 0x00; | |
438d99e3 | 646 | |
488ff207 | 647 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
de691855 BS |
648 | connector = &nv_connector->base; |
649 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
650 | if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) | |
651 | mode = DITHERING_MODE_DYNAMIC2X2; | |
652 | } else { | |
653 | mode = nv_connector->dithering_mode; | |
654 | } | |
655 | ||
656 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { | |
657 | if (connector->display_info.bpc >= 8) | |
658 | mode |= DITHERING_DEPTH_8BPC; | |
659 | } else { | |
660 | mode |= nv_connector->dithering_depth; | |
438d99e3 BS |
661 | } |
662 | ||
de8268c5 | 663 | push = evo_wait(mast, 4); |
438d99e3 | 664 | if (push) { |
e225f446 | 665 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
666 | evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); |
667 | evo_data(push, mode); | |
668 | } else | |
e225f446 | 669 | if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) { |
de8268c5 BS |
670 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); |
671 | evo_data(push, mode); | |
672 | } else { | |
673 | evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); | |
674 | evo_data(push, mode); | |
675 | } | |
676 | ||
438d99e3 BS |
677 | if (update) { |
678 | evo_mthd(push, 0x0080, 1); | |
679 | evo_data(push, 0x00000000); | |
680 | } | |
de8268c5 | 681 | evo_kick(push, mast); |
438d99e3 BS |
682 | } |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static int | |
e225f446 | 688 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 689 | { |
e225f446 | 690 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
92854622 | 691 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
3376ee37 | 692 | struct drm_crtc *crtc = &nv_crtc->base; |
f3fdc52d | 693 | struct nouveau_connector *nv_connector; |
92854622 BS |
694 | int mode = DRM_MODE_SCALE_NONE; |
695 | u32 oX, oY, *push; | |
f3fdc52d | 696 | |
92854622 BS |
697 | /* start off at the resolution we programmed the crtc for, this |
698 | * effectively handles NONE/FULL scaling | |
699 | */ | |
f3fdc52d | 700 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
92854622 BS |
701 | if (nv_connector && nv_connector->native_mode) |
702 | mode = nv_connector->scaling_mode; | |
703 | ||
704 | if (mode != DRM_MODE_SCALE_NONE) | |
705 | omode = nv_connector->native_mode; | |
706 | else | |
707 | omode = umode; | |
708 | ||
709 | oX = omode->hdisplay; | |
710 | oY = omode->vdisplay; | |
711 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
712 | oY *= 2; | |
713 | ||
714 | /* add overscan compensation if necessary, will keep the aspect | |
715 | * ratio the same as the backend mode unless overridden by the | |
716 | * user setting both hborder and vborder properties. | |
717 | */ | |
718 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
719 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
720 | nv_connector->edid && | |
721 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
722 | u32 bX = nv_connector->underscan_hborder; | |
723 | u32 bY = nv_connector->underscan_vborder; | |
724 | u32 aspect = (oY << 19) / oX; | |
725 | ||
726 | if (bX) { | |
727 | oX -= (bX * 2); | |
728 | if (bY) oY -= (bY * 2); | |
729 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
730 | } else { | |
731 | oX -= (oX >> 4) + 32; | |
732 | if (bY) oY -= (bY * 2); | |
733 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
734 | } | |
735 | } | |
736 | ||
737 | /* handle CENTER/ASPECT scaling, taking into account the areas | |
738 | * removed already for overscan compensation | |
739 | */ | |
740 | switch (mode) { | |
741 | case DRM_MODE_SCALE_CENTER: | |
742 | oX = min((u32)umode->hdisplay, oX); | |
743 | oY = min((u32)umode->vdisplay, oY); | |
744 | /* fall-through */ | |
745 | case DRM_MODE_SCALE_ASPECT: | |
746 | if (oY < oX) { | |
747 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; | |
748 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
749 | } else { | |
750 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; | |
751 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
f3fdc52d | 752 | } |
92854622 BS |
753 | break; |
754 | default: | |
755 | break; | |
f3fdc52d | 756 | } |
438d99e3 | 757 | |
de8268c5 | 758 | push = evo_wait(mast, 8); |
438d99e3 | 759 | if (push) { |
e225f446 | 760 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
761 | /*XXX: SCALE_CTRL_ACTIVE??? */ |
762 | evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); | |
763 | evo_data(push, (oY << 16) | oX); | |
764 | evo_data(push, (oY << 16) | oX); | |
765 | evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); | |
766 | evo_data(push, 0x00000000); | |
767 | evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); | |
768 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
769 | } else { | |
770 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); | |
771 | evo_data(push, (oY << 16) | oX); | |
772 | evo_data(push, (oY << 16) | oX); | |
773 | evo_data(push, (oY << 16) | oX); | |
774 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); | |
775 | evo_data(push, 0x00000000); | |
776 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); | |
777 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
778 | } | |
779 | ||
780 | evo_kick(push, mast); | |
781 | ||
438d99e3 | 782 | if (update) { |
e225f446 BS |
783 | nv50_display_flip_stop(crtc); |
784 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | |
438d99e3 | 785 | } |
438d99e3 BS |
786 | } |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
f9887d09 | 791 | static int |
e225f446 | 792 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
f9887d09 | 793 | { |
e225f446 | 794 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
f9887d09 BS |
795 | u32 *push, hue, vib; |
796 | int adj; | |
797 | ||
798 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; | |
799 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; | |
800 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; | |
801 | ||
802 | push = evo_wait(mast, 16); | |
803 | if (push) { | |
e225f446 | 804 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
f9887d09 BS |
805 | evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); |
806 | evo_data(push, (hue << 20) | (vib << 8)); | |
807 | } else { | |
808 | evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); | |
809 | evo_data(push, (hue << 20) | (vib << 8)); | |
810 | } | |
811 | ||
812 | if (update) { | |
813 | evo_mthd(push, 0x0080, 1); | |
814 | evo_data(push, 0x00000000); | |
815 | } | |
816 | evo_kick(push, mast); | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
438d99e3 | 822 | static int |
e225f446 | 823 | nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, |
438d99e3 BS |
824 | int x, int y, bool update) |
825 | { | |
826 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); | |
e225f446 | 827 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
438d99e3 BS |
828 | u32 *push; |
829 | ||
de8268c5 | 830 | push = evo_wait(mast, 16); |
438d99e3 | 831 | if (push) { |
e225f446 | 832 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
833 | evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); |
834 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
835 | evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); | |
836 | evo_data(push, (fb->height << 16) | fb->width); | |
837 | evo_data(push, nvfb->r_pitch); | |
838 | evo_data(push, nvfb->r_format); | |
839 | evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); | |
840 | evo_data(push, (y << 16) | x); | |
e225f446 | 841 | if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) { |
de8268c5 BS |
842 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
843 | evo_data(push, nvfb->r_dma); | |
844 | } | |
845 | } else { | |
846 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); | |
847 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
848 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); | |
849 | evo_data(push, (fb->height << 16) | fb->width); | |
850 | evo_data(push, nvfb->r_pitch); | |
851 | evo_data(push, nvfb->r_format); | |
852 | evo_data(push, nvfb->r_dma); | |
853 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); | |
854 | evo_data(push, (y << 16) | x); | |
855 | } | |
856 | ||
a46232ee BS |
857 | if (update) { |
858 | evo_mthd(push, 0x0080, 1); | |
859 | evo_data(push, 0x00000000); | |
860 | } | |
de8268c5 | 861 | evo_kick(push, mast); |
438d99e3 BS |
862 | } |
863 | ||
c0cc92a1 | 864 | nv_crtc->fb.tile_flags = nvfb->r_dma; |
438d99e3 BS |
865 | return 0; |
866 | } | |
867 | ||
868 | static void | |
e225f446 | 869 | nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) |
438d99e3 | 870 | { |
e225f446 | 871 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 | 872 | u32 *push = evo_wait(mast, 16); |
438d99e3 | 873 | if (push) { |
e225f446 | 874 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
875 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
876 | evo_data(push, 0x85000000); | |
877 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
878 | } else | |
e225f446 | 879 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
880 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
881 | evo_data(push, 0x85000000); | |
882 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
883 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
884 | evo_data(push, NvEvoVRAM); | |
885 | } else { | |
438d99e3 BS |
886 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
887 | evo_data(push, 0x85000000); | |
888 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
889 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
37b034a6 | 890 | evo_data(push, NvEvoVRAM); |
de8268c5 BS |
891 | } |
892 | evo_kick(push, mast); | |
893 | } | |
894 | } | |
895 | ||
896 | static void | |
e225f446 | 897 | nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) |
de8268c5 | 898 | { |
e225f446 | 899 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
900 | u32 *push = evo_wait(mast, 16); |
901 | if (push) { | |
e225f446 | 902 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
903 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
904 | evo_data(push, 0x05000000); | |
905 | } else | |
e225f446 | 906 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
907 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
908 | evo_data(push, 0x05000000); | |
909 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
910 | evo_data(push, 0x00000000); | |
438d99e3 BS |
911 | } else { |
912 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); | |
913 | evo_data(push, 0x05000000); | |
914 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
915 | evo_data(push, 0x00000000); | |
916 | } | |
de8268c5 BS |
917 | evo_kick(push, mast); |
918 | } | |
919 | } | |
438d99e3 | 920 | |
de8268c5 | 921 | static void |
e225f446 | 922 | nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) |
de8268c5 | 923 | { |
e225f446 | 924 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
925 | |
926 | if (show) | |
e225f446 | 927 | nv50_crtc_cursor_show(nv_crtc); |
de8268c5 | 928 | else |
e225f446 | 929 | nv50_crtc_cursor_hide(nv_crtc); |
de8268c5 BS |
930 | |
931 | if (update) { | |
932 | u32 *push = evo_wait(mast, 2); | |
933 | if (push) { | |
438d99e3 BS |
934 | evo_mthd(push, 0x0080, 1); |
935 | evo_data(push, 0x00000000); | |
de8268c5 | 936 | evo_kick(push, mast); |
438d99e3 | 937 | } |
438d99e3 BS |
938 | } |
939 | } | |
940 | ||
941 | static void | |
e225f446 | 942 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
438d99e3 BS |
943 | { |
944 | } | |
945 | ||
946 | static void | |
e225f446 | 947 | nv50_crtc_prepare(struct drm_crtc *crtc) |
438d99e3 BS |
948 | { |
949 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 950 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
951 | u32 *push; |
952 | ||
e225f446 | 953 | nv50_display_flip_stop(crtc); |
3376ee37 | 954 | |
de8268c5 | 955 | push = evo_wait(mast, 2); |
438d99e3 | 956 | if (push) { |
e225f446 | 957 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
958 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
959 | evo_data(push, 0x00000000); | |
960 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
961 | evo_data(push, 0x40000000); | |
962 | } else | |
e225f446 | 963 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
964 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
965 | evo_data(push, 0x00000000); | |
966 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
967 | evo_data(push, 0x40000000); | |
968 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
969 | evo_data(push, 0x00000000); | |
970 | } else { | |
971 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
972 | evo_data(push, 0x00000000); | |
973 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); | |
974 | evo_data(push, 0x03000000); | |
975 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
976 | evo_data(push, 0x00000000); | |
977 | } | |
978 | ||
979 | evo_kick(push, mast); | |
438d99e3 BS |
980 | } |
981 | ||
e225f446 | 982 | nv50_crtc_cursor_show_hide(nv_crtc, false, false); |
438d99e3 BS |
983 | } |
984 | ||
985 | static void | |
e225f446 | 986 | nv50_crtc_commit(struct drm_crtc *crtc) |
438d99e3 BS |
987 | { |
988 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 989 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
990 | u32 *push; |
991 | ||
de8268c5 | 992 | push = evo_wait(mast, 32); |
438d99e3 | 993 | if (push) { |
e225f446 | 994 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
995 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
996 | evo_data(push, NvEvoVRAM_LP); | |
997 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); | |
998 | evo_data(push, 0xc0000000); | |
999 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1000 | } else | |
e225f446 | 1001 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
1002 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1003 | evo_data(push, nv_crtc->fb.tile_flags); | |
1004 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); | |
1005 | evo_data(push, 0xc0000000); | |
1006 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1007 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
1008 | evo_data(push, NvEvoVRAM); | |
1009 | } else { | |
1010 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
1011 | evo_data(push, nv_crtc->fb.tile_flags); | |
1012 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); | |
1013 | evo_data(push, 0x83000000); | |
1014 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1015 | evo_data(push, 0x00000000); | |
1016 | evo_data(push, 0x00000000); | |
1017 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
1018 | evo_data(push, NvEvoVRAM); | |
1019 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); | |
1020 | evo_data(push, 0xffffff00); | |
1021 | } | |
1022 | ||
1023 | evo_kick(push, mast); | |
438d99e3 BS |
1024 | } |
1025 | ||
e225f446 BS |
1026 | nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); |
1027 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | |
438d99e3 BS |
1028 | } |
1029 | ||
1030 | static bool | |
e225f446 | 1031 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
438d99e3 BS |
1032 | struct drm_display_mode *adjusted_mode) |
1033 | { | |
1034 | return true; | |
1035 | } | |
1036 | ||
1037 | static int | |
e225f446 | 1038 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
438d99e3 BS |
1039 | { |
1040 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb); | |
1041 | int ret; | |
1042 | ||
1043 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); | |
1044 | if (ret) | |
1045 | return ret; | |
1046 | ||
1047 | if (old_fb) { | |
1048 | nvfb = nouveau_framebuffer(old_fb); | |
1049 | nouveau_bo_unpin(nvfb->nvbo); | |
1050 | } | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
1055 | static int | |
e225f446 | 1056 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
438d99e3 BS |
1057 | struct drm_display_mode *mode, int x, int y, |
1058 | struct drm_framebuffer *old_fb) | |
1059 | { | |
e225f446 | 1060 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1061 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1062 | struct nouveau_connector *nv_connector; | |
2d1d898b BS |
1063 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
1064 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
1065 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; | |
1066 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; | |
1067 | u32 vblan2e = 0, vblan2s = 1; | |
3488c57b | 1068 | u32 *push; |
438d99e3 BS |
1069 | int ret; |
1070 | ||
2d1d898b BS |
1071 | hactive = mode->htotal; |
1072 | hsynce = mode->hsync_end - mode->hsync_start - 1; | |
1073 | hbackp = mode->htotal - mode->hsync_end; | |
1074 | hblanke = hsynce + hbackp; | |
1075 | hfrontp = mode->hsync_start - mode->hdisplay; | |
1076 | hblanks = mode->htotal - hfrontp - 1; | |
1077 | ||
1078 | vactive = mode->vtotal * vscan / ilace; | |
1079 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
1080 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
1081 | vblanke = vsynce + vbackp; | |
1082 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
1083 | vblanks = vactive - vfrontp - 1; | |
1084 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
1085 | vblan2e = vactive + vsynce + vbackp; | |
1086 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); | |
1087 | vactive = (vactive * 2) + 1; | |
2d1d898b BS |
1088 | } |
1089 | ||
e225f446 | 1090 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1091 | if (ret) |
1092 | return ret; | |
1093 | ||
de8268c5 | 1094 | push = evo_wait(mast, 64); |
438d99e3 | 1095 | if (push) { |
e225f446 | 1096 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
1097 | evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); |
1098 | evo_data(push, 0x00800000 | mode->clock); | |
1099 | evo_data(push, (ilace == 2) ? 2 : 0); | |
1100 | evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6); | |
1101 | evo_data(push, 0x00000000); | |
1102 | evo_data(push, (vactive << 16) | hactive); | |
1103 | evo_data(push, ( vsynce << 16) | hsynce); | |
1104 | evo_data(push, (vblanke << 16) | hblanke); | |
1105 | evo_data(push, (vblanks << 16) | hblanks); | |
1106 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1107 | evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1); | |
1108 | evo_data(push, 0x00000000); | |
1109 | evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); | |
1110 | evo_data(push, 0x00000311); | |
1111 | evo_data(push, 0x00000100); | |
1112 | } else { | |
1113 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); | |
1114 | evo_data(push, 0x00000000); | |
1115 | evo_data(push, (vactive << 16) | hactive); | |
1116 | evo_data(push, ( vsynce << 16) | hsynce); | |
1117 | evo_data(push, (vblanke << 16) | hblanke); | |
1118 | evo_data(push, (vblanks << 16) | hblanks); | |
1119 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1120 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); | |
1121 | evo_data(push, 0x00000000); /* ??? */ | |
1122 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); | |
1123 | evo_data(push, mode->clock * 1000); | |
1124 | evo_data(push, 0x00200000); /* ??? */ | |
1125 | evo_data(push, mode->clock * 1000); | |
1126 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); | |
1127 | evo_data(push, 0x00000311); | |
1128 | evo_data(push, 0x00000100); | |
1129 | } | |
1130 | ||
1131 | evo_kick(push, mast); | |
438d99e3 BS |
1132 | } |
1133 | ||
1134 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
e225f446 BS |
1135 | nv50_crtc_set_dither(nv_crtc, false); |
1136 | nv50_crtc_set_scale(nv_crtc, false); | |
1137 | nv50_crtc_set_color_vibrance(nv_crtc, false); | |
1138 | nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false); | |
438d99e3 BS |
1139 | return 0; |
1140 | } | |
1141 | ||
1142 | static int | |
e225f446 | 1143 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
438d99e3 BS |
1144 | struct drm_framebuffer *old_fb) |
1145 | { | |
77145f1c | 1146 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
438d99e3 BS |
1147 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1148 | int ret; | |
1149 | ||
84e2ad8b | 1150 | if (!crtc->fb) { |
77145f1c | 1151 | NV_DEBUG(drm, "No FB bound\n"); |
84e2ad8b BS |
1152 | return 0; |
1153 | } | |
1154 | ||
e225f446 | 1155 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1156 | if (ret) |
1157 | return ret; | |
1158 | ||
e225f446 BS |
1159 | nv50_display_flip_stop(crtc); |
1160 | nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true); | |
1161 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | |
438d99e3 BS |
1162 | return 0; |
1163 | } | |
1164 | ||
1165 | static int | |
e225f446 | 1166 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
438d99e3 BS |
1167 | struct drm_framebuffer *fb, int x, int y, |
1168 | enum mode_set_atomic state) | |
1169 | { | |
1170 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1171 | nv50_display_flip_stop(crtc); |
1172 | nv50_crtc_set_image(nv_crtc, fb, x, y, true); | |
438d99e3 BS |
1173 | return 0; |
1174 | } | |
1175 | ||
1176 | static void | |
e225f446 | 1177 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
438d99e3 | 1178 | { |
e225f446 | 1179 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
438d99e3 BS |
1180 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1181 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
1182 | int i; | |
1183 | ||
1184 | for (i = 0; i < 256; i++) { | |
de8268c5 BS |
1185 | u16 r = nv_crtc->lut.r[i] >> 2; |
1186 | u16 g = nv_crtc->lut.g[i] >> 2; | |
1187 | u16 b = nv_crtc->lut.b[i] >> 2; | |
1188 | ||
1189 | if (nv_mclass(disp->core) < NVD0_DISP_CLASS) { | |
1190 | writew(r + 0x0000, lut + (i * 0x08) + 0); | |
1191 | writew(g + 0x0000, lut + (i * 0x08) + 2); | |
1192 | writew(b + 0x0000, lut + (i * 0x08) + 4); | |
1193 | } else { | |
1194 | writew(r + 0x6000, lut + (i * 0x20) + 0); | |
1195 | writew(g + 0x6000, lut + (i * 0x20) + 2); | |
1196 | writew(b + 0x6000, lut + (i * 0x20) + 4); | |
1197 | } | |
438d99e3 BS |
1198 | } |
1199 | } | |
1200 | ||
1201 | static int | |
e225f446 | 1202 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
438d99e3 BS |
1203 | uint32_t handle, uint32_t width, uint32_t height) |
1204 | { | |
1205 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
1206 | struct drm_device *dev = crtc->dev; | |
1207 | struct drm_gem_object *gem; | |
1208 | struct nouveau_bo *nvbo; | |
1209 | bool visible = (handle != 0); | |
1210 | int i, ret = 0; | |
1211 | ||
1212 | if (visible) { | |
1213 | if (width != 64 || height != 64) | |
1214 | return -EINVAL; | |
1215 | ||
1216 | gem = drm_gem_object_lookup(dev, file_priv, handle); | |
1217 | if (unlikely(!gem)) | |
1218 | return -ENOENT; | |
1219 | nvbo = nouveau_gem_object(gem); | |
1220 | ||
1221 | ret = nouveau_bo_map(nvbo); | |
1222 | if (ret == 0) { | |
1223 | for (i = 0; i < 64 * 64; i++) { | |
1224 | u32 v = nouveau_bo_rd32(nvbo, i); | |
1225 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v); | |
1226 | } | |
1227 | nouveau_bo_unmap(nvbo); | |
1228 | } | |
1229 | ||
1230 | drm_gem_object_unreference_unlocked(gem); | |
1231 | } | |
1232 | ||
1233 | if (visible != nv_crtc->cursor.visible) { | |
e225f446 | 1234 | nv50_crtc_cursor_show_hide(nv_crtc, visible, true); |
438d99e3 BS |
1235 | nv_crtc->cursor.visible = visible; |
1236 | } | |
1237 | ||
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | static int | |
e225f446 | 1242 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
438d99e3 | 1243 | { |
e225f446 BS |
1244 | struct nv50_curs *curs = nv50_curs(crtc); |
1245 | struct nv50_chan *chan = nv50_chan(curs); | |
b5a794b0 BS |
1246 | nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff)); |
1247 | nv_wo32(chan->user, 0x0080, 0x00000000); | |
438d99e3 BS |
1248 | return 0; |
1249 | } | |
1250 | ||
1251 | static void | |
e225f446 | 1252 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
438d99e3 BS |
1253 | uint32_t start, uint32_t size) |
1254 | { | |
1255 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
1256 | u32 end = max(start + size, (u32)256); | |
1257 | u32 i; | |
1258 | ||
1259 | for (i = start; i < end; i++) { | |
1260 | nv_crtc->lut.r[i] = r[i]; | |
1261 | nv_crtc->lut.g[i] = g[i]; | |
1262 | nv_crtc->lut.b[i] = b[i]; | |
1263 | } | |
1264 | ||
e225f446 | 1265 | nv50_crtc_lut_load(crtc); |
438d99e3 BS |
1266 | } |
1267 | ||
1268 | static void | |
e225f446 | 1269 | nv50_crtc_destroy(struct drm_crtc *crtc) |
438d99e3 BS |
1270 | { |
1271 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1272 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
1273 | struct nv50_head *head = nv50_head(crtc); | |
1274 | nv50_dmac_destroy(disp->core, &head->ovly.base); | |
1275 | nv50_pioc_destroy(disp->core, &head->oimm.base); | |
1276 | nv50_dmac_destroy(disp->core, &head->sync.base); | |
1277 | nv50_pioc_destroy(disp->core, &head->curs.base); | |
438d99e3 | 1278 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
04c8c210 MS |
1279 | if (nv_crtc->cursor.nvbo) |
1280 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
438d99e3 BS |
1281 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
1282 | nouveau_bo_unmap(nv_crtc->lut.nvbo); | |
04c8c210 MS |
1283 | if (nv_crtc->lut.nvbo) |
1284 | nouveau_bo_unpin(nv_crtc->lut.nvbo); | |
438d99e3 BS |
1285 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
1286 | drm_crtc_cleanup(crtc); | |
1287 | kfree(crtc); | |
1288 | } | |
1289 | ||
e225f446 BS |
1290 | static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { |
1291 | .dpms = nv50_crtc_dpms, | |
1292 | .prepare = nv50_crtc_prepare, | |
1293 | .commit = nv50_crtc_commit, | |
1294 | .mode_fixup = nv50_crtc_mode_fixup, | |
1295 | .mode_set = nv50_crtc_mode_set, | |
1296 | .mode_set_base = nv50_crtc_mode_set_base, | |
1297 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, | |
1298 | .load_lut = nv50_crtc_lut_load, | |
438d99e3 BS |
1299 | }; |
1300 | ||
e225f446 BS |
1301 | static const struct drm_crtc_funcs nv50_crtc_func = { |
1302 | .cursor_set = nv50_crtc_cursor_set, | |
1303 | .cursor_move = nv50_crtc_cursor_move, | |
1304 | .gamma_set = nv50_crtc_gamma_set, | |
438d99e3 | 1305 | .set_config = drm_crtc_helper_set_config, |
e225f446 | 1306 | .destroy = nv50_crtc_destroy, |
3376ee37 | 1307 | .page_flip = nouveau_crtc_page_flip, |
438d99e3 BS |
1308 | }; |
1309 | ||
c20ab3e1 | 1310 | static void |
e225f446 | 1311 | nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) |
c20ab3e1 BS |
1312 | { |
1313 | } | |
1314 | ||
1315 | static void | |
e225f446 | 1316 | nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) |
c20ab3e1 BS |
1317 | { |
1318 | } | |
1319 | ||
438d99e3 | 1320 | static int |
e225f446 | 1321 | nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index) |
438d99e3 | 1322 | { |
e225f446 BS |
1323 | struct nv50_disp *disp = nv50_disp(dev); |
1324 | struct nv50_head *head; | |
438d99e3 BS |
1325 | struct drm_crtc *crtc; |
1326 | int ret, i; | |
1327 | ||
dd0e3d53 BS |
1328 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
1329 | if (!head) | |
438d99e3 BS |
1330 | return -ENOMEM; |
1331 | ||
dd0e3d53 | 1332 | head->base.index = index; |
e225f446 BS |
1333 | head->base.set_dither = nv50_crtc_set_dither; |
1334 | head->base.set_scale = nv50_crtc_set_scale; | |
1335 | head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; | |
f9887d09 BS |
1336 | head->base.color_vibrance = 50; |
1337 | head->base.vibrant_hue = 0; | |
e225f446 BS |
1338 | head->base.cursor.set_offset = nv50_cursor_set_offset; |
1339 | head->base.cursor.set_pos = nv50_cursor_set_pos; | |
438d99e3 | 1340 | for (i = 0; i < 256; i++) { |
dd0e3d53 BS |
1341 | head->base.lut.r[i] = i << 8; |
1342 | head->base.lut.g[i] = i << 8; | |
1343 | head->base.lut.b[i] = i << 8; | |
438d99e3 BS |
1344 | } |
1345 | ||
dd0e3d53 | 1346 | crtc = &head->base.base; |
e225f446 BS |
1347 | drm_crtc_init(dev, crtc, &nv50_crtc_func); |
1348 | drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); | |
438d99e3 BS |
1349 | drm_mode_crtc_set_gamma_size(crtc, 256); |
1350 | ||
b5a794b0 BS |
1351 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
1352 | 0, 0x0000, NULL, &head->base.lut.nvbo); | |
1353 | if (!ret) { | |
1354 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM); | |
04c8c210 | 1355 | if (!ret) { |
b5a794b0 | 1356 | ret = nouveau_bo_map(head->base.lut.nvbo); |
04c8c210 MS |
1357 | if (ret) |
1358 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1359 | } | |
b5a794b0 BS |
1360 | if (ret) |
1361 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); | |
1362 | } | |
1363 | ||
1364 | if (ret) | |
1365 | goto out; | |
1366 | ||
e225f446 | 1367 | nv50_crtc_lut_load(crtc); |
b5a794b0 BS |
1368 | |
1369 | /* allocate cursor resources */ | |
e225f446 | 1370 | ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index, |
b5a794b0 BS |
1371 | &(struct nv50_display_curs_class) { |
1372 | .head = index, | |
1373 | }, sizeof(struct nv50_display_curs_class), | |
1374 | &head->curs.base); | |
1375 | if (ret) | |
1376 | goto out; | |
1377 | ||
438d99e3 | 1378 | ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM, |
dd0e3d53 | 1379 | 0, 0x0000, NULL, &head->base.cursor.nvbo); |
438d99e3 | 1380 | if (!ret) { |
dd0e3d53 | 1381 | ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM); |
04c8c210 | 1382 | if (!ret) { |
dd0e3d53 | 1383 | ret = nouveau_bo_map(head->base.cursor.nvbo); |
04c8c210 MS |
1384 | if (ret) |
1385 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1386 | } | |
438d99e3 | 1387 | if (ret) |
dd0e3d53 | 1388 | nouveau_bo_ref(NULL, &head->base.cursor.nvbo); |
438d99e3 BS |
1389 | } |
1390 | ||
1391 | if (ret) | |
1392 | goto out; | |
1393 | ||
b5a794b0 | 1394 | /* allocate page flip / sync resources */ |
e225f446 | 1395 | ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index, |
b5a794b0 BS |
1396 | &(struct nv50_display_sync_class) { |
1397 | .pushbuf = EVO_PUSH_HANDLE(SYNC, index), | |
1398 | .head = index, | |
1399 | }, sizeof(struct nv50_display_sync_class), | |
1400 | disp->sync->bo.offset, &head->sync.base); | |
1401 | if (ret) | |
1402 | goto out; | |
1403 | ||
9f9bdaaf BS |
1404 | head->sync.addr = EVO_FLIP_SEM0(index); |
1405 | head->sync.data = 0x00000000; | |
438d99e3 | 1406 | |
b5a794b0 | 1407 | /* allocate overlay resources */ |
e225f446 | 1408 | ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index, |
b5a794b0 BS |
1409 | &(struct nv50_display_oimm_class) { |
1410 | .head = index, | |
1411 | }, sizeof(struct nv50_display_oimm_class), | |
1412 | &head->oimm.base); | |
438d99e3 BS |
1413 | if (ret) |
1414 | goto out; | |
1415 | ||
e225f446 | 1416 | ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index, |
b5a794b0 BS |
1417 | &(struct nv50_display_ovly_class) { |
1418 | .pushbuf = EVO_PUSH_HANDLE(OVLY, index), | |
1419 | .head = index, | |
1420 | }, sizeof(struct nv50_display_ovly_class), | |
1421 | disp->sync->bo.offset, &head->ovly.base); | |
1422 | if (ret) | |
1423 | goto out; | |
438d99e3 BS |
1424 | |
1425 | out: | |
1426 | if (ret) | |
e225f446 | 1427 | nv50_crtc_destroy(crtc); |
438d99e3 BS |
1428 | return ret; |
1429 | } | |
1430 | ||
26f6d88b BS |
1431 | /****************************************************************************** |
1432 | * DAC | |
1433 | *****************************************************************************/ | |
8eaa9669 | 1434 | static void |
e225f446 | 1435 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
8eaa9669 BS |
1436 | { |
1437 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1438 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
8eaa9669 BS |
1439 | int or = nv_encoder->or; |
1440 | u32 dpms_ctrl; | |
1441 | ||
35b21d39 | 1442 | dpms_ctrl = 0x00000000; |
8eaa9669 BS |
1443 | if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF) |
1444 | dpms_ctrl |= 0x00000001; | |
1445 | if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF) | |
1446 | dpms_ctrl |= 0x00000004; | |
1447 | ||
35b21d39 | 1448 | nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl); |
8eaa9669 BS |
1449 | } |
1450 | ||
1451 | static bool | |
e225f446 | 1452 | nv50_dac_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 1453 | const struct drm_display_mode *mode, |
8eaa9669 BS |
1454 | struct drm_display_mode *adjusted_mode) |
1455 | { | |
1456 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1457 | struct nouveau_connector *nv_connector; | |
1458 | ||
1459 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1460 | if (nv_connector && nv_connector->native_mode) { | |
1461 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1462 | int id = adjusted_mode->base.id; | |
1463 | *adjusted_mode = *nv_connector->native_mode; | |
1464 | adjusted_mode->base.id = id; | |
1465 | } | |
1466 | } | |
1467 | ||
1468 | return true; | |
1469 | } | |
1470 | ||
8eaa9669 | 1471 | static void |
e225f446 | 1472 | nv50_dac_commit(struct drm_encoder *encoder) |
8eaa9669 BS |
1473 | { |
1474 | } | |
1475 | ||
1476 | static void | |
e225f446 | 1477 | nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
8eaa9669 BS |
1478 | struct drm_display_mode *adjusted_mode) |
1479 | { | |
e225f446 | 1480 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
8eaa9669 BS |
1481 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1482 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
97b19b5c | 1483 | u32 *push; |
8eaa9669 | 1484 | |
e225f446 | 1485 | nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
8eaa9669 | 1486 | |
97b19b5c | 1487 | push = evo_wait(mast, 8); |
8eaa9669 | 1488 | if (push) { |
e225f446 | 1489 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
97b19b5c BS |
1490 | u32 syncs = 0x00000000; |
1491 | ||
1492 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1493 | syncs |= 0x00000001; | |
1494 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1495 | syncs |= 0x00000002; | |
1496 | ||
1497 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); | |
1498 | evo_data(push, 1 << nv_crtc->index); | |
1499 | evo_data(push, syncs); | |
1500 | } else { | |
1501 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1502 | u32 syncs = 0x00000001; | |
1503 | ||
1504 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1505 | syncs |= 0x00000008; | |
1506 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1507 | syncs |= 0x00000010; | |
1508 | ||
1509 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1510 | magic |= 0x00000001; | |
1511 | ||
1512 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
1513 | evo_data(push, syncs); | |
1514 | evo_data(push, magic); | |
1515 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); | |
1516 | evo_data(push, 1 << nv_crtc->index); | |
1517 | } | |
1518 | ||
1519 | evo_kick(push, mast); | |
8eaa9669 BS |
1520 | } |
1521 | ||
1522 | nv_encoder->crtc = encoder->crtc; | |
1523 | } | |
1524 | ||
1525 | static void | |
e225f446 | 1526 | nv50_dac_disconnect(struct drm_encoder *encoder) |
8eaa9669 BS |
1527 | { |
1528 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1529 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
97b19b5c | 1530 | const int or = nv_encoder->or; |
8eaa9669 BS |
1531 | u32 *push; |
1532 | ||
1533 | if (nv_encoder->crtc) { | |
e225f446 | 1534 | nv50_crtc_prepare(nv_encoder->crtc); |
8eaa9669 | 1535 | |
97b19b5c | 1536 | push = evo_wait(mast, 4); |
8eaa9669 | 1537 | if (push) { |
e225f446 | 1538 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
97b19b5c BS |
1539 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
1540 | evo_data(push, 0x00000000); | |
1541 | } else { | |
1542 | evo_mthd(push, 0x0180 + (or * 0x020), 1); | |
1543 | evo_data(push, 0x00000000); | |
1544 | } | |
97b19b5c | 1545 | evo_kick(push, mast); |
8eaa9669 | 1546 | } |
8eaa9669 | 1547 | } |
97b19b5c BS |
1548 | |
1549 | nv_encoder->crtc = NULL; | |
8eaa9669 BS |
1550 | } |
1551 | ||
b6d8e7ec | 1552 | static enum drm_connector_status |
e225f446 | 1553 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
b6d8e7ec | 1554 | { |
e225f446 | 1555 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
35b21d39 | 1556 | int ret, or = nouveau_encoder(encoder)->or; |
7ebb38b5 | 1557 | u32 load = 0; |
b681993f | 1558 | |
35b21d39 BS |
1559 | ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load)); |
1560 | if (ret || load != 7) | |
1561 | return connector_status_disconnected; | |
b681993f | 1562 | |
35b21d39 | 1563 | return connector_status_connected; |
b6d8e7ec BS |
1564 | } |
1565 | ||
8eaa9669 | 1566 | static void |
e225f446 | 1567 | nv50_dac_destroy(struct drm_encoder *encoder) |
8eaa9669 BS |
1568 | { |
1569 | drm_encoder_cleanup(encoder); | |
1570 | kfree(encoder); | |
1571 | } | |
1572 | ||
e225f446 BS |
1573 | static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { |
1574 | .dpms = nv50_dac_dpms, | |
1575 | .mode_fixup = nv50_dac_mode_fixup, | |
1576 | .prepare = nv50_dac_disconnect, | |
1577 | .commit = nv50_dac_commit, | |
1578 | .mode_set = nv50_dac_mode_set, | |
1579 | .disable = nv50_dac_disconnect, | |
1580 | .get_crtc = nv50_display_crtc_get, | |
1581 | .detect = nv50_dac_detect | |
8eaa9669 BS |
1582 | }; |
1583 | ||
e225f446 BS |
1584 | static const struct drm_encoder_funcs nv50_dac_func = { |
1585 | .destroy = nv50_dac_destroy, | |
8eaa9669 BS |
1586 | }; |
1587 | ||
1588 | static int | |
e225f446 | 1589 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
8eaa9669 | 1590 | { |
5ed50209 BS |
1591 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1592 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); | |
8eaa9669 BS |
1593 | struct nouveau_encoder *nv_encoder; |
1594 | struct drm_encoder *encoder; | |
5ed50209 | 1595 | int type = DRM_MODE_ENCODER_DAC; |
8eaa9669 BS |
1596 | |
1597 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1598 | if (!nv_encoder) | |
1599 | return -ENOMEM; | |
1600 | nv_encoder->dcb = dcbe; | |
1601 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 1602 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
8eaa9669 BS |
1603 | |
1604 | encoder = to_drm_encoder(nv_encoder); | |
1605 | encoder->possible_crtcs = dcbe->heads; | |
1606 | encoder->possible_clones = 0; | |
5ed50209 | 1607 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type); |
e225f446 | 1608 | drm_encoder_helper_add(encoder, &nv50_dac_hfunc); |
8eaa9669 BS |
1609 | |
1610 | drm_mode_connector_attach_encoder(connector, encoder); | |
1611 | return 0; | |
1612 | } | |
26f6d88b | 1613 | |
78951d22 BS |
1614 | /****************************************************************************** |
1615 | * Audio | |
1616 | *****************************************************************************/ | |
1617 | static void | |
e225f446 | 1618 | nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 BS |
1619 | { |
1620 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1621 | struct nouveau_connector *nv_connector; | |
e225f446 | 1622 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
78951d22 BS |
1623 | |
1624 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1625 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
1626 | return; | |
1627 | ||
78951d22 | 1628 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
78951d22 | 1629 | |
0a9e2b95 BS |
1630 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, |
1631 | nv_connector->base.eld, | |
1632 | nv_connector->base.eld[2] * 4); | |
78951d22 BS |
1633 | } |
1634 | ||
1635 | static void | |
e225f446 | 1636 | nv50_audio_disconnect(struct drm_encoder *encoder) |
78951d22 BS |
1637 | { |
1638 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1639 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
78951d22 | 1640 | |
0a9e2b95 | 1641 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0); |
78951d22 BS |
1642 | } |
1643 | ||
1644 | /****************************************************************************** | |
1645 | * HDMI | |
1646 | *****************************************************************************/ | |
1647 | static void | |
e225f446 | 1648 | nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 | 1649 | { |
64d9cc04 BS |
1650 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1651 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
1652 | struct nouveau_connector *nv_connector; | |
e225f446 | 1653 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1c30cd09 | 1654 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
64d9cc04 BS |
1655 | u32 rekey = 56; /* binary driver, and tegra constant */ |
1656 | u32 max_ac_packet; | |
1657 | ||
1658 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1659 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
1660 | return; | |
1661 | ||
1662 | max_ac_packet = mode->htotal - mode->hdisplay; | |
1663 | max_ac_packet -= rekey; | |
1664 | max_ac_packet -= 18; /* constant from tegra */ | |
1665 | max_ac_packet /= 32; | |
1666 | ||
1c30cd09 BS |
1667 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, |
1668 | NV84_DISP_SOR_HDMI_PWR_STATE_ON | | |
1669 | (max_ac_packet << 16) | rekey); | |
091e40cd | 1670 | |
e225f446 | 1671 | nv50_audio_mode_set(encoder, mode); |
78951d22 BS |
1672 | } |
1673 | ||
1674 | static void | |
e225f446 | 1675 | nv50_hdmi_disconnect(struct drm_encoder *encoder) |
78951d22 | 1676 | { |
64d9cc04 BS |
1677 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1678 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
e225f446 | 1679 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1c30cd09 | 1680 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
64d9cc04 | 1681 | |
e225f446 | 1682 | nv50_audio_disconnect(encoder); |
64d9cc04 | 1683 | |
1c30cd09 | 1684 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000); |
78951d22 BS |
1685 | } |
1686 | ||
26f6d88b BS |
1687 | /****************************************************************************** |
1688 | * SOR | |
1689 | *****************************************************************************/ | |
83fc083c | 1690 | static void |
e225f446 | 1691 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
83fc083c BS |
1692 | { |
1693 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1694 | struct drm_device *dev = encoder->dev; | |
e225f446 | 1695 | struct nv50_disp *disp = nv50_disp(dev); |
83fc083c BS |
1696 | struct drm_encoder *partner; |
1697 | int or = nv_encoder->or; | |
83fc083c BS |
1698 | |
1699 | nv_encoder->last_dpms = mode; | |
1700 | ||
1701 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { | |
1702 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); | |
1703 | ||
1704 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) | |
1705 | continue; | |
1706 | ||
1707 | if (nv_partner != nv_encoder && | |
26cfa813 | 1708 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
83fc083c BS |
1709 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
1710 | return; | |
1711 | break; | |
1712 | } | |
1713 | } | |
1714 | ||
74b66850 | 1715 | nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON)); |
83fc083c BS |
1716 | } |
1717 | ||
1718 | static bool | |
e225f446 | 1719 | nv50_sor_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 1720 | const struct drm_display_mode *mode, |
83fc083c BS |
1721 | struct drm_display_mode *adjusted_mode) |
1722 | { | |
1723 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1724 | struct nouveau_connector *nv_connector; | |
1725 | ||
1726 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1727 | if (nv_connector && nv_connector->native_mode) { | |
1728 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1729 | int id = adjusted_mode->base.id; | |
1730 | *adjusted_mode = *nv_connector->native_mode; | |
1731 | adjusted_mode->base.id = id; | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | return true; | |
1736 | } | |
1737 | ||
4cbb0f8d | 1738 | static void |
e225f446 | 1739 | nv50_sor_disconnect(struct drm_encoder *encoder) |
4cbb0f8d BS |
1740 | { |
1741 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1742 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
419e8dc0 | 1743 | const int or = nv_encoder->or; |
4cbb0f8d BS |
1744 | u32 *push; |
1745 | ||
1746 | if (nv_encoder->crtc) { | |
e225f446 | 1747 | nv50_crtc_prepare(nv_encoder->crtc); |
4cbb0f8d | 1748 | |
419e8dc0 | 1749 | push = evo_wait(mast, 4); |
4cbb0f8d | 1750 | if (push) { |
e225f446 | 1751 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
419e8dc0 BS |
1752 | evo_mthd(push, 0x0600 + (or * 0x40), 1); |
1753 | evo_data(push, 0x00000000); | |
1754 | } else { | |
1755 | evo_mthd(push, 0x0200 + (or * 0x20), 1); | |
1756 | evo_data(push, 0x00000000); | |
1757 | } | |
419e8dc0 | 1758 | evo_kick(push, mast); |
4cbb0f8d BS |
1759 | } |
1760 | ||
e225f446 | 1761 | nv50_hdmi_disconnect(encoder); |
4cbb0f8d | 1762 | } |
419e8dc0 BS |
1763 | |
1764 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
1765 | nv_encoder->crtc = NULL; | |
4cbb0f8d BS |
1766 | } |
1767 | ||
83fc083c | 1768 | static void |
e225f446 | 1769 | nv50_sor_commit(struct drm_encoder *encoder) |
83fc083c BS |
1770 | { |
1771 | } | |
1772 | ||
1773 | static void | |
e225f446 | 1774 | nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
3b6d83d1 | 1775 | struct drm_display_mode *mode) |
83fc083c | 1776 | { |
e225f446 BS |
1777 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1778 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
78951d22 | 1779 | struct drm_device *dev = encoder->dev; |
77145f1c | 1780 | struct nouveau_drm *drm = nouveau_drm(dev); |
83fc083c BS |
1781 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1782 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
3b6d83d1 | 1783 | struct nouveau_connector *nv_connector; |
77145f1c | 1784 | struct nvbios *bios = &drm->vbios; |
419e8dc0 BS |
1785 | u32 *push, lvds = 0; |
1786 | u8 owner = 1 << nv_crtc->index; | |
1787 | u8 proto = 0xf; | |
1788 | u8 depth = 0x0; | |
83fc083c | 1789 | |
3b6d83d1 BS |
1790 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1791 | switch (nv_encoder->dcb->type) { | |
cb75d97e | 1792 | case DCB_OUTPUT_TMDS: |
3b6d83d1 BS |
1793 | if (nv_encoder->dcb->sorconf.link & 1) { |
1794 | if (mode->clock < 165000) | |
419e8dc0 | 1795 | proto = 0x1; |
3b6d83d1 | 1796 | else |
419e8dc0 | 1797 | proto = 0x5; |
3b6d83d1 | 1798 | } else { |
419e8dc0 | 1799 | proto = 0x2; |
3b6d83d1 BS |
1800 | } |
1801 | ||
e225f446 | 1802 | nv50_hdmi_mode_set(encoder, mode); |
3b6d83d1 | 1803 | break; |
cb75d97e | 1804 | case DCB_OUTPUT_LVDS: |
419e8dc0 BS |
1805 | proto = 0x0; |
1806 | ||
3b6d83d1 BS |
1807 | if (bios->fp_no_ddc) { |
1808 | if (bios->fp.dual_link) | |
419e8dc0 | 1809 | lvds |= 0x0100; |
3b6d83d1 | 1810 | if (bios->fp.if_is_24bit) |
419e8dc0 | 1811 | lvds |= 0x0200; |
3b6d83d1 | 1812 | } else { |
befb51e9 | 1813 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 | 1814 | if (((u8 *)nv_connector->edid)[121] == 2) |
419e8dc0 | 1815 | lvds |= 0x0100; |
3b6d83d1 BS |
1816 | } else |
1817 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
419e8dc0 | 1818 | lvds |= 0x0100; |
3b6d83d1 | 1819 | } |
83fc083c | 1820 | |
419e8dc0 | 1821 | if (lvds & 0x0100) { |
3b6d83d1 | 1822 | if (bios->fp.strapless_is_24bit & 2) |
419e8dc0 | 1823 | lvds |= 0x0200; |
3b6d83d1 BS |
1824 | } else { |
1825 | if (bios->fp.strapless_is_24bit & 1) | |
419e8dc0 | 1826 | lvds |= 0x0200; |
3b6d83d1 BS |
1827 | } |
1828 | ||
1829 | if (nv_connector->base.display_info.bpc == 8) | |
419e8dc0 | 1830 | lvds |= 0x0200; |
3b6d83d1 | 1831 | } |
4a230fa6 | 1832 | |
419e8dc0 | 1833 | nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds); |
3b6d83d1 | 1834 | break; |
cb75d97e | 1835 | case DCB_OUTPUT_DP: |
3488c57b | 1836 | if (nv_connector->base.display_info.bpc == 6) { |
6e83fda2 | 1837 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
419e8dc0 | 1838 | depth = 0x2; |
bf2c886a BS |
1839 | } else |
1840 | if (nv_connector->base.display_info.bpc == 8) { | |
6e83fda2 | 1841 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
419e8dc0 | 1842 | depth = 0x5; |
bf2c886a BS |
1843 | } else { |
1844 | nv_encoder->dp.datarate = mode->clock * 30 / 8; | |
1845 | depth = 0x6; | |
3488c57b | 1846 | } |
6e83fda2 BS |
1847 | |
1848 | if (nv_encoder->dcb->sorconf.link & 1) | |
419e8dc0 | 1849 | proto = 0x8; |
6e83fda2 | 1850 | else |
419e8dc0 | 1851 | proto = 0x9; |
6e83fda2 | 1852 | break; |
3b6d83d1 BS |
1853 | default: |
1854 | BUG_ON(1); | |
1855 | break; | |
1856 | } | |
ff8ff503 | 1857 | |
e225f446 | 1858 | nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); |
83fc083c | 1859 | |
e225f446 | 1860 | push = evo_wait(nv50_mast(dev), 8); |
83fc083c | 1861 | if (push) { |
e225f446 | 1862 | if (nv50_vers(mast) < NVD0_DISP_CLASS) { |
e2de1794 BS |
1863 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
1864 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1865 | ctrl |= 0x00001000; | |
1866 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1867 | ctrl |= 0x00002000; | |
419e8dc0 | 1868 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1); |
e2de1794 | 1869 | evo_data(push, ctrl); |
419e8dc0 BS |
1870 | } else { |
1871 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1872 | u32 syncs = 0x00000001; | |
1873 | ||
1874 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1875 | syncs |= 0x00000008; | |
1876 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1877 | syncs |= 0x00000010; | |
1878 | ||
1879 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1880 | magic |= 0x00000001; | |
1881 | ||
1882 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
1883 | evo_data(push, syncs | (depth << 6)); | |
1884 | evo_data(push, magic); | |
1885 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1); | |
1886 | evo_data(push, owner | (proto << 8)); | |
1887 | } | |
1888 | ||
1889 | evo_kick(push, mast); | |
83fc083c BS |
1890 | } |
1891 | ||
1892 | nv_encoder->crtc = encoder->crtc; | |
1893 | } | |
1894 | ||
83fc083c | 1895 | static void |
e225f446 | 1896 | nv50_sor_destroy(struct drm_encoder *encoder) |
83fc083c BS |
1897 | { |
1898 | drm_encoder_cleanup(encoder); | |
1899 | kfree(encoder); | |
1900 | } | |
1901 | ||
e225f446 BS |
1902 | static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { |
1903 | .dpms = nv50_sor_dpms, | |
1904 | .mode_fixup = nv50_sor_mode_fixup, | |
5a885f0b | 1905 | .prepare = nv50_sor_disconnect, |
e225f446 BS |
1906 | .commit = nv50_sor_commit, |
1907 | .mode_set = nv50_sor_mode_set, | |
1908 | .disable = nv50_sor_disconnect, | |
1909 | .get_crtc = nv50_display_crtc_get, | |
83fc083c BS |
1910 | }; |
1911 | ||
e225f446 BS |
1912 | static const struct drm_encoder_funcs nv50_sor_func = { |
1913 | .destroy = nv50_sor_destroy, | |
83fc083c BS |
1914 | }; |
1915 | ||
1916 | static int | |
e225f446 | 1917 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
83fc083c | 1918 | { |
5ed50209 BS |
1919 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1920 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); | |
83fc083c BS |
1921 | struct nouveau_encoder *nv_encoder; |
1922 | struct drm_encoder *encoder; | |
5ed50209 BS |
1923 | int type; |
1924 | ||
1925 | switch (dcbe->type) { | |
1926 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; | |
1927 | case DCB_OUTPUT_TMDS: | |
1928 | case DCB_OUTPUT_DP: | |
1929 | default: | |
1930 | type = DRM_MODE_ENCODER_TMDS; | |
1931 | break; | |
1932 | } | |
83fc083c BS |
1933 | |
1934 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1935 | if (!nv_encoder) | |
1936 | return -ENOMEM; | |
1937 | nv_encoder->dcb = dcbe; | |
1938 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 1939 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
83fc083c BS |
1940 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
1941 | ||
1942 | encoder = to_drm_encoder(nv_encoder); | |
1943 | encoder->possible_crtcs = dcbe->heads; | |
1944 | encoder->possible_clones = 0; | |
5ed50209 | 1945 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type); |
e225f446 | 1946 | drm_encoder_helper_add(encoder, &nv50_sor_hfunc); |
83fc083c BS |
1947 | |
1948 | drm_mode_connector_attach_encoder(connector, encoder); | |
1949 | return 0; | |
1950 | } | |
26f6d88b | 1951 | |
eb6313ad BS |
1952 | /****************************************************************************** |
1953 | * PIOR | |
1954 | *****************************************************************************/ | |
1955 | ||
1956 | static void | |
1957 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) | |
1958 | { | |
1959 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1960 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
1961 | u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or; | |
1962 | u32 ctrl = (mode == DRM_MODE_DPMS_ON); | |
1963 | nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl); | |
1964 | } | |
1965 | ||
1966 | static bool | |
1967 | nv50_pior_mode_fixup(struct drm_encoder *encoder, | |
1968 | const struct drm_display_mode *mode, | |
1969 | struct drm_display_mode *adjusted_mode) | |
1970 | { | |
1971 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1972 | struct nouveau_connector *nv_connector; | |
1973 | ||
1974 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1975 | if (nv_connector && nv_connector->native_mode) { | |
1976 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1977 | int id = adjusted_mode->base.id; | |
1978 | *adjusted_mode = *nv_connector->native_mode; | |
1979 | adjusted_mode->base.id = id; | |
1980 | } | |
1981 | } | |
1982 | ||
1983 | adjusted_mode->clock *= 2; | |
1984 | return true; | |
1985 | } | |
1986 | ||
1987 | static void | |
1988 | nv50_pior_commit(struct drm_encoder *encoder) | |
1989 | { | |
1990 | } | |
1991 | ||
1992 | static void | |
1993 | nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
1994 | struct drm_display_mode *adjusted_mode) | |
1995 | { | |
1996 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
1997 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1998 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
1999 | struct nouveau_connector *nv_connector; | |
2000 | u8 owner = 1 << nv_crtc->index; | |
2001 | u8 proto, depth; | |
2002 | u32 *push; | |
2003 | ||
2004 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2005 | switch (nv_connector->base.display_info.bpc) { | |
2006 | case 10: depth = 0x6; break; | |
2007 | case 8: depth = 0x5; break; | |
2008 | case 6: depth = 0x2; break; | |
2009 | default: depth = 0x0; break; | |
2010 | } | |
2011 | ||
2012 | switch (nv_encoder->dcb->type) { | |
2013 | case DCB_OUTPUT_TMDS: | |
2014 | case DCB_OUTPUT_DP: | |
2015 | proto = 0x0; | |
2016 | break; | |
2017 | default: | |
2018 | BUG_ON(1); | |
2019 | break; | |
2020 | } | |
2021 | ||
2022 | nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); | |
2023 | ||
2024 | push = evo_wait(mast, 8); | |
2025 | if (push) { | |
2026 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { | |
2027 | u32 ctrl = (depth << 16) | (proto << 8) | owner; | |
2028 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2029 | ctrl |= 0x00001000; | |
2030 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2031 | ctrl |= 0x00002000; | |
2032 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); | |
2033 | evo_data(push, ctrl); | |
2034 | } | |
2035 | ||
2036 | evo_kick(push, mast); | |
2037 | } | |
2038 | ||
2039 | nv_encoder->crtc = encoder->crtc; | |
2040 | } | |
2041 | ||
2042 | static void | |
2043 | nv50_pior_disconnect(struct drm_encoder *encoder) | |
2044 | { | |
2045 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2046 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2047 | const int or = nv_encoder->or; | |
2048 | u32 *push; | |
2049 | ||
2050 | if (nv_encoder->crtc) { | |
2051 | nv50_crtc_prepare(nv_encoder->crtc); | |
2052 | ||
2053 | push = evo_wait(mast, 4); | |
2054 | if (push) { | |
2055 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { | |
2056 | evo_mthd(push, 0x0700 + (or * 0x040), 1); | |
2057 | evo_data(push, 0x00000000); | |
2058 | } | |
eb6313ad BS |
2059 | evo_kick(push, mast); |
2060 | } | |
2061 | } | |
2062 | ||
2063 | nv_encoder->crtc = NULL; | |
2064 | } | |
2065 | ||
2066 | static void | |
2067 | nv50_pior_destroy(struct drm_encoder *encoder) | |
2068 | { | |
2069 | drm_encoder_cleanup(encoder); | |
2070 | kfree(encoder); | |
2071 | } | |
2072 | ||
2073 | static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { | |
2074 | .dpms = nv50_pior_dpms, | |
2075 | .mode_fixup = nv50_pior_mode_fixup, | |
2076 | .prepare = nv50_pior_disconnect, | |
2077 | .commit = nv50_pior_commit, | |
2078 | .mode_set = nv50_pior_mode_set, | |
2079 | .disable = nv50_pior_disconnect, | |
2080 | .get_crtc = nv50_display_crtc_get, | |
2081 | }; | |
2082 | ||
2083 | static const struct drm_encoder_funcs nv50_pior_func = { | |
2084 | .destroy = nv50_pior_destroy, | |
2085 | }; | |
2086 | ||
2087 | static int | |
2088 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) | |
2089 | { | |
2090 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
2091 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); | |
2092 | struct nouveau_i2c_port *ddc = NULL; | |
2093 | struct nouveau_encoder *nv_encoder; | |
2094 | struct drm_encoder *encoder; | |
2095 | int type; | |
2096 | ||
2097 | switch (dcbe->type) { | |
2098 | case DCB_OUTPUT_TMDS: | |
2099 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev)); | |
2100 | type = DRM_MODE_ENCODER_TMDS; | |
2101 | break; | |
2102 | case DCB_OUTPUT_DP: | |
2103 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev)); | |
2104 | type = DRM_MODE_ENCODER_TMDS; | |
2105 | break; | |
2106 | default: | |
2107 | return -ENODEV; | |
2108 | } | |
2109 | ||
2110 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2111 | if (!nv_encoder) | |
2112 | return -ENOMEM; | |
2113 | nv_encoder->dcb = dcbe; | |
2114 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2115 | nv_encoder->i2c = ddc; | |
2116 | ||
2117 | encoder = to_drm_encoder(nv_encoder); | |
2118 | encoder->possible_crtcs = dcbe->heads; | |
2119 | encoder->possible_clones = 0; | |
2120 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type); | |
2121 | drm_encoder_helper_add(encoder, &nv50_pior_hfunc); | |
2122 | ||
2123 | drm_mode_connector_attach_encoder(connector, encoder); | |
2124 | return 0; | |
2125 | } | |
2126 | ||
26f6d88b BS |
2127 | /****************************************************************************** |
2128 | * Init | |
2129 | *****************************************************************************/ | |
2a44e499 | 2130 | void |
e225f446 | 2131 | nv50_display_fini(struct drm_device *dev) |
26f6d88b | 2132 | { |
26f6d88b BS |
2133 | } |
2134 | ||
2135 | int | |
e225f446 | 2136 | nv50_display_init(struct drm_device *dev) |
26f6d88b | 2137 | { |
9f9bdaaf BS |
2138 | struct nv50_disp *disp = nv50_disp(dev); |
2139 | struct drm_crtc *crtc; | |
2140 | u32 *push; | |
2141 | ||
2142 | push = evo_wait(nv50_mast(dev), 32); | |
2143 | if (!push) | |
2144 | return -EBUSY; | |
2145 | ||
2146 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2147 | struct nv50_sync *sync = nv50_sync(crtc); | |
2148 | nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); | |
bdb8c212 | 2149 | } |
efd272a7 | 2150 | |
9f9bdaaf BS |
2151 | evo_mthd(push, 0x0088, 1); |
2152 | evo_data(push, NvEvoSync); | |
2153 | evo_kick(push, nv50_mast(dev)); | |
2154 | return 0; | |
26f6d88b BS |
2155 | } |
2156 | ||
2157 | void | |
e225f446 | 2158 | nv50_display_destroy(struct drm_device *dev) |
26f6d88b | 2159 | { |
e225f446 | 2160 | struct nv50_disp *disp = nv50_disp(dev); |
bdb8c212 | 2161 | |
e225f446 | 2162 | nv50_dmac_destroy(disp->core, &disp->mast.base); |
26f6d88b | 2163 | |
816af2f2 | 2164 | nouveau_bo_unmap(disp->sync); |
04c8c210 MS |
2165 | if (disp->sync) |
2166 | nouveau_bo_unpin(disp->sync); | |
816af2f2 | 2167 | nouveau_bo_ref(NULL, &disp->sync); |
51beb428 | 2168 | |
77145f1c | 2169 | nouveau_display(dev)->priv = NULL; |
26f6d88b BS |
2170 | kfree(disp); |
2171 | } | |
2172 | ||
2173 | int | |
e225f446 | 2174 | nv50_display_create(struct drm_device *dev) |
26f6d88b | 2175 | { |
b5a794b0 | 2176 | static const u16 oclass[] = { |
e5398b23 | 2177 | NVF0_DISP_CLASS, |
b5a794b0 BS |
2178 | NVE0_DISP_CLASS, |
2179 | NVD0_DISP_CLASS, | |
63718a07 BS |
2180 | NVA3_DISP_CLASS, |
2181 | NV94_DISP_CLASS, | |
2182 | NVA0_DISP_CLASS, | |
2183 | NV84_DISP_CLASS, | |
2184 | NV50_DISP_CLASS, | |
b5a794b0 | 2185 | }; |
77145f1c BS |
2186 | struct nouveau_device *device = nouveau_dev(dev); |
2187 | struct nouveau_drm *drm = nouveau_drm(dev); | |
77145f1c | 2188 | struct dcb_table *dcb = &drm->vbios.dcb; |
83fc083c | 2189 | struct drm_connector *connector, *tmp; |
e225f446 | 2190 | struct nv50_disp *disp; |
cb75d97e | 2191 | struct dcb_output *dcbe; |
7c5f6a87 | 2192 | int crtcs, ret, i; |
26f6d88b BS |
2193 | |
2194 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
2195 | if (!disp) | |
2196 | return -ENOMEM; | |
77145f1c BS |
2197 | |
2198 | nouveau_display(dev)->priv = disp; | |
e225f446 BS |
2199 | nouveau_display(dev)->dtor = nv50_display_destroy; |
2200 | nouveau_display(dev)->init = nv50_display_init; | |
2201 | nouveau_display(dev)->fini = nv50_display_fini; | |
26f6d88b | 2202 | |
b5a794b0 BS |
2203 | /* small shared memory area we use for notifiers and semaphores */ |
2204 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
2205 | 0, 0x0000, NULL, &disp->sync); | |
2206 | if (!ret) { | |
2207 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM); | |
04c8c210 | 2208 | if (!ret) { |
b5a794b0 | 2209 | ret = nouveau_bo_map(disp->sync); |
04c8c210 MS |
2210 | if (ret) |
2211 | nouveau_bo_unpin(disp->sync); | |
2212 | } | |
b5a794b0 BS |
2213 | if (ret) |
2214 | nouveau_bo_ref(NULL, &disp->sync); | |
2215 | } | |
2216 | ||
2217 | if (ret) | |
2218 | goto out; | |
2219 | ||
2220 | /* attempt to allocate a supported evo display class */ | |
2221 | ret = -ENODEV; | |
2222 | for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) { | |
2223 | ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE, | |
2224 | 0xd1500000, oclass[i], NULL, 0, | |
2225 | &disp->core); | |
2226 | } | |
2227 | ||
2228 | if (ret) | |
2229 | goto out; | |
2230 | ||
2231 | /* allocate master evo channel */ | |
e225f446 | 2232 | ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0, |
b5a794b0 BS |
2233 | &(struct nv50_display_mast_class) { |
2234 | .pushbuf = EVO_PUSH_HANDLE(MAST, 0), | |
2235 | }, sizeof(struct nv50_display_mast_class), | |
2236 | disp->sync->bo.offset, &disp->mast.base); | |
2237 | if (ret) | |
2238 | goto out; | |
2239 | ||
438d99e3 | 2240 | /* create crtc objects to represent the hw heads */ |
63718a07 BS |
2241 | if (nv_mclass(disp->core) >= NVD0_DISP_CLASS) |
2242 | crtcs = nv_rd32(device, 0x022448); | |
2243 | else | |
2244 | crtcs = 2; | |
2245 | ||
7c5f6a87 | 2246 | for (i = 0; i < crtcs; i++) { |
e225f446 | 2247 | ret = nv50_crtc_create(dev, disp->core, i); |
438d99e3 BS |
2248 | if (ret) |
2249 | goto out; | |
2250 | } | |
2251 | ||
83fc083c BS |
2252 | /* create encoder/connector objects based on VBIOS DCB table */ |
2253 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
2254 | connector = nouveau_connector_create(dev, dcbe->connector); | |
2255 | if (IS_ERR(connector)) | |
2256 | continue; | |
2257 | ||
eb6313ad BS |
2258 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
2259 | switch (dcbe->type) { | |
2260 | case DCB_OUTPUT_TMDS: | |
2261 | case DCB_OUTPUT_LVDS: | |
2262 | case DCB_OUTPUT_DP: | |
2263 | ret = nv50_sor_create(connector, dcbe); | |
2264 | break; | |
2265 | case DCB_OUTPUT_ANALOG: | |
2266 | ret = nv50_dac_create(connector, dcbe); | |
2267 | break; | |
2268 | default: | |
2269 | ret = -ENODEV; | |
2270 | break; | |
2271 | } | |
2272 | } else { | |
2273 | ret = nv50_pior_create(connector, dcbe); | |
83fc083c BS |
2274 | } |
2275 | ||
eb6313ad BS |
2276 | if (ret) { |
2277 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", | |
2278 | dcbe->location, dcbe->type, | |
2279 | ffs(dcbe->or) - 1, ret); | |
94f54f53 | 2280 | ret = 0; |
83fc083c BS |
2281 | } |
2282 | } | |
2283 | ||
2284 | /* cull any connectors we created that don't have an encoder */ | |
2285 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
2286 | if (connector->encoder_ids[0]) | |
2287 | continue; | |
2288 | ||
77145f1c | 2289 | NV_WARN(drm, "%s has no encoders, removing\n", |
83fc083c BS |
2290 | drm_get_connector_name(connector)); |
2291 | connector->funcs->destroy(connector); | |
2292 | } | |
2293 | ||
26f6d88b BS |
2294 | out: |
2295 | if (ret) | |
e225f446 | 2296 | nv50_display_destroy(dev); |
26f6d88b BS |
2297 | return ret; |
2298 | } |