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Merge branch 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[linux-block.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
e225f446 1 /*
26f6d88b
BS		 2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
51beb428 25#include <linux/dma-mapping.h>
83fc083c 26
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/drm_crtc_helper.h>
26f6d88b 29
77145f1c
BS		 30#include "nouveau_drm.h"
31#include "nouveau_dma.h"
32#include "nouveau_gem.h"
26f6d88b
BS		 33#include "nouveau_connector.h"
34#include "nouveau_encoder.h"
35#include "nouveau_crtc.h"
f589be88 36#include "nouveau_fence.h"
3a89cd02 37#include "nv50_display.h"
26f6d88b 38
b5a794b0 39#include <core/client.h>
77145f1c 40#include <core/gpuobj.h>
b5a794b0 41#include <core/class.h>
77145f1c
BS		 42
43#include <subdev/timer.h>
44#include <subdev/bar.h>
45#include <subdev/fb.h>
5ed50209 46#include <subdev/i2c.h>
77145f1c 47
8a46438a
BS		 48#define EVO_DMA_NR 9
49
bdb8c212 50#define EVO_MASTER (0x00)
a63a97eb 51#define EVO_FLIP(c) (0x01 + (c))
8a46438a
BS		 52#define EVO_OVLY(c) (0x05 + (c))
53#define EVO_OIMM(c) (0x09 + (c))
bdb8c212
BS		 54#define EVO_CURS(c) (0x0d + (c))
55
816af2f2
BS		 56/* offsets in shared sync bo of various structures */
57#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
9f9bdaaf
BS		 58#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
59#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
60#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
816af2f2 61
b5a794b0
BS		 62#define EVO_CORE_HANDLE (0xd1500000)
63#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
64#define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
65#define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
66 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
67
68/******************************************************************************
69 * EVO channel
70 *****************************************************************************/
71
e225f446 72struct nv50_chan {
b5a794b0
BS		 73 struct nouveau_object *user;
74 u32 handle;
75};
76
77static int
e225f446
BS		 78nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
79 void *data, u32 size, struct nv50_chan *chan)
b5a794b0
BS		 80{
81 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
82 const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
83 const u32 handle = EVO_CHAN_HANDLE(bclass, head);
84 int ret;
85
86 ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
87 oclass, data, size, &chan->user);
88 if (ret)
89 return ret;
90
91 chan->handle = handle;
92 return 0;
93}
94
95static void
e225f446 96nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
b5a794b0
BS		 97{
98 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
99 if (chan->handle)
100 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
101}
102
103/******************************************************************************
104 * PIO EVO channel
105 *****************************************************************************/
106
e225f446
BS		 107struct nv50_pioc {
108 struct nv50_chan base;
b5a794b0
BS		 109};
110
111static void
e225f446 112nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
b5a794b0 113{
e225f446 114 nv50_chan_destroy(core, &pioc->base);
b5a794b0
BS		 115}
116
117static int
e225f446
BS		 118nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
119 void *data, u32 size, struct nv50_pioc *pioc)
b5a794b0 120{
e225f446 121 return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
b5a794b0
BS		 122}
123
124/******************************************************************************
125 * DMA EVO channel
126 *****************************************************************************/
127
e225f446
BS		 128struct nv50_dmac {
129 struct nv50_chan base;
3376ee37
BS		 130 dma_addr_t handle;
131 u32 *ptr;
59ad1465
DV		 132
133 /* Protects against concurrent pushbuf access to this channel, lock is
134 * grabbed by evo_wait (if the pushbuf reservation is successful) and
135 * dropped again by evo_kick. */
136 struct mutex lock;
b5a794b0
BS		 137};
138
139static void
e225f446 140nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
b5a794b0
BS		 141{
142 if (dmac->ptr) {
143 struct pci_dev *pdev = nv_device(core)->pdev;
144 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
145 }
146
e225f446 147 nv50_chan_destroy(core, &dmac->base);
b5a794b0
BS		 148}
149
150static int
47057302 151nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
b5a794b0
BS		 152{
153 struct nouveau_fb *pfb = nouveau_fb(core);
154 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
155 struct nouveau_object *object;
47057302
BS		 156 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
157 NV_DMA_IN_MEMORY_CLASS,
158 &(struct nv_dma_class) {
159 .flags = NV_DMA_TARGET_VRAM |
160 NV_DMA_ACCESS_RDWR,
161 .start = 0,
dceef5d8 162 .limit = pfb->ram->size - 1,
47057302
BS		 163 .conf0 = NV50_DMA_CONF0_ENABLE |
164 NV50_DMA_CONF0_PART_256,
165 }, sizeof(struct nv_dma_class), &object);
166 if (ret)
167 return ret;
b5a794b0 168
47057302
BS		 169 ret = nouveau_object_new(client, parent, NvEvoFB16,
170 NV_DMA_IN_MEMORY_CLASS,
b5a794b0 171 &(struct nv_dma_class) {
47057302
BS		 172 .flags = NV_DMA_TARGET_VRAM |
173 NV_DMA_ACCESS_RDWR,
174 .start = 0,
dceef5d8 175 .limit = pfb->ram->size - 1,
47057302
BS		 176 .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
177 NV50_DMA_CONF0_PART_256,
b5a794b0
BS		 178 }, sizeof(struct nv_dma_class), &object);
179 if (ret)
180 return ret;
181
47057302
BS		 182 ret = nouveau_object_new(client, parent, NvEvoFB32,
183 NV_DMA_IN_MEMORY_CLASS,
184 &(struct nv_dma_class) {
185 .flags = NV_DMA_TARGET_VRAM |
186 NV_DMA_ACCESS_RDWR,
187 .start = 0,
dceef5d8 188 .limit = pfb->ram->size - 1,
47057302
BS		 189 .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
190 NV50_DMA_CONF0_PART_256,
191 }, sizeof(struct nv_dma_class), &object);
192 return ret;
193}
194
195static int
196nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
197{
198 struct nouveau_fb *pfb = nouveau_fb(core);
199 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
200 struct nouveau_object *object;
201 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
202 NV_DMA_IN_MEMORY_CLASS,
203 &(struct nv_dma_class) {
204 .flags = NV_DMA_TARGET_VRAM |
205 NV_DMA_ACCESS_RDWR,
206 .start = 0,
dceef5d8 207 .limit = pfb->ram->size - 1,
47057302
BS		 208 .conf0 = NVC0_DMA_CONF0_ENABLE,
209 }, sizeof(struct nv_dma_class), &object);
b5a794b0
BS		 210 if (ret)
211 return ret;
212
47057302 213 ret = nouveau_object_new(client, parent, NvEvoFB16,
b5a794b0
BS		 214 NV_DMA_IN_MEMORY_CLASS,
215 &(struct nv_dma_class) {
216 .flags = NV_DMA_TARGET_VRAM |
217 NV_DMA_ACCESS_RDWR,
47057302 218 .start = 0,
dceef5d8 219 .limit = pfb->ram->size - 1,
47057302 220 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
b5a794b0
BS		 221 }, sizeof(struct nv_dma_class), &object);
222 if (ret)
47057302 223 return ret;
b5a794b0 224
47057302 225 ret = nouveau_object_new(client, parent, NvEvoFB32,
b5a794b0
BS		 226 NV_DMA_IN_MEMORY_CLASS,
227 &(struct nv_dma_class) {
228 .flags = NV_DMA_TARGET_VRAM |
229 NV_DMA_ACCESS_RDWR,
230 .start = 0,
dceef5d8 231 .limit = pfb->ram->size - 1,
47057302 232 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
b5a794b0 233 }, sizeof(struct nv_dma_class), &object);
47057302
BS		 234 return ret;
235}
236
237static int
238nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
239{
240 struct nouveau_fb *pfb = nouveau_fb(core);
241 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
242 struct nouveau_object *object;
243 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
244 NV_DMA_IN_MEMORY_CLASS,
245 &(struct nv_dma_class) {
246 .flags = NV_DMA_TARGET_VRAM |
247 NV_DMA_ACCESS_RDWR,
248 .start = 0,
dceef5d8 249 .limit = pfb->ram->size - 1,
47057302
BS		 250 .conf0 = NVD0_DMA_CONF0_ENABLE |
251 NVD0_DMA_CONF0_PAGE_LP,
252 }, sizeof(struct nv_dma_class), &object);
b5a794b0 253 if (ret)
47057302 254 return ret;
b5a794b0 255
47057302 256 ret = nouveau_object_new(client, parent, NvEvoFB32,
b5a794b0
BS		 257 NV_DMA_IN_MEMORY_CLASS,
258 &(struct nv_dma_class) {
259 .flags = NV_DMA_TARGET_VRAM |
260 NV_DMA_ACCESS_RDWR,
261 .start = 0,
dceef5d8 262 .limit = pfb->ram->size - 1,
47057302 263 .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
b5a794b0
BS		 264 NVD0_DMA_CONF0_PAGE_LP,
265 }, sizeof(struct nv_dma_class), &object);
47057302
BS		 266 return ret;
267}
268
269static int
e225f446 270nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
47057302 271 void *data, u32 size, u64 syncbuf,
e225f446 272 struct nv50_dmac *dmac)
47057302
BS		 273{
274 struct nouveau_fb *pfb = nouveau_fb(core);
275 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
276 struct nouveau_object *object;
277 u32 pushbuf = *(u32 *)data;
278 int ret;
279
59ad1465
DV		 280 mutex_init(&dmac->lock);
281
47057302
BS		 282 dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
283 &dmac->handle);
284 if (!dmac->ptr)
285 return -ENOMEM;
286
287 ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
288 NV_DMA_FROM_MEMORY_CLASS,
289 &(struct nv_dma_class) {
290 .flags = NV_DMA_TARGET_PCI_US |
291 NV_DMA_ACCESS_RD,
292 .start = dmac->handle + 0x0000,
293 .limit = dmac->handle + 0x0fff,
294 }, sizeof(struct nv_dma_class), &object);
b5a794b0 295 if (ret)
47057302 296 return ret;
b5a794b0 297
e225f446 298 ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
47057302
BS		 299 if (ret)
300 return ret;
301
302 ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
303 NV_DMA_IN_MEMORY_CLASS,
304 &(struct nv_dma_class) {
305 .flags = NV_DMA_TARGET_VRAM |
306 NV_DMA_ACCESS_RDWR,
307 .start = syncbuf + 0x0000,
308 .limit = syncbuf + 0x0fff,
309 }, sizeof(struct nv_dma_class), &object);
310 if (ret)
311 return ret;
312
313 ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
b5a794b0
BS		 314 NV_DMA_IN_MEMORY_CLASS,
315 &(struct nv_dma_class) {
316 .flags = NV_DMA_TARGET_VRAM |
317 NV_DMA_ACCESS_RDWR,
318 .start = 0,
dceef5d8 319 .limit = pfb->ram->size - 1,
b5a794b0 320 }, sizeof(struct nv_dma_class), &object);
b5a794b0 321 if (ret)
47057302
BS		 322 return ret;
323
324 if (nv_device(core)->card_type < NV_C0)
325 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
326 else
327 if (nv_device(core)->card_type < NV_D0)
328 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
329 else
330 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
b5a794b0
BS		 331 return ret;
332}
333
e225f446
BS		 334struct nv50_mast {
335 struct nv50_dmac base;
b5a794b0
BS		 336};
337
e225f446
BS		 338struct nv50_curs {
339 struct nv50_pioc base;
b5a794b0
BS		 340};
341
e225f446
BS		 342struct nv50_sync {
343 struct nv50_dmac base;
9f9bdaaf
BS		 344 u32 addr;
345 u32 data;
3376ee37
BS		 346};
347
e225f446
BS		 348struct nv50_ovly {
349 struct nv50_dmac base;
b5a794b0 350};
f20ce962 351
e225f446
BS		 352struct nv50_oimm {
353 struct nv50_pioc base;
26f6d88b
BS		 354};
355
e225f446 356struct nv50_head {
dd0e3d53 357 struct nouveau_crtc base;
8dda53fc 358 struct nouveau_bo *image;
e225f446
BS		 359 struct nv50_curs curs;
360 struct nv50_sync sync;
361 struct nv50_ovly ovly;
362 struct nv50_oimm oimm;
b5a794b0
BS		 363};
364
e225f446
BS		 365#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
366#define nv50_curs(c) (&nv50_head(c)->curs)
367#define nv50_sync(c) (&nv50_head(c)->sync)
368#define nv50_ovly(c) (&nv50_head(c)->ovly)
369#define nv50_oimm(c) (&nv50_head(c)->oimm)
370#define nv50_chan(c) (&(c)->base.base)
371#define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
b5a794b0 372
e225f446 373struct nv50_disp {
b5a794b0 374 struct nouveau_object *core;
e225f446 375 struct nv50_mast mast;
b5a794b0 376
b5a794b0
BS		 377 u32 modeset;
378
379 struct nouveau_bo *sync;
dd0e3d53
BS		 380};
381
e225f446
BS		 382static struct nv50_disp *
383nv50_disp(struct drm_device *dev)
26f6d88b 384{
77145f1c 385 return nouveau_display(dev)->priv;
26f6d88b
BS		 386}
387
e225f446 388#define nv50_mast(d) (&nv50_disp(d)->mast)
b5a794b0 389
bdb8c212 390static struct drm_crtc *
e225f446 391nv50_display_crtc_get(struct drm_encoder *encoder)
bdb8c212
BS		 392{
393 return nouveau_encoder(encoder)->crtc;
394}
395
396/******************************************************************************
397 * EVO channel helpers
398 *****************************************************************************/
51beb428 399static u32 *
b5a794b0 400evo_wait(void *evoc, int nr)
51beb428 401{
e225f446 402 struct nv50_dmac *dmac = evoc;
b5a794b0 403 u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
51beb428 404
59ad1465 405 mutex_lock(&dmac->lock);
de8268c5 406 if (put + nr >= (PAGE_SIZE / 4) - 8) {
b5a794b0 407 dmac->ptr[put] = 0x20000000;
51beb428 408
b5a794b0
BS		 409 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
410 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
59ad1465 411 mutex_unlock(&dmac->lock);
b5a794b0 412 NV_ERROR(dmac->base.user, "channel stalled\n");
51beb428
BS		 413 return NULL;
414 }
415
416 put = 0;
417 }
418
b5a794b0 419 return dmac->ptr + put;
51beb428
BS		 420}
421
422static void
b5a794b0 423evo_kick(u32 *push, void *evoc)
51beb428 424{
e225f446 425 struct nv50_dmac *dmac = evoc;
b5a794b0 426 nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
59ad1465 427 mutex_unlock(&dmac->lock);
51beb428
BS		 428}
429
430#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
431#define evo_data(p,d) *((p)++) = (d)
432
3376ee37
BS		 433static bool
434evo_sync_wait(void *data)
435{
5cc027f6
BS		 436 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
437 return true;
438 usleep_range(1, 2);
439 return false;
3376ee37
BS		 440}
441
442static int
b5a794b0 443evo_sync(struct drm_device *dev)
3376ee37 444{
77145f1c 445 struct nouveau_device *device = nouveau_dev(dev);
e225f446
BS		 446 struct nv50_disp *disp = nv50_disp(dev);
447 struct nv50_mast *mast = nv50_mast(dev);
b5a794b0 448 u32 *push = evo_wait(mast, 8);
3376ee37 449 if (push) {
816af2f2 450 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
3376ee37 451 evo_mthd(push, 0x0084, 1);
816af2f2 452 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
3376ee37
BS		 453 evo_mthd(push, 0x0080, 2);
454 evo_data(push, 0x00000000);
455 evo_data(push, 0x00000000);
b5a794b0 456 evo_kick(push, mast);
77145f1c 457 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
3376ee37
BS		 458 return 0;
459 }
460
461 return -EBUSY;
462}
463
464/******************************************************************************
a63a97eb 465 * Page flipping channel
3376ee37
BS		 466 *****************************************************************************/
467struct nouveau_bo *
e225f446 468nv50_display_crtc_sema(struct drm_device *dev, int crtc)
3376ee37 469{
e225f446 470 return nv50_disp(dev)->sync;
3376ee37
BS		 471}
472
9f9bdaaf
BS		 473struct nv50_display_flip {
474 struct nv50_disp *disp;
475 struct nv50_sync *chan;
476};
477
478static bool
479nv50_display_flip_wait(void *data)
480{
481 struct nv50_display_flip *flip = data;
482 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
b1ea3e6e 483 flip->chan->data)
9f9bdaaf
BS		 484 return true;
485 usleep_range(1, 2);
486 return false;
487}
488
3376ee37 489void
e225f446 490nv50_display_flip_stop(struct drm_crtc *crtc)
3376ee37 491{
9f9bdaaf
BS		 492 struct nouveau_device *device = nouveau_dev(crtc->dev);
493 struct nv50_display_flip flip = {
494 .disp = nv50_disp(crtc->dev),
495 .chan = nv50_sync(crtc),
496 };
3376ee37
BS		 497 u32 *push;
498
9f9bdaaf 499 push = evo_wait(flip.chan, 8);
3376ee37
BS		 500 if (push) {
501 evo_mthd(push, 0x0084, 1);
502 evo_data(push, 0x00000000);
503 evo_mthd(push, 0x0094, 1);
504 evo_data(push, 0x00000000);
505 evo_mthd(push, 0x00c0, 1);
506 evo_data(push, 0x00000000);
507 evo_mthd(push, 0x0080, 1);
508 evo_data(push, 0x00000000);
9f9bdaaf 509 evo_kick(push, flip.chan);
3376ee37 510 }
9f9bdaaf
BS		 511
512 nv_wait_cb(device, nv50_display_flip_wait, &flip);
3376ee37
BS		 513}
514
515int
e225f446 516nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3376ee37
BS		 517 struct nouveau_channel *chan, u32 swap_interval)
518{
519 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
3376ee37 520 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
8dda53fc 521 struct nv50_head *head = nv50_head(crtc);
e225f446 522 struct nv50_sync *sync = nv50_sync(crtc);
3376ee37 523 u32 *push;
8dda53fc 524 int ret;
3376ee37
BS		 525
526 swap_interval <<= 4;
527 if (swap_interval == 0)
528 swap_interval |= 0x100;
f60b6e7a
BS		 529 if (chan == NULL)
530 evo_sync(crtc->dev);
3376ee37 531
b5a794b0 532 push = evo_wait(sync, 128);
3376ee37
BS		 533 if (unlikely(push == NULL))
534 return -EBUSY;
535
9f9bdaaf
BS		 536 if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
537 ret = RING_SPACE(chan, 8);
538 if (ret)
539 return ret;
540
541 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
8dda53fc 542 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
9f9bdaaf
BS		 543 OUT_RING (chan, sync->addr ^ 0x10);
544 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
545 OUT_RING (chan, sync->data + 1);
546 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
547 OUT_RING (chan, sync->addr);
548 OUT_RING (chan, sync->data);
549 } else
550 if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
8dda53fc 551 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 552 ret = RING_SPACE(chan, 12);
553 if (ret)
554 return ret;
555
556 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
557 OUT_RING (chan, chan->vram);
558 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
559 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
560 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
561 OUT_RING (chan, sync->data + 1);
562 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
563 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
564 OUT_RING (chan, upper_32_bits(addr));
565 OUT_RING (chan, lower_32_bits(addr));
566 OUT_RING (chan, sync->data);
567 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
568 } else
569 if (chan) {
8dda53fc 570 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 571 ret = RING_SPACE(chan, 10);
572 if (ret)
573 return ret;
574
575 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
576 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
577 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
578 OUT_RING (chan, sync->data + 1);
579 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
580 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
581 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
582 OUT_RING (chan, upper_32_bits(addr));
583 OUT_RING (chan, lower_32_bits(addr));
584 OUT_RING (chan, sync->data);
585 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
586 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
587 }
35bcf5d5 588
9f9bdaaf
BS		 589 if (chan) {
590 sync->addr ^= 0x10;
591 sync->data++;
3376ee37 592 FIRE_RING (chan);
3376ee37
BS		 593 }
594
595 /* queue the flip */
596 evo_mthd(push, 0x0100, 1);
597 evo_data(push, 0xfffe0000);
598 evo_mthd(push, 0x0084, 1);
599 evo_data(push, swap_interval);
600 if (!(swap_interval & 0x00000100)) {
601 evo_mthd(push, 0x00e0, 1);
602 evo_data(push, 0x40000000);
603 }
604 evo_mthd(push, 0x0088, 4);
9f9bdaaf
BS		 605 evo_data(push, sync->addr);
606 evo_data(push, sync->data++);
607 evo_data(push, sync->data);
3376ee37
BS		 608 evo_data(push, NvEvoSync);
609 evo_mthd(push, 0x00a0, 2);
610 evo_data(push, 0x00000000);
611 evo_data(push, 0x00000000);
612 evo_mthd(push, 0x00c0, 1);
613 evo_data(push, nv_fb->r_dma);
614 evo_mthd(push, 0x0110, 2);
615 evo_data(push, 0x00000000);
616 evo_data(push, 0x00000000);
e225f446 617 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
ed5085a5
BS		 618 evo_mthd(push, 0x0800, 5);
619 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
620 evo_data(push, 0);
621 evo_data(push, (fb->height << 16) | fb->width);
622 evo_data(push, nv_fb->r_pitch);
623 evo_data(push, nv_fb->r_format);
624 } else {
625 evo_mthd(push, 0x0400, 5);
626 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
627 evo_data(push, 0);
628 evo_data(push, (fb->height << 16) | fb->width);
629 evo_data(push, nv_fb->r_pitch);
630 evo_data(push, nv_fb->r_format);
631 }
3376ee37
BS		 632 evo_mthd(push, 0x0080, 1);
633 evo_data(push, 0x00000000);
b5a794b0 634 evo_kick(push, sync);
8dda53fc
BS		 635
636 nouveau_bo_ref(nv_fb->nvbo, &head->image);
3376ee37
BS		 637 return 0;
638}
639
438d99e3
BS		 640/******************************************************************************
641 * CRTC
642 *****************************************************************************/
643static int
e225f446 644nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 645{
e225f446 646 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de691855
BS		 647 struct nouveau_connector *nv_connector;
648 struct drm_connector *connector;
649 u32 *push, mode = 0x00;
438d99e3 650
488ff207 651 nv_connector = nouveau_crtc_connector_get(nv_crtc);
de691855
BS		 652 connector = &nv_connector->base;
653 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
654 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
655 mode = DITHERING_MODE_DYNAMIC2X2;
656 } else {
657 mode = nv_connector->dithering_mode;
658 }
659
660 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
661 if (connector->display_info.bpc >= 8)
662 mode |= DITHERING_DEPTH_8BPC;
663 } else {
664 mode |= nv_connector->dithering_depth;
438d99e3
BS		 665 }
666
de8268c5 667 push = evo_wait(mast, 4);
438d99e3 668 if (push) {
e225f446 669 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 670 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
671 evo_data(push, mode);
672 } else
e225f446 673 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
de8268c5
BS		 674 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
675 evo_data(push, mode);
676 } else {
677 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
678 evo_data(push, mode);
679 }
680
438d99e3
BS		 681 if (update) {
682 evo_mthd(push, 0x0080, 1);
683 evo_data(push, 0x00000000);
684 }
de8268c5 685 evo_kick(push, mast);
438d99e3
BS		 686 }
687
688 return 0;
689}
690
691static int
e225f446 692nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 693{
e225f446 694 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
92854622 695 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
3376ee37 696 struct drm_crtc *crtc = &nv_crtc->base;
f3fdc52d 697 struct nouveau_connector *nv_connector;
92854622
BS		 698 int mode = DRM_MODE_SCALE_NONE;
699 u32 oX, oY, *push;
f3fdc52d 700
92854622
BS		 701 /* start off at the resolution we programmed the crtc for, this
702 * effectively handles NONE/FULL scaling
703 */
f3fdc52d 704 nv_connector = nouveau_crtc_connector_get(nv_crtc);
92854622
BS		 705 if (nv_connector && nv_connector->native_mode)
706 mode = nv_connector->scaling_mode;
707
708 if (mode != DRM_MODE_SCALE_NONE)
709 omode = nv_connector->native_mode;
710 else
711 omode = umode;
712
713 oX = omode->hdisplay;
714 oY = omode->vdisplay;
715 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
716 oY *= 2;
717
718 /* add overscan compensation if necessary, will keep the aspect
719 * ratio the same as the backend mode unless overridden by the
720 * user setting both hborder and vborder properties.
721 */
722 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
723 (nv_connector->underscan == UNDERSCAN_AUTO &&
724 nv_connector->edid &&
725 drm_detect_hdmi_monitor(nv_connector->edid)))) {
726 u32 bX = nv_connector->underscan_hborder;
727 u32 bY = nv_connector->underscan_vborder;
728 u32 aspect = (oY << 19) / oX;
729
730 if (bX) {
731 oX -= (bX * 2);
732 if (bY) oY -= (bY * 2);
733 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
734 } else {
735 oX -= (oX >> 4) + 32;
736 if (bY) oY -= (bY * 2);
737 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
738 }
739 }
740
741 /* handle CENTER/ASPECT scaling, taking into account the areas
742 * removed already for overscan compensation
743 */
744 switch (mode) {
745 case DRM_MODE_SCALE_CENTER:
746 oX = min((u32)umode->hdisplay, oX);
747 oY = min((u32)umode->vdisplay, oY);
748 /* fall-through */
749 case DRM_MODE_SCALE_ASPECT:
750 if (oY < oX) {
751 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
752 oX = ((oY * aspect) + (aspect / 2)) >> 19;
753 } else {
754 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
755 oY = ((oX * aspect) + (aspect / 2)) >> 19;
f3fdc52d 756 }
92854622
BS		 757 break;
758 default:
759 break;
f3fdc52d 760 }
438d99e3 761
de8268c5 762 push = evo_wait(mast, 8);
438d99e3 763 if (push) {
e225f446 764 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 765 /*XXX: SCALE_CTRL_ACTIVE??? */
766 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
767 evo_data(push, (oY << 16) | oX);
768 evo_data(push, (oY << 16) | oX);
769 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
770 evo_data(push, 0x00000000);
771 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
772 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
773 } else {
774 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
775 evo_data(push, (oY << 16) | oX);
776 evo_data(push, (oY << 16) | oX);
777 evo_data(push, (oY << 16) | oX);
778 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
779 evo_data(push, 0x00000000);
780 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
781 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
782 }
783
784 evo_kick(push, mast);
785
438d99e3 786 if (update) {
e225f446
BS		 787 nv50_display_flip_stop(crtc);
788 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
438d99e3 789 }
438d99e3
BS		 790 }
791
792 return 0;
793}
794
f9887d09 795static int
e225f446 796nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
f9887d09 797{
e225f446 798 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
f9887d09
BS		 799 u32 *push, hue, vib;
800 int adj;
801
802 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
803 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
804 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
805
806 push = evo_wait(mast, 16);
807 if (push) {
e225f446 808 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
f9887d09
BS		 809 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
810 evo_data(push, (hue << 20) | (vib << 8));
811 } else {
812 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
813 evo_data(push, (hue << 20) | (vib << 8));
814 }
815
816 if (update) {
817 evo_mthd(push, 0x0080, 1);
818 evo_data(push, 0x00000000);
819 }
820 evo_kick(push, mast);
821 }
822
823 return 0;
824}
825
438d99e3 826static int
e225f446 827nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
438d99e3
BS		 828 int x, int y, bool update)
829{
830 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
e225f446 831 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
438d99e3
BS		 832 u32 *push;
833
de8268c5 834 push = evo_wait(mast, 16);
438d99e3 835 if (push) {
e225f446 836 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 837 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
838 evo_data(push, nvfb->nvbo->bo.offset >> 8);
839 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
840 evo_data(push, (fb->height << 16) | fb->width);
841 evo_data(push, nvfb->r_pitch);
842 evo_data(push, nvfb->r_format);
843 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
844 evo_data(push, (y << 16) | x);
e225f446 845 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
de8268c5
BS		 846 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
847 evo_data(push, nvfb->r_dma);
848 }
849 } else {
850 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
851 evo_data(push, nvfb->nvbo->bo.offset >> 8);
852 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
853 evo_data(push, (fb->height << 16) | fb->width);
854 evo_data(push, nvfb->r_pitch);
855 evo_data(push, nvfb->r_format);
856 evo_data(push, nvfb->r_dma);
857 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
858 evo_data(push, (y << 16) | x);
859 }
860
a46232ee
BS		 861 if (update) {
862 evo_mthd(push, 0x0080, 1);
863 evo_data(push, 0x00000000);
864 }
de8268c5 865 evo_kick(push, mast);
438d99e3
BS		 866 }
867
c0cc92a1 868 nv_crtc->fb.tile_flags = nvfb->r_dma;
438d99e3
BS		 869 return 0;
870}
871
872static void
e225f446 873nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
438d99e3 874{
e225f446 875 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5 876 u32 *push = evo_wait(mast, 16);
438d99e3 877 if (push) {
e225f446 878 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5
BS		 879 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
880 evo_data(push, 0x85000000);
881 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
882 } else
e225f446 883 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 884 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
885 evo_data(push, 0x85000000);
886 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
887 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
888 evo_data(push, NvEvoVRAM);
889 } else {
438d99e3
BS		 890 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
891 evo_data(push, 0x85000000);
892 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
893 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
37b034a6 894 evo_data(push, NvEvoVRAM);
de8268c5
BS		 895 }
896 evo_kick(push, mast);
897 }
898}
899
900static void
e225f446 901nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
de8268c5 902{
e225f446 903 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 904 u32 *push = evo_wait(mast, 16);
905 if (push) {
e225f446 906 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5
BS		 907 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
908 evo_data(push, 0x05000000);
909 } else
e225f446 910 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 911 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
912 evo_data(push, 0x05000000);
913 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
914 evo_data(push, 0x00000000);
438d99e3
BS		 915 } else {
916 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
917 evo_data(push, 0x05000000);
918 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
919 evo_data(push, 0x00000000);
920 }
de8268c5
BS		 921 evo_kick(push, mast);
922 }
923}
438d99e3 924
de8268c5 925static void
e225f446 926nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
de8268c5 927{
e225f446 928 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 929
930 if (show)
e225f446 931 nv50_crtc_cursor_show(nv_crtc);
de8268c5 932 else
e225f446 933 nv50_crtc_cursor_hide(nv_crtc);
de8268c5
BS		 934
935 if (update) {
936 u32 *push = evo_wait(mast, 2);
937 if (push) {
438d99e3
BS		 938 evo_mthd(push, 0x0080, 1);
939 evo_data(push, 0x00000000);
de8268c5 940 evo_kick(push, mast);
438d99e3 941 }
438d99e3
BS		 942 }
943}
944
945static void
e225f446 946nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
438d99e3
BS		 947{
948}
949
950static void
e225f446 951nv50_crtc_prepare(struct drm_crtc *crtc)
438d99e3
BS		 952{
953 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 954 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 955 u32 *push;
956
e225f446 957 nv50_display_flip_stop(crtc);
3376ee37 958
de8268c5 959 push = evo_wait(mast, 2);
438d99e3 960 if (push) {
e225f446 961 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5
BS		 962 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
963 evo_data(push, 0x00000000);
964 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
965 evo_data(push, 0x40000000);
966 } else
e225f446 967 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 968 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
969 evo_data(push, 0x00000000);
970 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
971 evo_data(push, 0x40000000);
972 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
973 evo_data(push, 0x00000000);
974 } else {
975 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
976 evo_data(push, 0x00000000);
977 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
978 evo_data(push, 0x03000000);
979 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
980 evo_data(push, 0x00000000);
981 }
982
983 evo_kick(push, mast);
438d99e3
BS		 984 }
985
e225f446 986 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
438d99e3
BS		 987}
988
989static void
e225f446 990nv50_crtc_commit(struct drm_crtc *crtc)
438d99e3
BS		 991{
992 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 993 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 994 u32 *push;
995
de8268c5 996 push = evo_wait(mast, 32);
438d99e3 997 if (push) {
e225f446 998 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5
BS		 999 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1000 evo_data(push, NvEvoVRAM_LP);
1001 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1002 evo_data(push, 0xc0000000);
1003 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1004 } else
e225f446 1005 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 1006 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1007 evo_data(push, nv_crtc->fb.tile_flags);
1008 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1009 evo_data(push, 0xc0000000);
1010 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1011 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1012 evo_data(push, NvEvoVRAM);
1013 } else {
1014 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1015 evo_data(push, nv_crtc->fb.tile_flags);
1016 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1017 evo_data(push, 0x83000000);
1018 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1019 evo_data(push, 0x00000000);
1020 evo_data(push, 0x00000000);
1021 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1022 evo_data(push, NvEvoVRAM);
1023 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1024 evo_data(push, 0xffffff00);
1025 }
1026
1027 evo_kick(push, mast);
438d99e3
BS		 1028 }
1029
e225f446
BS		 1030 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1031 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
438d99e3
BS		 1032}
1033
1034static bool
e225f446 1035nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
438d99e3
BS		 1036 struct drm_display_mode *adjusted_mode)
1037{
1038 return true;
1039}
1040
1041static int
e225f446 1042nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
438d99e3
BS		 1043{
1044 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
8dda53fc 1045 struct nv50_head *head = nv50_head(crtc);
438d99e3
BS		 1046 int ret;
1047
1048 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
8dda53fc
BS		 1049 if (ret == 0) {
1050 if (head->image)
1051 nouveau_bo_unpin(head->image);
1052 nouveau_bo_ref(nvfb->nvbo, &head->image);
438d99e3
BS		 1053 }
1054
8dda53fc 1055 return ret;
438d99e3
BS		 1056}
1057
1058static int
e225f446 1059nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
438d99e3
BS		 1060 struct drm_display_mode *mode, int x, int y,
1061 struct drm_framebuffer *old_fb)
1062{
e225f446 1063 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 1064 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1065 struct nouveau_connector *nv_connector;
2d1d898b
BS		 1066 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1067 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1068 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1069 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1070 u32 vblan2e = 0, vblan2s = 1;
3488c57b 1071 u32 *push;
438d99e3
BS		 1072 int ret;
1073
2d1d898b
BS		 1074 hactive = mode->htotal;
1075 hsynce = mode->hsync_end - mode->hsync_start - 1;
1076 hbackp = mode->htotal - mode->hsync_end;
1077 hblanke = hsynce + hbackp;
1078 hfrontp = mode->hsync_start - mode->hdisplay;
1079 hblanks = mode->htotal - hfrontp - 1;
1080
1081 vactive = mode->vtotal * vscan / ilace;
1082 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1083 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1084 vblanke = vsynce + vbackp;
1085 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1086 vblanks = vactive - vfrontp - 1;
1087 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1088 vblan2e = vactive + vsynce + vbackp;
1089 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1090 vactive = (vactive * 2) + 1;
2d1d898b
BS		 1091 }
1092
e225f446 1093 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1094 if (ret)
1095 return ret;
1096
de8268c5 1097 push = evo_wait(mast, 64);
438d99e3 1098 if (push) {
e225f446 1099 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 1100 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1101 evo_data(push, 0x00800000 | mode->clock);
1102 evo_data(push, (ilace == 2) ? 2 : 0);
1103 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1104 evo_data(push, 0x00000000);
1105 evo_data(push, (vactive << 16) | hactive);
1106 evo_data(push, ( vsynce << 16) | hsynce);
1107 evo_data(push, (vblanke << 16) | hblanke);
1108 evo_data(push, (vblanks << 16) | hblanks);
1109 evo_data(push, (vblan2e << 16) | vblan2s);
1110 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1111 evo_data(push, 0x00000000);
1112 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1113 evo_data(push, 0x00000311);
1114 evo_data(push, 0x00000100);
1115 } else {
1116 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1117 evo_data(push, 0x00000000);
1118 evo_data(push, (vactive << 16) | hactive);
1119 evo_data(push, ( vsynce << 16) | hsynce);
1120 evo_data(push, (vblanke << 16) | hblanke);
1121 evo_data(push, (vblanks << 16) | hblanks);
1122 evo_data(push, (vblan2e << 16) | vblan2s);
1123 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1124 evo_data(push, 0x00000000); /* ??? */
1125 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1126 evo_data(push, mode->clock * 1000);
1127 evo_data(push, 0x00200000); /* ??? */
1128 evo_data(push, mode->clock * 1000);
1129 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1130 evo_data(push, 0x00000311);
1131 evo_data(push, 0x00000100);
1132 }
1133
1134 evo_kick(push, mast);
438d99e3
BS		 1135 }
1136
1137 nv_connector = nouveau_crtc_connector_get(nv_crtc);
e225f446
BS		 1138 nv50_crtc_set_dither(nv_crtc, false);
1139 nv50_crtc_set_scale(nv_crtc, false);
1140 nv50_crtc_set_color_vibrance(nv_crtc, false);
1141 nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
438d99e3
BS		 1142 return 0;
1143}
1144
1145static int
e225f446 1146nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
438d99e3
BS		 1147 struct drm_framebuffer *old_fb)
1148{
77145f1c 1149 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
438d99e3
BS		 1150 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1151 int ret;
1152
84e2ad8b 1153 if (!crtc->fb) {
77145f1c 1154 NV_DEBUG(drm, "No FB bound\n");
84e2ad8b
BS		 1155 return 0;
1156 }
1157
e225f446 1158 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1159 if (ret)
1160 return ret;
1161
e225f446
BS		 1162 nv50_display_flip_stop(crtc);
1163 nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
1164 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
438d99e3
BS		 1165 return 0;
1166}
1167
1168static int
e225f446 1169nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
438d99e3
BS		 1170 struct drm_framebuffer *fb, int x, int y,
1171 enum mode_set_atomic state)
1172{
1173 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1174 nv50_display_flip_stop(crtc);
1175 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
438d99e3
BS		 1176 return 0;
1177}
1178
1179static void
e225f446 1180nv50_crtc_lut_load(struct drm_crtc *crtc)
438d99e3 1181{
e225f446 1182 struct nv50_disp *disp = nv50_disp(crtc->dev);
438d99e3
BS		 1183 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1184 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1185 int i;
1186
1187 for (i = 0; i < 256; i++) {
de8268c5
BS		 1188 u16 r = nv_crtc->lut.r[i] >> 2;
1189 u16 g = nv_crtc->lut.g[i] >> 2;
1190 u16 b = nv_crtc->lut.b[i] >> 2;
1191
1192 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1193 writew(r + 0x0000, lut + (i * 0x08) + 0);
1194 writew(g + 0x0000, lut + (i * 0x08) + 2);
1195 writew(b + 0x0000, lut + (i * 0x08) + 4);
1196 } else {
1197 writew(r + 0x6000, lut + (i * 0x20) + 0);
1198 writew(g + 0x6000, lut + (i * 0x20) + 2);
1199 writew(b + 0x6000, lut + (i * 0x20) + 4);
1200 }
438d99e3
BS		 1201 }
1202}
1203
8dda53fc
BS		 1204static void
1205nv50_crtc_disable(struct drm_crtc *crtc)
1206{
1207 struct nv50_head *head = nv50_head(crtc);
1208 if (head->image)
1209 nouveau_bo_unpin(head->image);
1210 nouveau_bo_ref(NULL, &head->image);
1211}
1212
438d99e3 1213static int
e225f446 1214nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
438d99e3
BS		 1215 uint32_t handle, uint32_t width, uint32_t height)
1216{
1217 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1218 struct drm_device *dev = crtc->dev;
1219 struct drm_gem_object *gem;
1220 struct nouveau_bo *nvbo;
1221 bool visible = (handle != 0);
1222 int i, ret = 0;
1223
1224 if (visible) {
1225 if (width != 64 || height != 64)
1226 return -EINVAL;
1227
1228 gem = drm_gem_object_lookup(dev, file_priv, handle);
1229 if (unlikely(!gem))
1230 return -ENOENT;
1231 nvbo = nouveau_gem_object(gem);
1232
1233 ret = nouveau_bo_map(nvbo);
1234 if (ret == 0) {
1235 for (i = 0; i < 64 * 64; i++) {
1236 u32 v = nouveau_bo_rd32(nvbo, i);
1237 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1238 }
1239 nouveau_bo_unmap(nvbo);
1240 }
1241
1242 drm_gem_object_unreference_unlocked(gem);
1243 }
1244
1245 if (visible != nv_crtc->cursor.visible) {
e225f446 1246 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
438d99e3
BS		 1247 nv_crtc->cursor.visible = visible;
1248 }
1249
1250 return ret;
1251}
1252
1253static int
e225f446 1254nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
438d99e3 1255{
e225f446
BS		 1256 struct nv50_curs *curs = nv50_curs(crtc);
1257 struct nv50_chan *chan = nv50_chan(curs);
b5a794b0
BS		 1258 nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1259 nv_wo32(chan->user, 0x0080, 0x00000000);
438d99e3
BS		 1260 return 0;
1261}
1262
1263static void
e225f446 1264nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
438d99e3
BS		 1265 uint32_t start, uint32_t size)
1266{
1267 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1268 u32 end = max(start + size, (u32)256);
1269 u32 i;
1270
1271 for (i = start; i < end; i++) {
1272 nv_crtc->lut.r[i] = r[i];
1273 nv_crtc->lut.g[i] = g[i];
1274 nv_crtc->lut.b[i] = b[i];
1275 }
1276
e225f446 1277 nv50_crtc_lut_load(crtc);
438d99e3
BS		 1278}
1279
1280static void
e225f446 1281nv50_crtc_destroy(struct drm_crtc *crtc)
438d99e3
BS		 1282{
1283 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1284 struct nv50_disp *disp = nv50_disp(crtc->dev);
1285 struct nv50_head *head = nv50_head(crtc);
8dda53fc 1286
e225f446
BS		 1287 nv50_dmac_destroy(disp->core, &head->ovly.base);
1288 nv50_pioc_destroy(disp->core, &head->oimm.base);
1289 nv50_dmac_destroy(disp->core, &head->sync.base);
1290 nv50_pioc_destroy(disp->core, &head->curs.base);
8dda53fc
BS		 1291
1292 /*XXX: this shouldn't be necessary, but the core doesn't call
1293 * disconnect() during the cleanup paths
1294 */
1295 if (head->image)
1296 nouveau_bo_unpin(head->image);
1297 nouveau_bo_ref(NULL, &head->image);
1298
438d99e3 1299 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
04c8c210
MS		 1300 if (nv_crtc->cursor.nvbo)
1301 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
438d99e3 1302 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
8dda53fc 1303
438d99e3 1304 nouveau_bo_unmap(nv_crtc->lut.nvbo);
04c8c210
MS		 1305 if (nv_crtc->lut.nvbo)
1306 nouveau_bo_unpin(nv_crtc->lut.nvbo);
438d99e3 1307 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
8dda53fc 1308
438d99e3
BS		 1309 drm_crtc_cleanup(crtc);
1310 kfree(crtc);
1311}
1312
e225f446
BS		 1313static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1314 .dpms = nv50_crtc_dpms,
1315 .prepare = nv50_crtc_prepare,
1316 .commit = nv50_crtc_commit,
1317 .mode_fixup = nv50_crtc_mode_fixup,
1318 .mode_set = nv50_crtc_mode_set,
1319 .mode_set_base = nv50_crtc_mode_set_base,
1320 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1321 .load_lut = nv50_crtc_lut_load,
8dda53fc 1322 .disable = nv50_crtc_disable,
438d99e3
BS		 1323};
1324
e225f446
BS		 1325static const struct drm_crtc_funcs nv50_crtc_func = {
1326 .cursor_set = nv50_crtc_cursor_set,
1327 .cursor_move = nv50_crtc_cursor_move,
1328 .gamma_set = nv50_crtc_gamma_set,
438d99e3 1329 .set_config = drm_crtc_helper_set_config,
e225f446 1330 .destroy = nv50_crtc_destroy,
3376ee37 1331 .page_flip = nouveau_crtc_page_flip,
438d99e3
BS		 1332};
1333
c20ab3e1 1334static void
e225f446 1335nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
c20ab3e1
BS		 1336{
1337}
1338
1339static void
e225f446 1340nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
c20ab3e1
BS		 1341{
1342}
1343
438d99e3 1344static int
e225f446 1345nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
438d99e3 1346{
e225f446
BS		 1347 struct nv50_disp *disp = nv50_disp(dev);
1348 struct nv50_head *head;
438d99e3
BS		 1349 struct drm_crtc *crtc;
1350 int ret, i;
1351
dd0e3d53
BS		 1352 head = kzalloc(sizeof(*head), GFP_KERNEL);
1353 if (!head)
438d99e3
BS		 1354 return -ENOMEM;
1355
dd0e3d53 1356 head->base.index = index;
e225f446
BS		 1357 head->base.set_dither = nv50_crtc_set_dither;
1358 head->base.set_scale = nv50_crtc_set_scale;
1359 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
f9887d09
BS		 1360 head->base.color_vibrance = 50;
1361 head->base.vibrant_hue = 0;
e225f446
BS		 1362 head->base.cursor.set_offset = nv50_cursor_set_offset;
1363 head->base.cursor.set_pos = nv50_cursor_set_pos;
438d99e3 1364 for (i = 0; i < 256; i++) {
dd0e3d53
BS		 1365 head->base.lut.r[i] = i << 8;
1366 head->base.lut.g[i] = i << 8;
1367 head->base.lut.b[i] = i << 8;
438d99e3
BS		 1368 }
1369
dd0e3d53 1370 crtc = &head->base.base;
e225f446
BS		 1371 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1372 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
438d99e3
BS		 1373 drm_mode_crtc_set_gamma_size(crtc, 256);
1374
b5a794b0
BS		 1375 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1376 0, 0x0000, NULL, &head->base.lut.nvbo);
1377 if (!ret) {
1378 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1379 if (!ret) {
b5a794b0 1380 ret = nouveau_bo_map(head->base.lut.nvbo);
04c8c210
MS		 1381 if (ret)
1382 nouveau_bo_unpin(head->base.lut.nvbo);
1383 }
b5a794b0
BS		 1384 if (ret)
1385 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1386 }
1387
1388 if (ret)
1389 goto out;
1390
e225f446 1391 nv50_crtc_lut_load(crtc);
b5a794b0
BS		 1392
1393 /* allocate cursor resources */
e225f446 1394 ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
b5a794b0
BS		 1395 &(struct nv50_display_curs_class) {
1396 .head = index,
1397 }, sizeof(struct nv50_display_curs_class),
1398 &head->curs.base);
1399 if (ret)
1400 goto out;
1401
438d99e3 1402 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
dd0e3d53 1403 0, 0x0000, NULL, &head->base.cursor.nvbo);
438d99e3 1404 if (!ret) {
dd0e3d53 1405 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1406 if (!ret) {
dd0e3d53 1407 ret = nouveau_bo_map(head->base.cursor.nvbo);
04c8c210
MS		 1408 if (ret)
1409 nouveau_bo_unpin(head->base.lut.nvbo);
1410 }
438d99e3 1411 if (ret)
dd0e3d53 1412 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
438d99e3
BS		 1413 }
1414
1415 if (ret)
1416 goto out;
1417
b5a794b0 1418 /* allocate page flip / sync resources */
e225f446 1419 ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
b5a794b0
BS		 1420 &(struct nv50_display_sync_class) {
1421 .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1422 .head = index,
1423 }, sizeof(struct nv50_display_sync_class),
1424 disp->sync->bo.offset, &head->sync.base);
1425 if (ret)
1426 goto out;
1427
9f9bdaaf
BS		 1428 head->sync.addr = EVO_FLIP_SEM0(index);
1429 head->sync.data = 0x00000000;
438d99e3 1430
b5a794b0 1431 /* allocate overlay resources */
e225f446 1432 ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
b5a794b0
BS		 1433 &(struct nv50_display_oimm_class) {
1434 .head = index,
1435 }, sizeof(struct nv50_display_oimm_class),
1436 &head->oimm.base);
438d99e3
BS		 1437 if (ret)
1438 goto out;
1439
e225f446 1440 ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
b5a794b0
BS		 1441 &(struct nv50_display_ovly_class) {
1442 .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1443 .head = index,
1444 }, sizeof(struct nv50_display_ovly_class),
1445 disp->sync->bo.offset, &head->ovly.base);
1446 if (ret)
1447 goto out;
438d99e3
BS		 1448
1449out:
1450 if (ret)
e225f446 1451 nv50_crtc_destroy(crtc);
438d99e3
BS		 1452 return ret;
1453}
1454
26f6d88b
BS		 1455/******************************************************************************
1456 * DAC
1457 *****************************************************************************/
8eaa9669 1458static void
e225f446 1459nv50_dac_dpms(struct drm_encoder *encoder, int mode)
8eaa9669
BS		 1460{
1461 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1462 struct nv50_disp *disp = nv50_disp(encoder->dev);
8eaa9669
BS		 1463 int or = nv_encoder->or;
1464 u32 dpms_ctrl;
1465
35b21d39 1466 dpms_ctrl = 0x00000000;
8eaa9669
BS		 1467 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1468 dpms_ctrl |= 0x00000001;
1469 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1470 dpms_ctrl |= 0x00000004;
1471
35b21d39 1472 nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
8eaa9669
BS		 1473}
1474
1475static bool
e225f446 1476nv50_dac_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1477 const struct drm_display_mode *mode,
8eaa9669
BS		 1478 struct drm_display_mode *adjusted_mode)
1479{
1480 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1481 struct nouveau_connector *nv_connector;
1482
1483 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1484 if (nv_connector && nv_connector->native_mode) {
1485 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1486 int id = adjusted_mode->base.id;
1487 *adjusted_mode = *nv_connector->native_mode;
1488 adjusted_mode->base.id = id;
1489 }
1490 }
1491
1492 return true;
1493}
1494
8eaa9669 1495static void
e225f446 1496nv50_dac_commit(struct drm_encoder *encoder)
8eaa9669
BS		 1497{
1498}
1499
1500static void
e225f446 1501nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
8eaa9669
BS		 1502 struct drm_display_mode *adjusted_mode)
1503{
e225f446 1504 struct nv50_mast *mast = nv50_mast(encoder->dev);
8eaa9669
BS		 1505 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1506 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
97b19b5c 1507 u32 *push;
8eaa9669 1508
e225f446 1509 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
8eaa9669 1510
97b19b5c 1511 push = evo_wait(mast, 8);
8eaa9669 1512 if (push) {
e225f446 1513 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
97b19b5c
BS		 1514 u32 syncs = 0x00000000;
1515
1516 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1517 syncs |= 0x00000001;
1518 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1519 syncs |= 0x00000002;
1520
1521 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1522 evo_data(push, 1 << nv_crtc->index);
1523 evo_data(push, syncs);
1524 } else {
1525 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1526 u32 syncs = 0x00000001;
1527
1528 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1529 syncs |= 0x00000008;
1530 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1531 syncs |= 0x00000010;
1532
1533 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1534 magic |= 0x00000001;
1535
1536 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1537 evo_data(push, syncs);
1538 evo_data(push, magic);
1539 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1540 evo_data(push, 1 << nv_crtc->index);
1541 }
1542
1543 evo_kick(push, mast);
8eaa9669
BS		 1544 }
1545
1546 nv_encoder->crtc = encoder->crtc;
1547}
1548
1549static void
e225f446 1550nv50_dac_disconnect(struct drm_encoder *encoder)
8eaa9669
BS		 1551{
1552 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1553 struct nv50_mast *mast = nv50_mast(encoder->dev);
97b19b5c 1554 const int or = nv_encoder->or;
8eaa9669
BS		 1555 u32 *push;
1556
1557 if (nv_encoder->crtc) {
e225f446 1558 nv50_crtc_prepare(nv_encoder->crtc);
8eaa9669 1559
97b19b5c 1560 push = evo_wait(mast, 4);
8eaa9669 1561 if (push) {
e225f446 1562 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
97b19b5c
BS		 1563 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1564 evo_data(push, 0x00000000);
1565 } else {
1566 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1567 evo_data(push, 0x00000000);
1568 }
97b19b5c 1569 evo_kick(push, mast);
8eaa9669 1570 }
8eaa9669 1571 }
97b19b5c
BS		 1572
1573 nv_encoder->crtc = NULL;
8eaa9669
BS		 1574}
1575
b6d8e7ec 1576static enum drm_connector_status
e225f446 1577nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
b6d8e7ec 1578{
e225f446 1579 struct nv50_disp *disp = nv50_disp(encoder->dev);
35b21d39 1580 int ret, or = nouveau_encoder(encoder)->or;
d40ee48a
BS		 1581 u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
1582 if (load == 0)
1583 load = 340;
b681993f 1584
35b21d39
BS		 1585 ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1586 if (ret || load != 7)
1587 return connector_status_disconnected;
b681993f 1588
35b21d39 1589 return connector_status_connected;
b6d8e7ec
BS		 1590}
1591
8eaa9669 1592static void
e225f446 1593nv50_dac_destroy(struct drm_encoder *encoder)
8eaa9669
BS		 1594{
1595 drm_encoder_cleanup(encoder);
1596 kfree(encoder);
1597}
1598
e225f446
BS		 1599static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1600 .dpms = nv50_dac_dpms,
1601 .mode_fixup = nv50_dac_mode_fixup,
1602 .prepare = nv50_dac_disconnect,
1603 .commit = nv50_dac_commit,
1604 .mode_set = nv50_dac_mode_set,
1605 .disable = nv50_dac_disconnect,
1606 .get_crtc = nv50_display_crtc_get,
1607 .detect = nv50_dac_detect
8eaa9669
BS		 1608};
1609
e225f446
BS		 1610static const struct drm_encoder_funcs nv50_dac_func = {
1611 .destroy = nv50_dac_destroy,
8eaa9669
BS		 1612};
1613
1614static int
e225f446 1615nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
8eaa9669 1616{
5ed50209
BS		 1617 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1618 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
8eaa9669
BS		 1619 struct nouveau_encoder *nv_encoder;
1620 struct drm_encoder *encoder;
5ed50209 1621 int type = DRM_MODE_ENCODER_DAC;
8eaa9669
BS		 1622
1623 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1624 if (!nv_encoder)
1625 return -ENOMEM;
1626 nv_encoder->dcb = dcbe;
1627 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 1628 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
8eaa9669
BS		 1629
1630 encoder = to_drm_encoder(nv_encoder);
1631 encoder->possible_crtcs = dcbe->heads;
1632 encoder->possible_clones = 0;
5ed50209 1633 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
e225f446 1634 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
8eaa9669
BS		 1635
1636 drm_mode_connector_attach_encoder(connector, encoder);
1637 return 0;
1638}
26f6d88b 1639
78951d22
BS		 1640/******************************************************************************
1641 * Audio
1642 *****************************************************************************/
1643static void
e225f446 1644nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22
BS		 1645{
1646 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1647 struct nouveau_connector *nv_connector;
e225f446 1648 struct nv50_disp *disp = nv50_disp(encoder->dev);
78951d22
BS		 1649
1650 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1651 if (!drm_detect_monitor_audio(nv_connector->edid))
1652 return;
1653
78951d22 1654 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
78951d22 1655
0a9e2b95
BS		 1656 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1657 nv_connector->base.eld,
1658 nv_connector->base.eld[2] * 4);
78951d22
BS		 1659}
1660
1661static void
e225f446 1662nv50_audio_disconnect(struct drm_encoder *encoder)
78951d22
BS		 1663{
1664 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1665 struct nv50_disp *disp = nv50_disp(encoder->dev);
78951d22 1666
0a9e2b95 1667 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
78951d22
BS		 1668}
1669
1670/******************************************************************************
1671 * HDMI
1672 *****************************************************************************/
1673static void
e225f446 1674nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22 1675{
64d9cc04
BS		 1676 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1677 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1678 struct nouveau_connector *nv_connector;
e225f446 1679 struct nv50_disp *disp = nv50_disp(encoder->dev);
1c30cd09 1680 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
64d9cc04
BS		 1681 u32 rekey = 56; /* binary driver, and tegra constant */
1682 u32 max_ac_packet;
1683
1684 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1685 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1686 return;
1687
1688 max_ac_packet = mode->htotal - mode->hdisplay;
1689 max_ac_packet -= rekey;
1690 max_ac_packet -= 18; /* constant from tegra */
1691 max_ac_packet /= 32;
1692
1c30cd09
BS		 1693 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1694 NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1695 (max_ac_packet << 16) | rekey);
091e40cd 1696
e225f446 1697 nv50_audio_mode_set(encoder, mode);
78951d22
BS		 1698}
1699
1700static void
e225f446 1701nv50_hdmi_disconnect(struct drm_encoder *encoder)
78951d22 1702{
64d9cc04
BS		 1703 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1704 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
e225f446 1705 struct nv50_disp *disp = nv50_disp(encoder->dev);
1c30cd09 1706 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
64d9cc04 1707
e225f446 1708 nv50_audio_disconnect(encoder);
64d9cc04 1709
1c30cd09 1710 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
78951d22
BS		 1711}
1712
26f6d88b
BS		 1713/******************************************************************************
1714 * SOR
1715 *****************************************************************************/
83fc083c 1716static void
e225f446 1717nv50_sor_dpms(struct drm_encoder *encoder, int mode)
83fc083c
BS		 1718{
1719 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1720 struct drm_device *dev = encoder->dev;
e225f446 1721 struct nv50_disp *disp = nv50_disp(dev);
83fc083c
BS		 1722 struct drm_encoder *partner;
1723 int or = nv_encoder->or;
83fc083c
BS		 1724
1725 nv_encoder->last_dpms = mode;
1726
1727 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1728 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1729
1730 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1731 continue;
1732
1733 if (nv_partner != nv_encoder &&
26cfa813 1734 nv_partner->dcb->or == nv_encoder->dcb->or) {
83fc083c
BS		 1735 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1736 return;
1737 break;
1738 }
1739 }
1740
74b66850 1741 nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
83fc083c
BS		 1742}
1743
1744static bool
e225f446 1745nv50_sor_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1746 const struct drm_display_mode *mode,
83fc083c
BS		 1747 struct drm_display_mode *adjusted_mode)
1748{
1749 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1750 struct nouveau_connector *nv_connector;
1751
1752 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1753 if (nv_connector && nv_connector->native_mode) {
1754 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1755 int id = adjusted_mode->base.id;
1756 *adjusted_mode = *nv_connector->native_mode;
1757 adjusted_mode->base.id = id;
1758 }
1759 }
1760
1761 return true;
1762}
1763
4cbb0f8d 1764static void
e225f446 1765nv50_sor_disconnect(struct drm_encoder *encoder)
4cbb0f8d
BS		 1766{
1767 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1768 struct nv50_mast *mast = nv50_mast(encoder->dev);
419e8dc0 1769 const int or = nv_encoder->or;
4cbb0f8d
BS		 1770 u32 *push;
1771
1772 if (nv_encoder->crtc) {
e225f446 1773 nv50_crtc_prepare(nv_encoder->crtc);
4cbb0f8d 1774
419e8dc0 1775 push = evo_wait(mast, 4);
4cbb0f8d 1776 if (push) {
e225f446 1777 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
419e8dc0
BS		 1778 evo_mthd(push, 0x0600 + (or * 0x40), 1);
1779 evo_data(push, 0x00000000);
1780 } else {
1781 evo_mthd(push, 0x0200 + (or * 0x20), 1);
1782 evo_data(push, 0x00000000);
1783 }
419e8dc0 1784 evo_kick(push, mast);
4cbb0f8d
BS		 1785 }
1786
e225f446 1787 nv50_hdmi_disconnect(encoder);
4cbb0f8d 1788 }
419e8dc0
BS		 1789
1790 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1791 nv_encoder->crtc = NULL;
4cbb0f8d
BS		 1792}
1793
83fc083c 1794static void
e225f446 1795nv50_sor_commit(struct drm_encoder *encoder)
83fc083c
BS		 1796{
1797}
1798
1799static void
e225f446 1800nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
3b6d83d1 1801 struct drm_display_mode *mode)
83fc083c 1802{
e225f446
BS		 1803 struct nv50_disp *disp = nv50_disp(encoder->dev);
1804 struct nv50_mast *mast = nv50_mast(encoder->dev);
78951d22 1805 struct drm_device *dev = encoder->dev;
77145f1c 1806 struct nouveau_drm *drm = nouveau_drm(dev);
83fc083c
BS		 1807 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1808 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3b6d83d1 1809 struct nouveau_connector *nv_connector;
77145f1c 1810 struct nvbios *bios = &drm->vbios;
419e8dc0
BS		 1811 u32 *push, lvds = 0;
1812 u8 owner = 1 << nv_crtc->index;
1813 u8 proto = 0xf;
1814 u8 depth = 0x0;
83fc083c 1815
3b6d83d1
BS		 1816 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1817 switch (nv_encoder->dcb->type) {
cb75d97e 1818 case DCB_OUTPUT_TMDS:
3b6d83d1
BS		 1819 if (nv_encoder->dcb->sorconf.link & 1) {
1820 if (mode->clock < 165000)
419e8dc0 1821 proto = 0x1;
3b6d83d1 1822 else
419e8dc0 1823 proto = 0x5;
3b6d83d1 1824 } else {
419e8dc0 1825 proto = 0x2;
3b6d83d1
BS		 1826 }
1827
e225f446 1828 nv50_hdmi_mode_set(encoder, mode);
3b6d83d1 1829 break;
cb75d97e 1830 case DCB_OUTPUT_LVDS:
419e8dc0
BS		 1831 proto = 0x0;
1832
3b6d83d1
BS		 1833 if (bios->fp_no_ddc) {
1834 if (bios->fp.dual_link)
419e8dc0 1835 lvds |= 0x0100;
3b6d83d1 1836 if (bios->fp.if_is_24bit)
419e8dc0 1837 lvds |= 0x0200;
3b6d83d1 1838 } else {
befb51e9 1839 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3b6d83d1 1840 if (((u8 *)nv_connector->edid)[121] == 2)
419e8dc0 1841 lvds |= 0x0100;
3b6d83d1
BS		 1842 } else
1843 if (mode->clock >= bios->fp.duallink_transition_clk) {
419e8dc0 1844 lvds |= 0x0100;
3b6d83d1 1845 }
83fc083c 1846
419e8dc0 1847 if (lvds & 0x0100) {
3b6d83d1 1848 if (bios->fp.strapless_is_24bit & 2)
419e8dc0 1849 lvds |= 0x0200;
3b6d83d1
BS		 1850 } else {
1851 if (bios->fp.strapless_is_24bit & 1)
419e8dc0 1852 lvds |= 0x0200;
3b6d83d1
BS		 1853 }
1854
1855 if (nv_connector->base.display_info.bpc == 8)
419e8dc0 1856 lvds |= 0x0200;
3b6d83d1 1857 }
4a230fa6 1858
419e8dc0 1859 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
3b6d83d1 1860 break;
cb75d97e 1861 case DCB_OUTPUT_DP:
3488c57b 1862 if (nv_connector->base.display_info.bpc == 6) {
6e83fda2 1863 nv_encoder->dp.datarate = mode->clock * 18 / 8;
419e8dc0 1864 depth = 0x2;
bf2c886a
BS		 1865 } else
1866 if (nv_connector->base.display_info.bpc == 8) {
6e83fda2 1867 nv_encoder->dp.datarate = mode->clock * 24 / 8;
419e8dc0 1868 depth = 0x5;
bf2c886a
BS		 1869 } else {
1870 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1871 depth = 0x6;
3488c57b 1872 }
6e83fda2
BS		 1873
1874 if (nv_encoder->dcb->sorconf.link & 1)
419e8dc0 1875 proto = 0x8;
6e83fda2 1876 else
419e8dc0 1877 proto = 0x9;
6e83fda2 1878 break;
3b6d83d1
BS		 1879 default:
1880 BUG_ON(1);
1881 break;
1882 }
ff8ff503 1883
e225f446 1884 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
83fc083c 1885
e225f446 1886 push = evo_wait(nv50_mast(dev), 8);
83fc083c 1887 if (push) {
e225f446 1888 if (nv50_vers(mast) < NVD0_DISP_CLASS) {
e2de1794
BS		 1889 u32 ctrl = (depth << 16) | (proto << 8) | owner;
1890 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1891 ctrl |= 0x00001000;
1892 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1893 ctrl |= 0x00002000;
419e8dc0 1894 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
e2de1794 1895 evo_data(push, ctrl);
419e8dc0
BS		 1896 } else {
1897 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1898 u32 syncs = 0x00000001;
1899
1900 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1901 syncs |= 0x00000008;
1902 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1903 syncs |= 0x00000010;
1904
1905 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1906 magic |= 0x00000001;
1907
1908 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1909 evo_data(push, syncs | (depth << 6));
1910 evo_data(push, magic);
1911 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
1912 evo_data(push, owner | (proto << 8));
1913 }
1914
1915 evo_kick(push, mast);
83fc083c
BS		 1916 }
1917
1918 nv_encoder->crtc = encoder->crtc;
1919}
1920
83fc083c 1921static void
e225f446 1922nv50_sor_destroy(struct drm_encoder *encoder)
83fc083c
BS		 1923{
1924 drm_encoder_cleanup(encoder);
1925 kfree(encoder);
1926}
1927
e225f446
BS		 1928static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1929 .dpms = nv50_sor_dpms,
1930 .mode_fixup = nv50_sor_mode_fixup,
5a885f0b 1931 .prepare = nv50_sor_disconnect,
e225f446
BS		 1932 .commit = nv50_sor_commit,
1933 .mode_set = nv50_sor_mode_set,
1934 .disable = nv50_sor_disconnect,
1935 .get_crtc = nv50_display_crtc_get,
83fc083c
BS		 1936};
1937
e225f446
BS		 1938static const struct drm_encoder_funcs nv50_sor_func = {
1939 .destroy = nv50_sor_destroy,
83fc083c
BS		 1940};
1941
1942static int
e225f446 1943nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
83fc083c 1944{
5ed50209
BS		 1945 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1946 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
83fc083c
BS		 1947 struct nouveau_encoder *nv_encoder;
1948 struct drm_encoder *encoder;
5ed50209
BS		 1949 int type;
1950
1951 switch (dcbe->type) {
1952 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1953 case DCB_OUTPUT_TMDS:
1954 case DCB_OUTPUT_DP:
1955 default:
1956 type = DRM_MODE_ENCODER_TMDS;
1957 break;
1958 }
83fc083c
BS		 1959
1960 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1961 if (!nv_encoder)
1962 return -ENOMEM;
1963 nv_encoder->dcb = dcbe;
1964 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 1965 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
83fc083c
BS		 1966 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1967
1968 encoder = to_drm_encoder(nv_encoder);
1969 encoder->possible_crtcs = dcbe->heads;
1970 encoder->possible_clones = 0;
5ed50209 1971 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
e225f446 1972 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
83fc083c
BS		 1973
1974 drm_mode_connector_attach_encoder(connector, encoder);
1975 return 0;
1976}
26f6d88b 1977
eb6313ad
BS		 1978/******************************************************************************
1979 * PIOR
1980 *****************************************************************************/
1981
1982static void
1983nv50_pior_dpms(struct drm_encoder *encoder, int mode)
1984{
1985 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1986 struct nv50_disp *disp = nv50_disp(encoder->dev);
1987 u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
1988 u32 ctrl = (mode == DRM_MODE_DPMS_ON);
1989 nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
1990}
1991
1992static bool
1993nv50_pior_mode_fixup(struct drm_encoder *encoder,
1994 const struct drm_display_mode *mode,
1995 struct drm_display_mode *adjusted_mode)
1996{
1997 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1998 struct nouveau_connector *nv_connector;
1999
2000 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2001 if (nv_connector && nv_connector->native_mode) {
2002 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2003 int id = adjusted_mode->base.id;
2004 *adjusted_mode = *nv_connector->native_mode;
2005 adjusted_mode->base.id = id;
2006 }
2007 }
2008
2009 adjusted_mode->clock *= 2;
2010 return true;
2011}
2012
2013static void
2014nv50_pior_commit(struct drm_encoder *encoder)
2015{
2016}
2017
2018static void
2019nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2020 struct drm_display_mode *adjusted_mode)
2021{
2022 struct nv50_mast *mast = nv50_mast(encoder->dev);
2023 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2024 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2025 struct nouveau_connector *nv_connector;
2026 u8 owner = 1 << nv_crtc->index;
2027 u8 proto, depth;
2028 u32 *push;
2029
2030 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2031 switch (nv_connector->base.display_info.bpc) {
2032 case 10: depth = 0x6; break;
2033 case 8: depth = 0x5; break;
2034 case 6: depth = 0x2; break;
2035 default: depth = 0x0; break;
2036 }
2037
2038 switch (nv_encoder->dcb->type) {
2039 case DCB_OUTPUT_TMDS:
2040 case DCB_OUTPUT_DP:
2041 proto = 0x0;
2042 break;
2043 default:
2044 BUG_ON(1);
2045 break;
2046 }
2047
2048 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2049
2050 push = evo_wait(mast, 8);
2051 if (push) {
2052 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2053 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2054 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2055 ctrl |= 0x00001000;
2056 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2057 ctrl |= 0x00002000;
2058 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2059 evo_data(push, ctrl);
2060 }
2061
2062 evo_kick(push, mast);
2063 }
2064
2065 nv_encoder->crtc = encoder->crtc;
2066}
2067
2068static void
2069nv50_pior_disconnect(struct drm_encoder *encoder)
2070{
2071 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2072 struct nv50_mast *mast = nv50_mast(encoder->dev);
2073 const int or = nv_encoder->or;
2074 u32 *push;
2075
2076 if (nv_encoder->crtc) {
2077 nv50_crtc_prepare(nv_encoder->crtc);
2078
2079 push = evo_wait(mast, 4);
2080 if (push) {
2081 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2082 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2083 evo_data(push, 0x00000000);
2084 }
eb6313ad
BS		 2085 evo_kick(push, mast);
2086 }
2087 }
2088
2089 nv_encoder->crtc = NULL;
2090}
2091
2092static void
2093nv50_pior_destroy(struct drm_encoder *encoder)
2094{
2095 drm_encoder_cleanup(encoder);
2096 kfree(encoder);
2097}
2098
2099static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2100 .dpms = nv50_pior_dpms,
2101 .mode_fixup = nv50_pior_mode_fixup,
2102 .prepare = nv50_pior_disconnect,
2103 .commit = nv50_pior_commit,
2104 .mode_set = nv50_pior_mode_set,
2105 .disable = nv50_pior_disconnect,
2106 .get_crtc = nv50_display_crtc_get,
2107};
2108
2109static const struct drm_encoder_funcs nv50_pior_func = {
2110 .destroy = nv50_pior_destroy,
2111};
2112
2113static int
2114nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2115{
2116 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2117 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
2118 struct nouveau_i2c_port *ddc = NULL;
2119 struct nouveau_encoder *nv_encoder;
2120 struct drm_encoder *encoder;
2121 int type;
2122
2123 switch (dcbe->type) {
2124 case DCB_OUTPUT_TMDS:
2125 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2126 type = DRM_MODE_ENCODER_TMDS;
2127 break;
2128 case DCB_OUTPUT_DP:
2129 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2130 type = DRM_MODE_ENCODER_TMDS;
2131 break;
2132 default:
2133 return -ENODEV;
2134 }
2135
2136 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2137 if (!nv_encoder)
2138 return -ENOMEM;
2139 nv_encoder->dcb = dcbe;
2140 nv_encoder->or = ffs(dcbe->or) - 1;
2141 nv_encoder->i2c = ddc;
2142
2143 encoder = to_drm_encoder(nv_encoder);
2144 encoder->possible_crtcs = dcbe->heads;
2145 encoder->possible_clones = 0;
2146 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2147 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2148
2149 drm_mode_connector_attach_encoder(connector, encoder);
2150 return 0;
2151}
2152
26f6d88b
BS		 2153/******************************************************************************
2154 * Init
2155 *****************************************************************************/
2a44e499 2156void
e225f446 2157nv50_display_fini(struct drm_device *dev)
26f6d88b 2158{
26f6d88b
BS		 2159}
2160
2161int
e225f446 2162nv50_display_init(struct drm_device *dev)
26f6d88b 2163{
9f9bdaaf
BS		 2164 struct nv50_disp *disp = nv50_disp(dev);
2165 struct drm_crtc *crtc;
2166 u32 *push;
2167
2168 push = evo_wait(nv50_mast(dev), 32);
2169 if (!push)
2170 return -EBUSY;
2171
2172 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2173 struct nv50_sync *sync = nv50_sync(crtc);
2174 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
bdb8c212 2175 }
efd272a7 2176
9f9bdaaf
BS		 2177 evo_mthd(push, 0x0088, 1);
2178 evo_data(push, NvEvoSync);
2179 evo_kick(push, nv50_mast(dev));
2180 return 0;
26f6d88b
BS		 2181}
2182
2183void
e225f446 2184nv50_display_destroy(struct drm_device *dev)
26f6d88b 2185{
e225f446 2186 struct nv50_disp *disp = nv50_disp(dev);
bdb8c212 2187
e225f446 2188 nv50_dmac_destroy(disp->core, &disp->mast.base);
26f6d88b 2189
816af2f2 2190 nouveau_bo_unmap(disp->sync);
04c8c210
MS		 2191 if (disp->sync)
2192 nouveau_bo_unpin(disp->sync);
816af2f2 2193 nouveau_bo_ref(NULL, &disp->sync);
51beb428 2194
77145f1c 2195 nouveau_display(dev)->priv = NULL;
26f6d88b
BS		 2196 kfree(disp);
2197}
2198
2199int
e225f446 2200nv50_display_create(struct drm_device *dev)
26f6d88b 2201{
b5a794b0 2202 static const u16 oclass[] = {
e5398b23 2203 NVF0_DISP_CLASS,
b5a794b0
BS		 2204 NVE0_DISP_CLASS,
2205 NVD0_DISP_CLASS,
63718a07
BS		 2206 NVA3_DISP_CLASS,
2207 NV94_DISP_CLASS,
2208 NVA0_DISP_CLASS,
2209 NV84_DISP_CLASS,
2210 NV50_DISP_CLASS,
b5a794b0 2211 };
77145f1c
BS		 2212 struct nouveau_device *device = nouveau_dev(dev);
2213 struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c 2214 struct dcb_table *dcb = &drm->vbios.dcb;
83fc083c 2215 struct drm_connector *connector, *tmp;
e225f446 2216 struct nv50_disp *disp;
cb75d97e 2217 struct dcb_output *dcbe;
7c5f6a87 2218 int crtcs, ret, i;
26f6d88b
BS		 2219
2220 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2221 if (!disp)
2222 return -ENOMEM;
77145f1c
BS		 2223
2224 nouveau_display(dev)->priv = disp;
e225f446
BS		 2225 nouveau_display(dev)->dtor = nv50_display_destroy;
2226 nouveau_display(dev)->init = nv50_display_init;
2227 nouveau_display(dev)->fini = nv50_display_fini;
26f6d88b 2228
b5a794b0
BS		 2229 /* small shared memory area we use for notifiers and semaphores */
2230 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2231 0, 0x0000, NULL, &disp->sync);
2232 if (!ret) {
2233 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
04c8c210 2234 if (!ret) {
b5a794b0 2235 ret = nouveau_bo_map(disp->sync);
04c8c210
MS		 2236 if (ret)
2237 nouveau_bo_unpin(disp->sync);
2238 }
b5a794b0
BS		 2239 if (ret)
2240 nouveau_bo_ref(NULL, &disp->sync);
2241 }
2242
2243 if (ret)
2244 goto out;
2245
2246 /* attempt to allocate a supported evo display class */
2247 ret = -ENODEV;
2248 for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
2249 ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
2250 0xd1500000, oclass[i], NULL, 0,
2251 &disp->core);
2252 }
2253
2254 if (ret)
2255 goto out;
2256
2257 /* allocate master evo channel */
e225f446 2258 ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
b5a794b0
BS		 2259 &(struct nv50_display_mast_class) {
2260 .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
2261 }, sizeof(struct nv50_display_mast_class),
2262 disp->sync->bo.offset, &disp->mast.base);
2263 if (ret)
2264 goto out;
2265
438d99e3 2266 /* create crtc objects to represent the hw heads */
63718a07
BS		 2267 if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2268 crtcs = nv_rd32(device, 0x022448);
2269 else
2270 crtcs = 2;
2271
7c5f6a87 2272 for (i = 0; i < crtcs; i++) {
e225f446 2273 ret = nv50_crtc_create(dev, disp->core, i);
438d99e3
BS		 2274 if (ret)
2275 goto out;
2276 }
2277
83fc083c
BS		 2278 /* create encoder/connector objects based on VBIOS DCB table */
2279 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2280 connector = nouveau_connector_create(dev, dcbe->connector);
2281 if (IS_ERR(connector))
2282 continue;
2283
eb6313ad
BS		 2284 if (dcbe->location == DCB_LOC_ON_CHIP) {
2285 switch (dcbe->type) {
2286 case DCB_OUTPUT_TMDS:
2287 case DCB_OUTPUT_LVDS:
2288 case DCB_OUTPUT_DP:
2289 ret = nv50_sor_create(connector, dcbe);
2290 break;
2291 case DCB_OUTPUT_ANALOG:
2292 ret = nv50_dac_create(connector, dcbe);
2293 break;
2294 default:
2295 ret = -ENODEV;
2296 break;
2297 }
2298 } else {
2299 ret = nv50_pior_create(connector, dcbe);
83fc083c
BS		 2300 }
2301
eb6313ad
BS		 2302 if (ret) {
2303 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2304 dcbe->location, dcbe->type,
2305 ffs(dcbe->or) - 1, ret);
94f54f53 2306 ret = 0;
83fc083c
BS		 2307 }
2308 }
2309
2310 /* cull any connectors we created that don't have an encoder */
2311 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2312 if (connector->encoder_ids[0])
2313 continue;
2314
77145f1c 2315 NV_WARN(drm, "%s has no encoders, removing\n",
83fc083c
BS		 2316 drm_get_connector_name(connector));
2317 connector->funcs->destroy(connector);
2318 }
2319
26f6d88b
BS		 2320out:
2321 if (ret)
e225f446 2322 nv50_display_destroy(dev);
26f6d88b
BS		 2323 return ret;
2324}
Linux 6.x block layer and io_uring tree(s)