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drm/nv50-/disp: audit and version DAC_LOAD method
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
56d237d2 1/*
26f6d88b
BS		 2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
51beb428 25#include <linux/dma-mapping.h>
83fc083c 26
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/drm_crtc_helper.h>
4874322e 29#include <drm/drm_dp_helper.h>
26f6d88b 30
fdb751ef
BS		 31#include <nvif/class.h>
32
77145f1c
BS		 33#include "nouveau_drm.h"
34#include "nouveau_dma.h"
35#include "nouveau_gem.h"
26f6d88b
BS		 36#include "nouveau_connector.h"
37#include "nouveau_encoder.h"
38#include "nouveau_crtc.h"
f589be88 39#include "nouveau_fence.h"
3a89cd02 40#include "nv50_display.h"
26f6d88b 41
8a46438a
BS		 42#define EVO_DMA_NR 9
43
bdb8c212 44#define EVO_MASTER (0x00)
a63a97eb 45#define EVO_FLIP(c) (0x01 + (c))
8a46438a
BS		 46#define EVO_OVLY(c) (0x05 + (c))
47#define EVO_OIMM(c) (0x09 + (c))
bdb8c212
BS		 48#define EVO_CURS(c) (0x0d + (c))
49
816af2f2
BS		 50/* offsets in shared sync bo of various structures */
51#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
9f9bdaaf
BS		 52#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
53#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
54#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
816af2f2 55
b5a794b0
BS		 56#define EVO_CORE_HANDLE (0xd1500000)
57#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
0ad72863 58#define EVO_CHAN_OCLASS(t,c) (((c)->oclass & 0xff00) | ((t) & 0x00ff))
b5a794b0
BS		 59#define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
60 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
61
62/******************************************************************************
63 * EVO channel
64 *****************************************************************************/
65
e225f446 66struct nv50_chan {
0ad72863 67 struct nvif_object user;
b5a794b0
BS		 68};
69
70static int
410f3ec6 71nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
e225f446 72 void *data, u32 size, struct nv50_chan *chan)
b5a794b0 73{
410f3ec6
BS		 74 while (oclass[0]) {
75 int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head,
76 oclass[0], data, size,
77 &chan->user);
78 if (oclass++, ret == 0)
79 return ret;
80 }
81 return -ENOSYS;
b5a794b0
BS		 82}
83
84static void
0ad72863 85nv50_chan_destroy(struct nv50_chan *chan)
b5a794b0 86{
0ad72863 87 nvif_object_fini(&chan->user);
b5a794b0
BS		 88}
89
90/******************************************************************************
91 * PIO EVO channel
92 *****************************************************************************/
93
e225f446
BS		 94struct nv50_pioc {
95 struct nv50_chan base;
b5a794b0
BS		 96};
97
98static void
0ad72863 99nv50_pioc_destroy(struct nv50_pioc *pioc)
b5a794b0 100{
0ad72863 101 nv50_chan_destroy(&pioc->base);
b5a794b0
BS		 102}
103
104static int
410f3ec6 105nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
e225f446 106 void *data, u32 size, struct nv50_pioc *pioc)
b5a794b0 107{
410f3ec6
BS		 108 return nv50_chan_create(disp, oclass, head, data, size, &pioc->base);
109}
110
111/******************************************************************************
112 * Cursor Immediate
113 *****************************************************************************/
114
115struct nv50_curs {
116 struct nv50_pioc base;
117};
118
119static int
120nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
121{
122 struct nv50_display_curs_class args = {
123 .head = head,
124 };
125 static const u32 oclass[] = {
126 GM107_DISP_CURS_CLASS,
127 NVF0_DISP_CURS_CLASS,
128 NVE0_DISP_CURS_CLASS,
129 NVD0_DISP_CURS_CLASS,
130 NVA3_DISP_CURS_CLASS,
131 NV94_DISP_CURS_CLASS,
132 NVA0_DISP_CURS_CLASS,
133 NV84_DISP_CURS_CLASS,
134 NV50_DISP_CURS_CLASS,
135 0
136 };
137
138 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
139 &curs->base);
140}
141
142/******************************************************************************
143 * Overlay Immediate
144 *****************************************************************************/
145
146struct nv50_oimm {
147 struct nv50_pioc base;
148};
149
150static int
151nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
152{
153 struct nv50_display_oimm_class args = {
154 .head = head,
155 };
156 static const u32 oclass[] = {
157 GM107_DISP_OIMM_CLASS,
158 NVF0_DISP_OIMM_CLASS,
159 NVE0_DISP_OIMM_CLASS,
160 NVD0_DISP_OIMM_CLASS,
161 NVA3_DISP_OIMM_CLASS,
162 NV94_DISP_OIMM_CLASS,
163 NVA0_DISP_OIMM_CLASS,
164 NV84_DISP_OIMM_CLASS,
165 NV50_DISP_OIMM_CLASS,
166 0
167 };
168
169 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
170 &oimm->base);
b5a794b0
BS		 171}
172
173/******************************************************************************
174 * DMA EVO channel
175 *****************************************************************************/
176
e225f446
BS		 177struct nv50_dmac {
178 struct nv50_chan base;
3376ee37
BS		 179 dma_addr_t handle;
180 u32 *ptr;
59ad1465 181
0ad72863
BS		 182 struct nvif_object sync;
183 struct nvif_object vram;
184
59ad1465
DV		 185 /* Protects against concurrent pushbuf access to this channel, lock is
186 * grabbed by evo_wait (if the pushbuf reservation is successful) and
187 * dropped again by evo_kick. */
188 struct mutex lock;
b5a794b0
BS		 189};
190
191static void
0ad72863 192nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
b5a794b0 193{
0ad72863
BS		 194 nvif_object_fini(&dmac->vram);
195 nvif_object_fini(&dmac->sync);
196
197 nv50_chan_destroy(&dmac->base);
198
b5a794b0 199 if (dmac->ptr) {
0ad72863 200 struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
b5a794b0
BS		 201 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
202 }
b5a794b0
BS		 203}
204
47057302 205static int
410f3ec6 206nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
47057302 207 void *data, u32 size, u64 syncbuf,
e225f446 208 struct nv50_dmac *dmac)
47057302 209{
0ad72863
BS		 210 struct nouveau_fb *pfb = nvkm_fb(nvif_device(disp));
211 struct nvif_object pushbuf;
212 u32 handle = *(u32 *)data;
47057302
BS		 213 int ret;
214
59ad1465
DV		 215 mutex_init(&dmac->lock);
216
0ad72863
BS		 217 dmac->ptr = pci_alloc_consistent(nvkm_device(nvif_device(disp))->pdev,
218 PAGE_SIZE, &dmac->handle);
47057302
BS		 219 if (!dmac->ptr)
220 return -ENOMEM;
221
0ad72863 222 ret = nvif_object_init(nvif_object(nvif_device(disp)), NULL, handle,
4acfd707
BS		 223 NV_DMA_FROM_MEMORY,
224 &(struct nv_dma_v0) {
225 .target = NV_DMA_V0_TARGET_PCI_US,
226 .access = NV_DMA_V0_ACCESS_RD,
47057302
BS		 227 .start = dmac->handle + 0x0000,
228 .limit = dmac->handle + 0x0fff,
4acfd707 229 }, sizeof(struct nv_dma_v0), &pushbuf);
b5a794b0 230 if (ret)
47057302 231 return ret;
b5a794b0 232
410f3ec6 233 ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base);
0ad72863 234 nvif_object_fini(&pushbuf);
47057302
BS		 235 if (ret)
236 return ret;
237
f45f55c4 238 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000,
4acfd707
BS		 239 NV_DMA_IN_MEMORY,
240 &(struct nv_dma_v0) {
241 .target = NV_DMA_V0_TARGET_VRAM,
242 .access = NV_DMA_V0_ACCESS_RDWR,
47057302
BS		 243 .start = syncbuf + 0x0000,
244 .limit = syncbuf + 0x0fff,
4acfd707 245 }, sizeof(struct nv_dma_v0),
0ad72863 246 &dmac->sync);
47057302
BS		 247 if (ret)
248 return ret;
249
f45f55c4 250 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001,
4acfd707
BS		 251 NV_DMA_IN_MEMORY,
252 &(struct nv_dma_v0) {
253 .target = NV_DMA_V0_TARGET_VRAM,
254 .access = NV_DMA_V0_ACCESS_RDWR,
b5a794b0 255 .start = 0,
dceef5d8 256 .limit = pfb->ram->size - 1,
4acfd707 257 }, sizeof(struct nv_dma_v0),
0ad72863 258 &dmac->vram);
b5a794b0 259 if (ret)
47057302
BS		 260 return ret;
261
b5a794b0
BS		 262 return ret;
263}
264
410f3ec6
BS		 265/******************************************************************************
266 * Core
267 *****************************************************************************/
268
e225f446
BS		 269struct nv50_mast {
270 struct nv50_dmac base;
b5a794b0
BS		 271};
272
410f3ec6
BS		 273static int
274nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
275{
276 struct nv50_display_mast_class args = {
277 .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
278 };
279 static const u32 oclass[] = {
280 GM107_DISP_MAST_CLASS,
281 NVF0_DISP_MAST_CLASS,
282 NVE0_DISP_MAST_CLASS,
283 NVD0_DISP_MAST_CLASS,
284 NVA3_DISP_MAST_CLASS,
285 NV94_DISP_MAST_CLASS,
286 NVA0_DISP_MAST_CLASS,
287 NV84_DISP_MAST_CLASS,
288 NV50_DISP_MAST_CLASS,
289 0
290 };
291
292 return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf,
293 &core->base);
294}
295
296/******************************************************************************
297 * Base
298 *****************************************************************************/
b5a794b0 299
e225f446
BS		 300struct nv50_sync {
301 struct nv50_dmac base;
9f9bdaaf
BS		 302 u32 addr;
303 u32 data;
3376ee37
BS		 304};
305
410f3ec6
BS		 306static int
307nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
308 struct nv50_sync *base)
309{
310 struct nv50_display_sync_class args = {
311 .pushbuf = EVO_PUSH_HANDLE(SYNC, head),
312 .head = head,
313 };
314 static const u32 oclass[] = {
315 GM107_DISP_SYNC_CLASS,
316 NVF0_DISP_SYNC_CLASS,
317 NVE0_DISP_SYNC_CLASS,
318 NVD0_DISP_SYNC_CLASS,
319 NVA3_DISP_SYNC_CLASS,
320 NV94_DISP_SYNC_CLASS,
321 NVA0_DISP_SYNC_CLASS,
322 NV84_DISP_SYNC_CLASS,
323 NV50_DISP_SYNC_CLASS,
324 0
325 };
326
327 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
328 syncbuf, &base->base);
329}
330
331/******************************************************************************
332 * Overlay
333 *****************************************************************************/
334
e225f446
BS		 335struct nv50_ovly {
336 struct nv50_dmac base;
b5a794b0 337};
f20ce962 338
410f3ec6
BS		 339static int
340nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
341 struct nv50_ovly *ovly)
342{
343 struct nv50_display_ovly_class args = {
344 .pushbuf = EVO_PUSH_HANDLE(OVLY, head),
345 .head = head,
346 };
347 static const u32 oclass[] = {
348 GM107_DISP_OVLY_CLASS,
349 NVF0_DISP_OVLY_CLASS,
350 NVE0_DISP_OVLY_CLASS,
351 NVD0_DISP_OVLY_CLASS,
352 NVA3_DISP_OVLY_CLASS,
353 NV94_DISP_OVLY_CLASS,
354 NVA0_DISP_OVLY_CLASS,
355 NV84_DISP_OVLY_CLASS,
356 NV50_DISP_OVLY_CLASS,
357 0
358 };
359
360 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
361 syncbuf, &ovly->base);
362}
26f6d88b 363
e225f446 364struct nv50_head {
dd0e3d53 365 struct nouveau_crtc base;
8dda53fc 366 struct nouveau_bo *image;
e225f446
BS		 367 struct nv50_curs curs;
368 struct nv50_sync sync;
369 struct nv50_ovly ovly;
370 struct nv50_oimm oimm;
b5a794b0
BS		 371};
372
e225f446
BS		 373#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
374#define nv50_curs(c) (&nv50_head(c)->curs)
375#define nv50_sync(c) (&nv50_head(c)->sync)
376#define nv50_ovly(c) (&nv50_head(c)->ovly)
377#define nv50_oimm(c) (&nv50_head(c)->oimm)
378#define nv50_chan(c) (&(c)->base.base)
0ad72863
BS		 379#define nv50_vers(c) nv50_chan(c)->user.oclass
380
381struct nv50_fbdma {
382 struct list_head head;
383 struct nvif_object core;
384 struct nvif_object base[4];
385};
b5a794b0 386
e225f446 387struct nv50_disp {
0ad72863 388 struct nvif_object *disp;
e225f446 389 struct nv50_mast mast;
b5a794b0 390
8a423647 391 struct list_head fbdma;
b5a794b0
BS		 392
393 struct nouveau_bo *sync;
dd0e3d53
BS		 394};
395
e225f446
BS		 396static struct nv50_disp *
397nv50_disp(struct drm_device *dev)
26f6d88b 398{
77145f1c 399 return nouveau_display(dev)->priv;
26f6d88b
BS		 400}
401
e225f446 402#define nv50_mast(d) (&nv50_disp(d)->mast)
b5a794b0 403
bdb8c212 404static struct drm_crtc *
e225f446 405nv50_display_crtc_get(struct drm_encoder *encoder)
bdb8c212
BS		 406{
407 return nouveau_encoder(encoder)->crtc;
408}
409
410/******************************************************************************
411 * EVO channel helpers
412 *****************************************************************************/
51beb428 413static u32 *
b5a794b0 414evo_wait(void *evoc, int nr)
51beb428 415{
e225f446 416 struct nv50_dmac *dmac = evoc;
0ad72863 417 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
51beb428 418
59ad1465 419 mutex_lock(&dmac->lock);
de8268c5 420 if (put + nr >= (PAGE_SIZE / 4) - 8) {
b5a794b0 421 dmac->ptr[put] = 0x20000000;
51beb428 422
0ad72863
BS		 423 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
424 if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
59ad1465 425 mutex_unlock(&dmac->lock);
0ad72863 426 nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
51beb428
BS		 427 return NULL;
428 }
429
430 put = 0;
431 }
432
b5a794b0 433 return dmac->ptr + put;
51beb428
BS		 434}
435
436static void
b5a794b0 437evo_kick(u32 *push, void *evoc)
51beb428 438{
e225f446 439 struct nv50_dmac *dmac = evoc;
0ad72863 440 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
59ad1465 441 mutex_unlock(&dmac->lock);
51beb428
BS		 442}
443
444#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
445#define evo_data(p,d) *((p)++) = (d)
446
3376ee37
BS		 447static bool
448evo_sync_wait(void *data)
449{
5cc027f6
BS		 450 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
451 return true;
452 usleep_range(1, 2);
453 return false;
3376ee37
BS		 454}
455
456static int
b5a794b0 457evo_sync(struct drm_device *dev)
3376ee37 458{
967e7bde 459 struct nvif_device *device = &nouveau_drm(dev)->device;
e225f446
BS		 460 struct nv50_disp *disp = nv50_disp(dev);
461 struct nv50_mast *mast = nv50_mast(dev);
b5a794b0 462 u32 *push = evo_wait(mast, 8);
3376ee37 463 if (push) {
816af2f2 464 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
3376ee37 465 evo_mthd(push, 0x0084, 1);
816af2f2 466 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
3376ee37
BS		 467 evo_mthd(push, 0x0080, 2);
468 evo_data(push, 0x00000000);
469 evo_data(push, 0x00000000);
b5a794b0 470 evo_kick(push, mast);
967e7bde 471 if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
3376ee37
BS		 472 return 0;
473 }
474
475 return -EBUSY;
476}
477
478/******************************************************************************
a63a97eb 479 * Page flipping channel
3376ee37
BS		 480 *****************************************************************************/
481struct nouveau_bo *
e225f446 482nv50_display_crtc_sema(struct drm_device *dev, int crtc)
3376ee37 483{
e225f446 484 return nv50_disp(dev)->sync;
3376ee37
BS		 485}
486
9f9bdaaf
BS		 487struct nv50_display_flip {
488 struct nv50_disp *disp;
489 struct nv50_sync *chan;
490};
491
492static bool
493nv50_display_flip_wait(void *data)
494{
495 struct nv50_display_flip *flip = data;
496 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
b1ea3e6e 497 flip->chan->data)
9f9bdaaf
BS		 498 return true;
499 usleep_range(1, 2);
500 return false;
501}
502
3376ee37 503void
e225f446 504nv50_display_flip_stop(struct drm_crtc *crtc)
3376ee37 505{
967e7bde 506 struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
9f9bdaaf
BS		 507 struct nv50_display_flip flip = {
508 .disp = nv50_disp(crtc->dev),
509 .chan = nv50_sync(crtc),
510 };
3376ee37
BS		 511 u32 *push;
512
9f9bdaaf 513 push = evo_wait(flip.chan, 8);
3376ee37
BS		 514 if (push) {
515 evo_mthd(push, 0x0084, 1);
516 evo_data(push, 0x00000000);
517 evo_mthd(push, 0x0094, 1);
518 evo_data(push, 0x00000000);
519 evo_mthd(push, 0x00c0, 1);
520 evo_data(push, 0x00000000);
521 evo_mthd(push, 0x0080, 1);
522 evo_data(push, 0x00000000);
9f9bdaaf 523 evo_kick(push, flip.chan);
3376ee37 524 }
9f9bdaaf 525
967e7bde 526 nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
3376ee37
BS		 527}
528
529int
e225f446 530nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3376ee37
BS		 531 struct nouveau_channel *chan, u32 swap_interval)
532{
533 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
3376ee37 534 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
8dda53fc 535 struct nv50_head *head = nv50_head(crtc);
e225f446 536 struct nv50_sync *sync = nv50_sync(crtc);
3376ee37 537 u32 *push;
8dda53fc 538 int ret;
3376ee37
BS		 539
540 swap_interval <<= 4;
541 if (swap_interval == 0)
542 swap_interval |= 0x100;
f60b6e7a
BS		 543 if (chan == NULL)
544 evo_sync(crtc->dev);
3376ee37 545
b5a794b0 546 push = evo_wait(sync, 128);
3376ee37
BS		 547 if (unlikely(push == NULL))
548 return -EBUSY;
549
bbf8906b 550 if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) {
9f9bdaaf
BS		 551 ret = RING_SPACE(chan, 8);
552 if (ret)
553 return ret;
554
555 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
8dda53fc 556 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
9f9bdaaf
BS		 557 OUT_RING (chan, sync->addr ^ 0x10);
558 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
559 OUT_RING (chan, sync->data + 1);
560 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
561 OUT_RING (chan, sync->addr);
562 OUT_RING (chan, sync->data);
563 } else
bbf8906b 564 if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) {
8dda53fc 565 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 566 ret = RING_SPACE(chan, 12);
567 if (ret)
568 return ret;
569
570 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
0ad72863 571 OUT_RING (chan, chan->vram.handle);
9f9bdaaf
BS		 572 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
573 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
574 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
575 OUT_RING (chan, sync->data + 1);
576 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
577 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
578 OUT_RING (chan, upper_32_bits(addr));
579 OUT_RING (chan, lower_32_bits(addr));
580 OUT_RING (chan, sync->data);
581 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
582 } else
583 if (chan) {
8dda53fc 584 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 585 ret = RING_SPACE(chan, 10);
586 if (ret)
587 return ret;
588
589 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
590 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
591 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
592 OUT_RING (chan, sync->data + 1);
593 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
594 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
595 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
596 OUT_RING (chan, upper_32_bits(addr));
597 OUT_RING (chan, lower_32_bits(addr));
598 OUT_RING (chan, sync->data);
599 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
600 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
601 }
35bcf5d5 602
9f9bdaaf
BS		 603 if (chan) {
604 sync->addr ^= 0x10;
605 sync->data++;
3376ee37 606 FIRE_RING (chan);
3376ee37
BS		 607 }
608
609 /* queue the flip */
610 evo_mthd(push, 0x0100, 1);
611 evo_data(push, 0xfffe0000);
612 evo_mthd(push, 0x0084, 1);
613 evo_data(push, swap_interval);
614 if (!(swap_interval & 0x00000100)) {
615 evo_mthd(push, 0x00e0, 1);
616 evo_data(push, 0x40000000);
617 }
618 evo_mthd(push, 0x0088, 4);
9f9bdaaf
BS		 619 evo_data(push, sync->addr);
620 evo_data(push, sync->data++);
621 evo_data(push, sync->data);
f45f55c4 622 evo_data(push, sync->base.sync.handle);
3376ee37
BS		 623 evo_mthd(push, 0x00a0, 2);
624 evo_data(push, 0x00000000);
625 evo_data(push, 0x00000000);
626 evo_mthd(push, 0x00c0, 1);
8a423647 627 evo_data(push, nv_fb->r_handle);
3376ee37
BS		 628 evo_mthd(push, 0x0110, 2);
629 evo_data(push, 0x00000000);
630 evo_data(push, 0x00000000);
e225f446 631 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
ed5085a5
BS		 632 evo_mthd(push, 0x0800, 5);
633 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
634 evo_data(push, 0);
635 evo_data(push, (fb->height << 16) | fb->width);
636 evo_data(push, nv_fb->r_pitch);
637 evo_data(push, nv_fb->r_format);
638 } else {
639 evo_mthd(push, 0x0400, 5);
640 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
641 evo_data(push, 0);
642 evo_data(push, (fb->height << 16) | fb->width);
643 evo_data(push, nv_fb->r_pitch);
644 evo_data(push, nv_fb->r_format);
645 }
3376ee37
BS		 646 evo_mthd(push, 0x0080, 1);
647 evo_data(push, 0x00000000);
b5a794b0 648 evo_kick(push, sync);
8dda53fc
BS		 649
650 nouveau_bo_ref(nv_fb->nvbo, &head->image);
3376ee37
BS		 651 return 0;
652}
653
438d99e3
BS		 654/******************************************************************************
655 * CRTC
656 *****************************************************************************/
657static int
e225f446 658nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 659{
e225f446 660 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de691855
BS		 661 struct nouveau_connector *nv_connector;
662 struct drm_connector *connector;
663 u32 *push, mode = 0x00;
438d99e3 664
488ff207 665 nv_connector = nouveau_crtc_connector_get(nv_crtc);
de691855
BS		 666 connector = &nv_connector->base;
667 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
f4510a27 668 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
de691855
BS		 669 mode = DITHERING_MODE_DYNAMIC2X2;
670 } else {
671 mode = nv_connector->dithering_mode;
672 }
673
674 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
675 if (connector->display_info.bpc >= 8)
676 mode |= DITHERING_DEPTH_8BPC;
677 } else {
678 mode |= nv_connector->dithering_depth;
438d99e3
BS		 679 }
680
de8268c5 681 push = evo_wait(mast, 4);
438d99e3 682 if (push) {
e225f446 683 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 684 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
685 evo_data(push, mode);
686 } else
e225f446 687 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
de8268c5
BS		 688 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
689 evo_data(push, mode);
690 } else {
691 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
692 evo_data(push, mode);
693 }
694
438d99e3
BS		 695 if (update) {
696 evo_mthd(push, 0x0080, 1);
697 evo_data(push, 0x00000000);
698 }
de8268c5 699 evo_kick(push, mast);
438d99e3
BS		 700 }
701
702 return 0;
703}
704
705static int
e225f446 706nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 707{
e225f446 708 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
92854622 709 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
3376ee37 710 struct drm_crtc *crtc = &nv_crtc->base;
f3fdc52d 711 struct nouveau_connector *nv_connector;
92854622
BS		 712 int mode = DRM_MODE_SCALE_NONE;
713 u32 oX, oY, *push;
f3fdc52d 714
92854622
BS		 715 /* start off at the resolution we programmed the crtc for, this
716 * effectively handles NONE/FULL scaling
717 */
f3fdc52d 718 nv_connector = nouveau_crtc_connector_get(nv_crtc);
92854622
BS		 719 if (nv_connector && nv_connector->native_mode)
720 mode = nv_connector->scaling_mode;
721
722 if (mode != DRM_MODE_SCALE_NONE)
723 omode = nv_connector->native_mode;
724 else
725 omode = umode;
726
727 oX = omode->hdisplay;
728 oY = omode->vdisplay;
729 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
730 oY *= 2;
731
732 /* add overscan compensation if necessary, will keep the aspect
733 * ratio the same as the backend mode unless overridden by the
734 * user setting both hborder and vborder properties.
735 */
736 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
737 (nv_connector->underscan == UNDERSCAN_AUTO &&
738 nv_connector->edid &&
739 drm_detect_hdmi_monitor(nv_connector->edid)))) {
740 u32 bX = nv_connector->underscan_hborder;
741 u32 bY = nv_connector->underscan_vborder;
742 u32 aspect = (oY << 19) / oX;
743
744 if (bX) {
745 oX -= (bX * 2);
746 if (bY) oY -= (bY * 2);
747 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
748 } else {
749 oX -= (oX >> 4) + 32;
750 if (bY) oY -= (bY * 2);
751 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
752 }
753 }
754
755 /* handle CENTER/ASPECT scaling, taking into account the areas
756 * removed already for overscan compensation
757 */
758 switch (mode) {
759 case DRM_MODE_SCALE_CENTER:
760 oX = min((u32)umode->hdisplay, oX);
761 oY = min((u32)umode->vdisplay, oY);
762 /* fall-through */
763 case DRM_MODE_SCALE_ASPECT:
764 if (oY < oX) {
765 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
766 oX = ((oY * aspect) + (aspect / 2)) >> 19;
767 } else {
768 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
769 oY = ((oX * aspect) + (aspect / 2)) >> 19;
f3fdc52d 770 }
92854622
BS		 771 break;
772 default:
773 break;
f3fdc52d 774 }
438d99e3 775
de8268c5 776 push = evo_wait(mast, 8);
438d99e3 777 if (push) {
e225f446 778 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 779 /*XXX: SCALE_CTRL_ACTIVE??? */
780 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
781 evo_data(push, (oY << 16) | oX);
782 evo_data(push, (oY << 16) | oX);
783 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
784 evo_data(push, 0x00000000);
785 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
786 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
787 } else {
788 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
789 evo_data(push, (oY << 16) | oX);
790 evo_data(push, (oY << 16) | oX);
791 evo_data(push, (oY << 16) | oX);
792 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
793 evo_data(push, 0x00000000);
794 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
795 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
796 }
797
798 evo_kick(push, mast);
799
438d99e3 800 if (update) {
e225f446 801 nv50_display_flip_stop(crtc);
f4510a27
MR		 802 nv50_display_flip_next(crtc, crtc->primary->fb,
803 NULL, 1);
438d99e3 804 }
438d99e3
BS		 805 }
806
807 return 0;
808}
809
f9887d09 810static int
e225f446 811nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
f9887d09 812{
e225f446 813 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
f9887d09
BS		 814 u32 *push, hue, vib;
815 int adj;
816
817 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
818 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
819 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
820
821 push = evo_wait(mast, 16);
822 if (push) {
e225f446 823 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
f9887d09
BS		 824 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
825 evo_data(push, (hue << 20) | (vib << 8));
826 } else {
827 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
828 evo_data(push, (hue << 20) | (vib << 8));
829 }
830
831 if (update) {
832 evo_mthd(push, 0x0080, 1);
833 evo_data(push, 0x00000000);
834 }
835 evo_kick(push, mast);
836 }
837
838 return 0;
839}
840
438d99e3 841static int
e225f446 842nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
438d99e3
BS		 843 int x, int y, bool update)
844{
845 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
e225f446 846 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
438d99e3
BS		 847 u32 *push;
848
de8268c5 849 push = evo_wait(mast, 16);
438d99e3 850 if (push) {
e225f446 851 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 852 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
853 evo_data(push, nvfb->nvbo->bo.offset >> 8);
854 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
855 evo_data(push, (fb->height << 16) | fb->width);
856 evo_data(push, nvfb->r_pitch);
857 evo_data(push, nvfb->r_format);
858 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
859 evo_data(push, (y << 16) | x);
e225f446 860 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
de8268c5 861 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 862 evo_data(push, nvfb->r_handle);
de8268c5
BS		 863 }
864 } else {
865 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
866 evo_data(push, nvfb->nvbo->bo.offset >> 8);
867 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
868 evo_data(push, (fb->height << 16) | fb->width);
869 evo_data(push, nvfb->r_pitch);
870 evo_data(push, nvfb->r_format);
8a423647 871 evo_data(push, nvfb->r_handle);
de8268c5
BS		 872 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
873 evo_data(push, (y << 16) | x);
874 }
875
a46232ee
BS		 876 if (update) {
877 evo_mthd(push, 0x0080, 1);
878 evo_data(push, 0x00000000);
879 }
de8268c5 880 evo_kick(push, mast);
438d99e3
BS		 881 }
882
8a423647 883 nv_crtc->fb.handle = nvfb->r_handle;
438d99e3
BS		 884 return 0;
885}
886
887static void
e225f446 888nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
438d99e3 889{
e225f446 890 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5 891 u32 *push = evo_wait(mast, 16);
438d99e3 892 if (push) {
e225f446 893 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5
BS		 894 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
895 evo_data(push, 0x85000000);
896 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
897 } else
e225f446 898 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 899 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
900 evo_data(push, 0x85000000);
901 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
902 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
f45f55c4 903 evo_data(push, mast->base.vram.handle);
de8268c5 904 } else {
438d99e3
BS		 905 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
906 evo_data(push, 0x85000000);
907 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
908 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
f45f55c4 909 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 910 }
911 evo_kick(push, mast);
912 }
913}
914
915static void
e225f446 916nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
de8268c5 917{
e225f446 918 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 919 u32 *push = evo_wait(mast, 16);
920 if (push) {
e225f446 921 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5
BS		 922 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
923 evo_data(push, 0x05000000);
924 } else
e225f446 925 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 926 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
927 evo_data(push, 0x05000000);
928 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
929 evo_data(push, 0x00000000);
438d99e3
BS		 930 } else {
931 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
932 evo_data(push, 0x05000000);
933 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
934 evo_data(push, 0x00000000);
935 }
de8268c5
BS		 936 evo_kick(push, mast);
937 }
938}
438d99e3 939
de8268c5 940static void
e225f446 941nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
de8268c5 942{
e225f446 943 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 944
945 if (show)
e225f446 946 nv50_crtc_cursor_show(nv_crtc);
de8268c5 947 else
e225f446 948 nv50_crtc_cursor_hide(nv_crtc);
de8268c5
BS		 949
950 if (update) {
951 u32 *push = evo_wait(mast, 2);
952 if (push) {
438d99e3
BS		 953 evo_mthd(push, 0x0080, 1);
954 evo_data(push, 0x00000000);
de8268c5 955 evo_kick(push, mast);
438d99e3 956 }
438d99e3
BS		 957 }
958}
959
960static void
e225f446 961nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
438d99e3
BS		 962{
963}
964
965static void
e225f446 966nv50_crtc_prepare(struct drm_crtc *crtc)
438d99e3
BS		 967{
968 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 969 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 970 u32 *push;
971
e225f446 972 nv50_display_flip_stop(crtc);
3376ee37 973
56d237d2 974 push = evo_wait(mast, 6);
438d99e3 975 if (push) {
e225f446 976 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5
BS		 977 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
978 evo_data(push, 0x00000000);
979 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
980 evo_data(push, 0x40000000);
981 } else
e225f446 982 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 983 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
984 evo_data(push, 0x00000000);
985 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
986 evo_data(push, 0x40000000);
987 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
988 evo_data(push, 0x00000000);
989 } else {
990 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
991 evo_data(push, 0x00000000);
992 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
993 evo_data(push, 0x03000000);
994 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
995 evo_data(push, 0x00000000);
996 }
997
998 evo_kick(push, mast);
438d99e3
BS		 999 }
1000
e225f446 1001 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
438d99e3
BS		 1002}
1003
1004static void
e225f446 1005nv50_crtc_commit(struct drm_crtc *crtc)
438d99e3
BS		 1006{
1007 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 1008 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 1009 u32 *push;
1010
de8268c5 1011 push = evo_wait(mast, 32);
438d99e3 1012 if (push) {
e225f446 1013 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
de8268c5 1014 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 1015 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1016 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1017 evo_data(push, 0xc0000000);
1018 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1019 } else
e225f446 1020 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5 1021 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 1022 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1023 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1024 evo_data(push, 0xc0000000);
1025 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1026 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
f45f55c4 1027 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 1028 } else {
1029 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
8a423647 1030 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1031 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1032 evo_data(push, 0x83000000);
1033 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1034 evo_data(push, 0x00000000);
1035 evo_data(push, 0x00000000);
1036 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
f45f55c4 1037 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 1038 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1039 evo_data(push, 0xffffff00);
1040 }
1041
1042 evo_kick(push, mast);
438d99e3
BS		 1043 }
1044
e225f446 1045 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
f4510a27 1046 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
438d99e3
BS		 1047}
1048
1049static bool
e225f446 1050nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
438d99e3
BS		 1051 struct drm_display_mode *adjusted_mode)
1052{
eb2e9686 1053 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
438d99e3
BS		 1054 return true;
1055}
1056
1057static int
e225f446 1058nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
438d99e3 1059{
f4510a27 1060 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
8dda53fc 1061 struct nv50_head *head = nv50_head(crtc);
438d99e3
BS		 1062 int ret;
1063
1064 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
8dda53fc
BS		 1065 if (ret == 0) {
1066 if (head->image)
1067 nouveau_bo_unpin(head->image);
1068 nouveau_bo_ref(nvfb->nvbo, &head->image);
438d99e3
BS		 1069 }
1070
8dda53fc 1071 return ret;
438d99e3
BS		 1072}
1073
1074static int
e225f446 1075nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
438d99e3
BS		 1076 struct drm_display_mode *mode, int x, int y,
1077 struct drm_framebuffer *old_fb)
1078{
e225f446 1079 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 1080 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1081 struct nouveau_connector *nv_connector;
2d1d898b
BS		 1082 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1083 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1084 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1085 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1086 u32 vblan2e = 0, vblan2s = 1;
3488c57b 1087 u32 *push;
438d99e3
BS		 1088 int ret;
1089
2d1d898b
BS		 1090 hactive = mode->htotal;
1091 hsynce = mode->hsync_end - mode->hsync_start - 1;
1092 hbackp = mode->htotal - mode->hsync_end;
1093 hblanke = hsynce + hbackp;
1094 hfrontp = mode->hsync_start - mode->hdisplay;
1095 hblanks = mode->htotal - hfrontp - 1;
1096
1097 vactive = mode->vtotal * vscan / ilace;
1098 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1099 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1100 vblanke = vsynce + vbackp;
1101 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1102 vblanks = vactive - vfrontp - 1;
1103 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1104 vblan2e = vactive + vsynce + vbackp;
1105 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1106 vactive = (vactive * 2) + 1;
2d1d898b
BS		 1107 }
1108
e225f446 1109 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1110 if (ret)
1111 return ret;
1112
de8268c5 1113 push = evo_wait(mast, 64);
438d99e3 1114 if (push) {
e225f446 1115 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
de8268c5
BS		 1116 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1117 evo_data(push, 0x00800000 | mode->clock);
1118 evo_data(push, (ilace == 2) ? 2 : 0);
1119 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1120 evo_data(push, 0x00000000);
1121 evo_data(push, (vactive << 16) | hactive);
1122 evo_data(push, ( vsynce << 16) | hsynce);
1123 evo_data(push, (vblanke << 16) | hblanke);
1124 evo_data(push, (vblanks << 16) | hblanks);
1125 evo_data(push, (vblan2e << 16) | vblan2s);
1126 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1127 evo_data(push, 0x00000000);
1128 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1129 evo_data(push, 0x00000311);
1130 evo_data(push, 0x00000100);
1131 } else {
1132 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1133 evo_data(push, 0x00000000);
1134 evo_data(push, (vactive << 16) | hactive);
1135 evo_data(push, ( vsynce << 16) | hsynce);
1136 evo_data(push, (vblanke << 16) | hblanke);
1137 evo_data(push, (vblanks << 16) | hblanks);
1138 evo_data(push, (vblan2e << 16) | vblan2s);
1139 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1140 evo_data(push, 0x00000000); /* ??? */
1141 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1142 evo_data(push, mode->clock * 1000);
1143 evo_data(push, 0x00200000); /* ??? */
1144 evo_data(push, mode->clock * 1000);
1145 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1146 evo_data(push, 0x00000311);
1147 evo_data(push, 0x00000100);
1148 }
1149
1150 evo_kick(push, mast);
438d99e3
BS		 1151 }
1152
1153 nv_connector = nouveau_crtc_connector_get(nv_crtc);
e225f446
BS		 1154 nv50_crtc_set_dither(nv_crtc, false);
1155 nv50_crtc_set_scale(nv_crtc, false);
1156 nv50_crtc_set_color_vibrance(nv_crtc, false);
f4510a27 1157 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
438d99e3
BS		 1158 return 0;
1159}
1160
1161static int
e225f446 1162nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
438d99e3
BS		 1163 struct drm_framebuffer *old_fb)
1164{
77145f1c 1165 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
438d99e3
BS		 1166 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1167 int ret;
1168
f4510a27 1169 if (!crtc->primary->fb) {
77145f1c 1170 NV_DEBUG(drm, "No FB bound\n");
84e2ad8b
BS		 1171 return 0;
1172 }
1173
e225f446 1174 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1175 if (ret)
1176 return ret;
1177
e225f446 1178 nv50_display_flip_stop(crtc);
f4510a27
MR		 1179 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1180 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
438d99e3
BS		 1181 return 0;
1182}
1183
1184static int
e225f446 1185nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
438d99e3
BS		 1186 struct drm_framebuffer *fb, int x, int y,
1187 enum mode_set_atomic state)
1188{
1189 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1190 nv50_display_flip_stop(crtc);
1191 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
438d99e3
BS		 1192 return 0;
1193}
1194
1195static void
e225f446 1196nv50_crtc_lut_load(struct drm_crtc *crtc)
438d99e3 1197{
e225f446 1198 struct nv50_disp *disp = nv50_disp(crtc->dev);
438d99e3
BS		 1199 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1200 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1201 int i;
1202
1203 for (i = 0; i < 256; i++) {
de8268c5
BS		 1204 u16 r = nv_crtc->lut.r[i] >> 2;
1205 u16 g = nv_crtc->lut.g[i] >> 2;
1206 u16 b = nv_crtc->lut.b[i] >> 2;
1207
0ad72863 1208 if (disp->disp->oclass < NVD0_DISP_CLASS) {
de8268c5
BS		 1209 writew(r + 0x0000, lut + (i * 0x08) + 0);
1210 writew(g + 0x0000, lut + (i * 0x08) + 2);
1211 writew(b + 0x0000, lut + (i * 0x08) + 4);
1212 } else {
1213 writew(r + 0x6000, lut + (i * 0x20) + 0);
1214 writew(g + 0x6000, lut + (i * 0x20) + 2);
1215 writew(b + 0x6000, lut + (i * 0x20) + 4);
1216 }
438d99e3
BS		 1217 }
1218}
1219
8dda53fc
BS		 1220static void
1221nv50_crtc_disable(struct drm_crtc *crtc)
1222{
1223 struct nv50_head *head = nv50_head(crtc);
efa366fd 1224 evo_sync(crtc->dev);
8dda53fc
BS		 1225 if (head->image)
1226 nouveau_bo_unpin(head->image);
1227 nouveau_bo_ref(NULL, &head->image);
1228}
1229
438d99e3 1230static int
e225f446 1231nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
438d99e3
BS		 1232 uint32_t handle, uint32_t width, uint32_t height)
1233{
1234 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1235 struct drm_device *dev = crtc->dev;
1236 struct drm_gem_object *gem;
1237 struct nouveau_bo *nvbo;
1238 bool visible = (handle != 0);
1239 int i, ret = 0;
1240
1241 if (visible) {
1242 if (width != 64 || height != 64)
1243 return -EINVAL;
1244
1245 gem = drm_gem_object_lookup(dev, file_priv, handle);
1246 if (unlikely(!gem))
1247 return -ENOENT;
1248 nvbo = nouveau_gem_object(gem);
1249
1250 ret = nouveau_bo_map(nvbo);
1251 if (ret == 0) {
1252 for (i = 0; i < 64 * 64; i++) {
1253 u32 v = nouveau_bo_rd32(nvbo, i);
1254 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1255 }
1256 nouveau_bo_unmap(nvbo);
1257 }
1258
1259 drm_gem_object_unreference_unlocked(gem);
1260 }
1261
1262 if (visible != nv_crtc->cursor.visible) {
e225f446 1263 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
438d99e3
BS		 1264 nv_crtc->cursor.visible = visible;
1265 }
1266
1267 return ret;
1268}
1269
1270static int
e225f446 1271nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
438d99e3 1272{
e225f446
BS		 1273 struct nv50_curs *curs = nv50_curs(crtc);
1274 struct nv50_chan *chan = nv50_chan(curs);
0ad72863
BS		 1275 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1276 nvif_wr32(&chan->user, 0x0080, 0x00000000);
438d99e3
BS		 1277 return 0;
1278}
1279
1280static void
e225f446 1281nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
438d99e3
BS		 1282 uint32_t start, uint32_t size)
1283{
1284 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
bdefc8cb 1285 u32 end = min_t(u32, start + size, 256);
438d99e3
BS		 1286 u32 i;
1287
1288 for (i = start; i < end; i++) {
1289 nv_crtc->lut.r[i] = r[i];
1290 nv_crtc->lut.g[i] = g[i];
1291 nv_crtc->lut.b[i] = b[i];
1292 }
1293
e225f446 1294 nv50_crtc_lut_load(crtc);
438d99e3
BS		 1295}
1296
1297static void
e225f446 1298nv50_crtc_destroy(struct drm_crtc *crtc)
438d99e3
BS		 1299{
1300 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1301 struct nv50_disp *disp = nv50_disp(crtc->dev);
1302 struct nv50_head *head = nv50_head(crtc);
0ad72863 1303 struct nv50_fbdma *fbdma;
8dda53fc 1304
0ad72863
BS		 1305 list_for_each_entry(fbdma, &disp->fbdma, head) {
1306 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1307 }
1308
1309 nv50_dmac_destroy(&head->ovly.base, disp->disp);
1310 nv50_pioc_destroy(&head->oimm.base);
1311 nv50_dmac_destroy(&head->sync.base, disp->disp);
1312 nv50_pioc_destroy(&head->curs.base);
8dda53fc
BS		 1313
1314 /*XXX: this shouldn't be necessary, but the core doesn't call
1315 * disconnect() during the cleanup paths
1316 */
1317 if (head->image)
1318 nouveau_bo_unpin(head->image);
1319 nouveau_bo_ref(NULL, &head->image);
1320
438d99e3 1321 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
04c8c210
MS		 1322 if (nv_crtc->cursor.nvbo)
1323 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
438d99e3 1324 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
8dda53fc 1325
438d99e3 1326 nouveau_bo_unmap(nv_crtc->lut.nvbo);
04c8c210
MS		 1327 if (nv_crtc->lut.nvbo)
1328 nouveau_bo_unpin(nv_crtc->lut.nvbo);
438d99e3 1329 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
8dda53fc 1330
438d99e3
BS		 1331 drm_crtc_cleanup(crtc);
1332 kfree(crtc);
1333}
1334
e225f446
BS		 1335static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1336 .dpms = nv50_crtc_dpms,
1337 .prepare = nv50_crtc_prepare,
1338 .commit = nv50_crtc_commit,
1339 .mode_fixup = nv50_crtc_mode_fixup,
1340 .mode_set = nv50_crtc_mode_set,
1341 .mode_set_base = nv50_crtc_mode_set_base,
1342 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1343 .load_lut = nv50_crtc_lut_load,
8dda53fc 1344 .disable = nv50_crtc_disable,
438d99e3
BS		 1345};
1346
e225f446
BS		 1347static const struct drm_crtc_funcs nv50_crtc_func = {
1348 .cursor_set = nv50_crtc_cursor_set,
1349 .cursor_move = nv50_crtc_cursor_move,
1350 .gamma_set = nv50_crtc_gamma_set,
5addcf0a 1351 .set_config = nouveau_crtc_set_config,
e225f446 1352 .destroy = nv50_crtc_destroy,
3376ee37 1353 .page_flip = nouveau_crtc_page_flip,
438d99e3
BS		 1354};
1355
c20ab3e1 1356static void
e225f446 1357nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
c20ab3e1
BS		 1358{
1359}
1360
1361static void
e225f446 1362nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
c20ab3e1
BS		 1363{
1364}
1365
438d99e3 1366static int
0ad72863 1367nv50_crtc_create(struct drm_device *dev, int index)
438d99e3 1368{
e225f446
BS		 1369 struct nv50_disp *disp = nv50_disp(dev);
1370 struct nv50_head *head;
438d99e3
BS		 1371 struct drm_crtc *crtc;
1372 int ret, i;
1373
dd0e3d53
BS		 1374 head = kzalloc(sizeof(*head), GFP_KERNEL);
1375 if (!head)
438d99e3
BS		 1376 return -ENOMEM;
1377
dd0e3d53 1378 head->base.index = index;
e225f446
BS		 1379 head->base.set_dither = nv50_crtc_set_dither;
1380 head->base.set_scale = nv50_crtc_set_scale;
1381 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
f9887d09
BS		 1382 head->base.color_vibrance = 50;
1383 head->base.vibrant_hue = 0;
e225f446
BS		 1384 head->base.cursor.set_offset = nv50_cursor_set_offset;
1385 head->base.cursor.set_pos = nv50_cursor_set_pos;
438d99e3 1386 for (i = 0; i < 256; i++) {
dd0e3d53
BS		 1387 head->base.lut.r[i] = i << 8;
1388 head->base.lut.g[i] = i << 8;
1389 head->base.lut.b[i] = i << 8;
438d99e3
BS		 1390 }
1391
dd0e3d53 1392 crtc = &head->base.base;
e225f446
BS		 1393 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1394 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
438d99e3
BS		 1395 drm_mode_crtc_set_gamma_size(crtc, 256);
1396
b5a794b0
BS		 1397 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1398 0, 0x0000, NULL, &head->base.lut.nvbo);
1399 if (!ret) {
1400 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1401 if (!ret) {
b5a794b0 1402 ret = nouveau_bo_map(head->base.lut.nvbo);
04c8c210
MS		 1403 if (ret)
1404 nouveau_bo_unpin(head->base.lut.nvbo);
1405 }
b5a794b0
BS		 1406 if (ret)
1407 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1408 }
1409
1410 if (ret)
1411 goto out;
1412
e225f446 1413 nv50_crtc_lut_load(crtc);
b5a794b0
BS		 1414
1415 /* allocate cursor resources */
410f3ec6 1416 ret = nv50_curs_create(disp->disp, index, &head->curs);
b5a794b0
BS		 1417 if (ret)
1418 goto out;
1419
438d99e3 1420 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
dd0e3d53 1421 0, 0x0000, NULL, &head->base.cursor.nvbo);
438d99e3 1422 if (!ret) {
dd0e3d53 1423 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1424 if (!ret) {
dd0e3d53 1425 ret = nouveau_bo_map(head->base.cursor.nvbo);
04c8c210
MS		 1426 if (ret)
1427 nouveau_bo_unpin(head->base.lut.nvbo);
1428 }
438d99e3 1429 if (ret)
dd0e3d53 1430 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
438d99e3
BS		 1431 }
1432
1433 if (ret)
1434 goto out;
1435
b5a794b0 1436 /* allocate page flip / sync resources */
410f3ec6
BS		 1437 ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset,
1438 &head->sync);
b5a794b0
BS		 1439 if (ret)
1440 goto out;
1441
9f9bdaaf
BS		 1442 head->sync.addr = EVO_FLIP_SEM0(index);
1443 head->sync.data = 0x00000000;
438d99e3 1444
b5a794b0 1445 /* allocate overlay resources */
410f3ec6 1446 ret = nv50_oimm_create(disp->disp, index, &head->oimm);
438d99e3
BS		 1447 if (ret)
1448 goto out;
1449
410f3ec6
BS		 1450 ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset,
1451 &head->ovly);
b5a794b0
BS		 1452 if (ret)
1453 goto out;
438d99e3
BS		 1454
1455out:
1456 if (ret)
e225f446 1457 nv50_crtc_destroy(crtc);
438d99e3
BS		 1458 return ret;
1459}
1460
26f6d88b
BS		 1461/******************************************************************************
1462 * DAC
1463 *****************************************************************************/
8eaa9669 1464static void
e225f446 1465nv50_dac_dpms(struct drm_encoder *encoder, int mode)
8eaa9669
BS		 1466{
1467 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1468 struct nv50_disp *disp = nv50_disp(encoder->dev);
bf0eb898
BS		 1469 struct {
1470 struct nv50_disp_mthd_v1 base;
1471 struct nv50_disp_dac_pwr_v0 pwr;
1472 } args = {
1473 .base.version = 1,
1474 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1475 .base.hasht = nv_encoder->dcb->hasht,
1476 .base.hashm = nv_encoder->dcb->hashm,
1477 .pwr.state = 1,
1478 .pwr.data = 1,
1479 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1480 mode != DRM_MODE_DPMS_OFF),
1481 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1482 mode != DRM_MODE_DPMS_OFF),
1483 };
8eaa9669 1484
8eaa9669 1485
bf0eb898 1486 nvif_mthd(disp->disp, 0, &args, sizeof(args));
8eaa9669
BS		 1487}
1488
1489static bool
e225f446 1490nv50_dac_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1491 const struct drm_display_mode *mode,
8eaa9669
BS		 1492 struct drm_display_mode *adjusted_mode)
1493{
1494 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1495 struct nouveau_connector *nv_connector;
1496
1497 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1498 if (nv_connector && nv_connector->native_mode) {
1499 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1500 int id = adjusted_mode->base.id;
1501 *adjusted_mode = *nv_connector->native_mode;
1502 adjusted_mode->base.id = id;
1503 }
1504 }
1505
1506 return true;
1507}
1508
8eaa9669 1509static void
e225f446 1510nv50_dac_commit(struct drm_encoder *encoder)
8eaa9669
BS		 1511{
1512}
1513
1514static void
e225f446 1515nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
8eaa9669
BS		 1516 struct drm_display_mode *adjusted_mode)
1517{
e225f446 1518 struct nv50_mast *mast = nv50_mast(encoder->dev);
8eaa9669
BS		 1519 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1520 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
97b19b5c 1521 u32 *push;
8eaa9669 1522
e225f446 1523 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
8eaa9669 1524
97b19b5c 1525 push = evo_wait(mast, 8);
8eaa9669 1526 if (push) {
e225f446 1527 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
97b19b5c
BS		 1528 u32 syncs = 0x00000000;
1529
1530 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1531 syncs |= 0x00000001;
1532 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1533 syncs |= 0x00000002;
1534
1535 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1536 evo_data(push, 1 << nv_crtc->index);
1537 evo_data(push, syncs);
1538 } else {
1539 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1540 u32 syncs = 0x00000001;
1541
1542 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1543 syncs |= 0x00000008;
1544 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1545 syncs |= 0x00000010;
1546
1547 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1548 magic |= 0x00000001;
1549
1550 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1551 evo_data(push, syncs);
1552 evo_data(push, magic);
1553 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1554 evo_data(push, 1 << nv_crtc->index);
1555 }
1556
1557 evo_kick(push, mast);
8eaa9669
BS		 1558 }
1559
1560 nv_encoder->crtc = encoder->crtc;
1561}
1562
1563static void
e225f446 1564nv50_dac_disconnect(struct drm_encoder *encoder)
8eaa9669
BS		 1565{
1566 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1567 struct nv50_mast *mast = nv50_mast(encoder->dev);
97b19b5c 1568 const int or = nv_encoder->or;
8eaa9669
BS		 1569 u32 *push;
1570
1571 if (nv_encoder->crtc) {
e225f446 1572 nv50_crtc_prepare(nv_encoder->crtc);
8eaa9669 1573
97b19b5c 1574 push = evo_wait(mast, 4);
8eaa9669 1575 if (push) {
e225f446 1576 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
97b19b5c
BS		 1577 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1578 evo_data(push, 0x00000000);
1579 } else {
1580 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1581 evo_data(push, 0x00000000);
1582 }
97b19b5c 1583 evo_kick(push, mast);
8eaa9669 1584 }
8eaa9669 1585 }
97b19b5c
BS		 1586
1587 nv_encoder->crtc = NULL;
8eaa9669
BS		 1588}
1589
b6d8e7ec 1590static enum drm_connector_status
e225f446 1591nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
b6d8e7ec 1592{
c4abd317 1593 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1594 struct nv50_disp *disp = nv50_disp(encoder->dev);
c4abd317
BS		 1595 struct {
1596 struct nv50_disp_mthd_v1 base;
1597 struct nv50_disp_dac_load_v0 load;
1598 } args = {
1599 .base.version = 1,
1600 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1601 .base.hasht = nv_encoder->dcb->hasht,
1602 .base.hashm = nv_encoder->dcb->hashm,
1603 };
1604 int ret;
1605
1606 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1607 if (args.load.data == 0)
1608 args.load.data = 340;
b681993f 1609
c4abd317
BS		 1610 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1611 if (ret || !args.load.load)
35b21d39 1612 return connector_status_disconnected;
b681993f 1613
35b21d39 1614 return connector_status_connected;
b6d8e7ec
BS		 1615}
1616
8eaa9669 1617static void
e225f446 1618nv50_dac_destroy(struct drm_encoder *encoder)
8eaa9669
BS		 1619{
1620 drm_encoder_cleanup(encoder);
1621 kfree(encoder);
1622}
1623
e225f446
BS		 1624static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1625 .dpms = nv50_dac_dpms,
1626 .mode_fixup = nv50_dac_mode_fixup,
1627 .prepare = nv50_dac_disconnect,
1628 .commit = nv50_dac_commit,
1629 .mode_set = nv50_dac_mode_set,
1630 .disable = nv50_dac_disconnect,
1631 .get_crtc = nv50_display_crtc_get,
1632 .detect = nv50_dac_detect
8eaa9669
BS		 1633};
1634
e225f446
BS		 1635static const struct drm_encoder_funcs nv50_dac_func = {
1636 .destroy = nv50_dac_destroy,
8eaa9669
BS		 1637};
1638
1639static int
e225f446 1640nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
8eaa9669 1641{
5ed50209 1642 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 1643 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
8eaa9669
BS		 1644 struct nouveau_encoder *nv_encoder;
1645 struct drm_encoder *encoder;
5ed50209 1646 int type = DRM_MODE_ENCODER_DAC;
8eaa9669
BS		 1647
1648 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1649 if (!nv_encoder)
1650 return -ENOMEM;
1651 nv_encoder->dcb = dcbe;
1652 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 1653 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
8eaa9669
BS		 1654
1655 encoder = to_drm_encoder(nv_encoder);
1656 encoder->possible_crtcs = dcbe->heads;
1657 encoder->possible_clones = 0;
5ed50209 1658 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
e225f446 1659 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
8eaa9669
BS		 1660
1661 drm_mode_connector_attach_encoder(connector, encoder);
1662 return 0;
1663}
26f6d88b 1664
78951d22
BS		 1665/******************************************************************************
1666 * Audio
1667 *****************************************************************************/
1668static void
e225f446 1669nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22
BS		 1670{
1671 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1672 struct nouveau_connector *nv_connector;
e225f446 1673 struct nv50_disp *disp = nv50_disp(encoder->dev);
78951d22
BS		 1674
1675 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1676 if (!drm_detect_monitor_audio(nv_connector->edid))
1677 return;
1678
78951d22 1679 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
78951d22 1680
0ad72863
BS		 1681 nvif_exec(disp->disp, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1682 nv_connector->base.eld,
1683 nv_connector->base.eld[2] * 4);
78951d22
BS		 1684}
1685
1686static void
e225f446 1687nv50_audio_disconnect(struct drm_encoder *encoder)
78951d22
BS		 1688{
1689 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1690 struct nv50_disp *disp = nv50_disp(encoder->dev);
78951d22 1691
0ad72863 1692 nvif_exec(disp->disp, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
78951d22
BS		 1693}
1694
1695/******************************************************************************
1696 * HDMI
1697 *****************************************************************************/
1698static void
e225f446 1699nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22 1700{
64d9cc04
BS		 1701 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1702 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1703 struct nouveau_connector *nv_connector;
e225f446 1704 struct nv50_disp *disp = nv50_disp(encoder->dev);
1c30cd09 1705 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
64d9cc04
BS		 1706 u32 rekey = 56; /* binary driver, and tegra constant */
1707 u32 max_ac_packet;
0ad72863 1708 u32 data;
64d9cc04
BS		 1709
1710 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1711 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1712 return;
1713
1714 max_ac_packet = mode->htotal - mode->hdisplay;
1715 max_ac_packet -= rekey;
1716 max_ac_packet -= 18; /* constant from tegra */
1717 max_ac_packet /= 32;
1718
0ad72863
BS		 1719 data = NV84_DISP_SOR_HDMI_PWR_STATE_ON | (max_ac_packet << 16) | rekey;
1720 nvif_exec(disp->disp, NV84_DISP_SOR_HDMI_PWR + moff, &data, sizeof(data));
091e40cd 1721
e225f446 1722 nv50_audio_mode_set(encoder, mode);
78951d22
BS		 1723}
1724
1725static void
e84a35a8 1726nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
78951d22 1727{
64d9cc04 1728 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1729 struct nv50_disp *disp = nv50_disp(encoder->dev);
1c30cd09 1730 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
0ad72863 1731 u32 data = 0;
64d9cc04 1732
e225f446 1733 nv50_audio_disconnect(encoder);
64d9cc04 1734
0ad72863 1735 nvif_exec(disp->disp, NV84_DISP_SOR_HDMI_PWR + moff, &data, sizeof(data));
78951d22
BS		 1736}
1737
26f6d88b
BS		 1738/******************************************************************************
1739 * SOR
1740 *****************************************************************************/
83fc083c 1741static void
e225f446 1742nv50_sor_dpms(struct drm_encoder *encoder, int mode)
83fc083c
BS		 1743{
1744 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1745 struct drm_device *dev = encoder->dev;
e225f446 1746 struct nv50_disp *disp = nv50_disp(dev);
83fc083c 1747 struct drm_encoder *partner;
0ad72863 1748 u32 mthd, data;
83fc083c
BS		 1749
1750 nv_encoder->last_dpms = mode;
1751
1752 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1753 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1754
1755 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1756 continue;
1757
1758 if (nv_partner != nv_encoder &&
26cfa813 1759 nv_partner->dcb->or == nv_encoder->dcb->or) {
83fc083c
BS		 1760 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1761 return;
1762 break;
1763 }
1764 }
1765
276e526c
BS		 1766 mthd = (ffs(nv_encoder->dcb->heads) - 1) << 3;
1767 mthd |= (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
4874322e
BS		 1768 mthd |= nv_encoder->or;
1769
1770 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
0ad72863
BS		 1771 data = 1;
1772 nvif_exec(disp->disp, NV50_DISP_SOR_PWR | mthd, &data, sizeof(data));
4874322e
BS		 1773 mthd |= NV94_DISP_SOR_DP_PWR;
1774 } else {
1775 mthd |= NV50_DISP_SOR_PWR;
1776 }
1777
0ad72863
BS		 1778 data = (mode == DRM_MODE_DPMS_ON);
1779 nvif_exec(disp->disp, mthd, &data, sizeof(data));
83fc083c
BS		 1780}
1781
1782static bool
e225f446 1783nv50_sor_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1784 const struct drm_display_mode *mode,
83fc083c
BS		 1785 struct drm_display_mode *adjusted_mode)
1786{
1787 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1788 struct nouveau_connector *nv_connector;
1789
1790 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1791 if (nv_connector && nv_connector->native_mode) {
1792 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1793 int id = adjusted_mode->base.id;
1794 *adjusted_mode = *nv_connector->native_mode;
1795 adjusted_mode->base.id = id;
1796 }
1797 }
1798
1799 return true;
1800}
1801
4cbb0f8d 1802static void
e84a35a8 1803nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
4cbb0f8d 1804{
e84a35a8
BS		 1805 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1806 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1807 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1808 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1809 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1810 evo_data(push, (nv_encoder->ctrl = temp));
1811 } else {
1812 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1813 evo_data(push, (nv_encoder->ctrl = temp));
4cbb0f8d 1814 }
e84a35a8 1815 evo_kick(push, mast);
4cbb0f8d 1816 }
e84a35a8
BS		 1817}
1818
1819static void
1820nv50_sor_disconnect(struct drm_encoder *encoder)
1821{
1822 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1823 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
419e8dc0
BS		 1824
1825 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1826 nv_encoder->crtc = NULL;
e84a35a8
BS		 1827
1828 if (nv_crtc) {
1829 nv50_crtc_prepare(&nv_crtc->base);
1830 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1831 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1832 }
4cbb0f8d
BS		 1833}
1834
83fc083c 1835static void
e225f446 1836nv50_sor_commit(struct drm_encoder *encoder)
83fc083c
BS		 1837{
1838}
1839
1840static void
e225f446 1841nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
3b6d83d1 1842 struct drm_display_mode *mode)
83fc083c 1843{
e225f446
BS		 1844 struct nv50_disp *disp = nv50_disp(encoder->dev);
1845 struct nv50_mast *mast = nv50_mast(encoder->dev);
78951d22 1846 struct drm_device *dev = encoder->dev;
77145f1c 1847 struct nouveau_drm *drm = nouveau_drm(dev);
83fc083c
BS		 1848 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1849 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3b6d83d1 1850 struct nouveau_connector *nv_connector;
77145f1c 1851 struct nvbios *bios = &drm->vbios;
e84a35a8 1852 u32 lvds = 0, mask, ctrl;
419e8dc0
BS		 1853 u8 owner = 1 << nv_crtc->index;
1854 u8 proto = 0xf;
1855 u8 depth = 0x0;
83fc083c 1856
3b6d83d1 1857 nv_connector = nouveau_encoder_connector_get(nv_encoder);
e84a35a8
BS		 1858 nv_encoder->crtc = encoder->crtc;
1859
3b6d83d1 1860 switch (nv_encoder->dcb->type) {
cb75d97e 1861 case DCB_OUTPUT_TMDS:
3b6d83d1
BS		 1862 if (nv_encoder->dcb->sorconf.link & 1) {
1863 if (mode->clock < 165000)
419e8dc0 1864 proto = 0x1;
3b6d83d1 1865 else
419e8dc0 1866 proto = 0x5;
3b6d83d1 1867 } else {
419e8dc0 1868 proto = 0x2;
3b6d83d1
BS		 1869 }
1870
e84a35a8 1871 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
3b6d83d1 1872 break;
cb75d97e 1873 case DCB_OUTPUT_LVDS:
419e8dc0
BS		 1874 proto = 0x0;
1875
3b6d83d1
BS		 1876 if (bios->fp_no_ddc) {
1877 if (bios->fp.dual_link)
419e8dc0 1878 lvds |= 0x0100;
3b6d83d1 1879 if (bios->fp.if_is_24bit)
419e8dc0 1880 lvds |= 0x0200;
3b6d83d1 1881 } else {
befb51e9 1882 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3b6d83d1 1883 if (((u8 *)nv_connector->edid)[121] == 2)
419e8dc0 1884 lvds |= 0x0100;
3b6d83d1
BS		 1885 } else
1886 if (mode->clock >= bios->fp.duallink_transition_clk) {
419e8dc0 1887 lvds |= 0x0100;
3b6d83d1 1888 }
83fc083c 1889
419e8dc0 1890 if (lvds & 0x0100) {
3b6d83d1 1891 if (bios->fp.strapless_is_24bit & 2)
419e8dc0 1892 lvds |= 0x0200;
3b6d83d1
BS		 1893 } else {
1894 if (bios->fp.strapless_is_24bit & 1)
419e8dc0 1895 lvds |= 0x0200;
3b6d83d1
BS		 1896 }
1897
1898 if (nv_connector->base.display_info.bpc == 8)
419e8dc0 1899 lvds |= 0x0200;
3b6d83d1 1900 }
4a230fa6 1901
0ad72863 1902 nvif_exec(disp->disp, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, &lvds, sizeof(lvds));
3b6d83d1 1903 break;
cb75d97e 1904 case DCB_OUTPUT_DP:
3488c57b 1905 if (nv_connector->base.display_info.bpc == 6) {
6e83fda2 1906 nv_encoder->dp.datarate = mode->clock * 18 / 8;
419e8dc0 1907 depth = 0x2;
bf2c886a
BS		 1908 } else
1909 if (nv_connector->base.display_info.bpc == 8) {
6e83fda2 1910 nv_encoder->dp.datarate = mode->clock * 24 / 8;
419e8dc0 1911 depth = 0x5;
bf2c886a
BS		 1912 } else {
1913 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1914 depth = 0x6;
3488c57b 1915 }
6e83fda2
BS		 1916
1917 if (nv_encoder->dcb->sorconf.link & 1)
419e8dc0 1918 proto = 0x8;
6e83fda2 1919 else
419e8dc0 1920 proto = 0x9;
6e83fda2 1921 break;
3b6d83d1
BS		 1922 default:
1923 BUG_ON(1);
1924 break;
1925 }
ff8ff503 1926
e84a35a8 1927 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
83fc083c 1928
e84a35a8
BS		 1929 if (nv50_vers(mast) >= NVD0_DISP_CLASS) {
1930 u32 *push = evo_wait(mast, 3);
1931 if (push) {
419e8dc0
BS		 1932 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1933 u32 syncs = 0x00000001;
1934
1935 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1936 syncs |= 0x00000008;
1937 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1938 syncs |= 0x00000010;
1939
1940 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1941 magic |= 0x00000001;
1942
1943 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1944 evo_data(push, syncs | (depth << 6));
1945 evo_data(push, magic);
e84a35a8 1946 evo_kick(push, mast);
419e8dc0
BS		 1947 }
1948
e84a35a8
BS		 1949 ctrl = proto << 8;
1950 mask = 0x00000f00;
1951 } else {
1952 ctrl = (depth << 16) | (proto << 8);
1953 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1954 ctrl |= 0x00001000;
1955 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1956 ctrl |= 0x00002000;
1957 mask = 0x000f3f00;
83fc083c
BS		 1958 }
1959
e84a35a8 1960 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
83fc083c
BS		 1961}
1962
83fc083c 1963static void
e225f446 1964nv50_sor_destroy(struct drm_encoder *encoder)
83fc083c
BS		 1965{
1966 drm_encoder_cleanup(encoder);
1967 kfree(encoder);
1968}
1969
e225f446
BS		 1970static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1971 .dpms = nv50_sor_dpms,
1972 .mode_fixup = nv50_sor_mode_fixup,
5a885f0b 1973 .prepare = nv50_sor_disconnect,
e225f446
BS		 1974 .commit = nv50_sor_commit,
1975 .mode_set = nv50_sor_mode_set,
1976 .disable = nv50_sor_disconnect,
1977 .get_crtc = nv50_display_crtc_get,
83fc083c
BS		 1978};
1979
e225f446
BS		 1980static const struct drm_encoder_funcs nv50_sor_func = {
1981 .destroy = nv50_sor_destroy,
83fc083c
BS		 1982};
1983
1984static int
e225f446 1985nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
83fc083c 1986{
5ed50209 1987 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 1988 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
83fc083c
BS		 1989 struct nouveau_encoder *nv_encoder;
1990 struct drm_encoder *encoder;
5ed50209
BS		 1991 int type;
1992
1993 switch (dcbe->type) {
1994 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1995 case DCB_OUTPUT_TMDS:
1996 case DCB_OUTPUT_DP:
1997 default:
1998 type = DRM_MODE_ENCODER_TMDS;
1999 break;
2000 }
83fc083c
BS		 2001
2002 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2003 if (!nv_encoder)
2004 return -ENOMEM;
2005 nv_encoder->dcb = dcbe;
2006 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 2007 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
83fc083c
BS		 2008 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2009
2010 encoder = to_drm_encoder(nv_encoder);
2011 encoder->possible_crtcs = dcbe->heads;
2012 encoder->possible_clones = 0;
5ed50209 2013 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
e225f446 2014 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
83fc083c
BS		 2015
2016 drm_mode_connector_attach_encoder(connector, encoder);
2017 return 0;
2018}
26f6d88b 2019
eb6313ad
BS		 2020/******************************************************************************
2021 * PIOR
2022 *****************************************************************************/
2023
2024static void
2025nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2026{
2027 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2028 struct nv50_disp *disp = nv50_disp(encoder->dev);
2029 u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
2030 u32 ctrl = (mode == DRM_MODE_DPMS_ON);
0ad72863 2031 nvif_exec(disp->disp, NV50_DISP_PIOR_PWR + mthd, &ctrl, sizeof(ctrl));
eb6313ad
BS		 2032}
2033
2034static bool
2035nv50_pior_mode_fixup(struct drm_encoder *encoder,
2036 const struct drm_display_mode *mode,
2037 struct drm_display_mode *adjusted_mode)
2038{
2039 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2040 struct nouveau_connector *nv_connector;
2041
2042 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2043 if (nv_connector && nv_connector->native_mode) {
2044 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2045 int id = adjusted_mode->base.id;
2046 *adjusted_mode = *nv_connector->native_mode;
2047 adjusted_mode->base.id = id;
2048 }
2049 }
2050
2051 adjusted_mode->clock *= 2;
2052 return true;
2053}
2054
2055static void
2056nv50_pior_commit(struct drm_encoder *encoder)
2057{
2058}
2059
2060static void
2061nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2062 struct drm_display_mode *adjusted_mode)
2063{
2064 struct nv50_mast *mast = nv50_mast(encoder->dev);
2065 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2066 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2067 struct nouveau_connector *nv_connector;
2068 u8 owner = 1 << nv_crtc->index;
2069 u8 proto, depth;
2070 u32 *push;
2071
2072 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2073 switch (nv_connector->base.display_info.bpc) {
2074 case 10: depth = 0x6; break;
2075 case 8: depth = 0x5; break;
2076 case 6: depth = 0x2; break;
2077 default: depth = 0x0; break;
2078 }
2079
2080 switch (nv_encoder->dcb->type) {
2081 case DCB_OUTPUT_TMDS:
2082 case DCB_OUTPUT_DP:
2083 proto = 0x0;
2084 break;
2085 default:
2086 BUG_ON(1);
2087 break;
2088 }
2089
2090 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2091
2092 push = evo_wait(mast, 8);
2093 if (push) {
2094 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2095 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2096 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2097 ctrl |= 0x00001000;
2098 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2099 ctrl |= 0x00002000;
2100 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2101 evo_data(push, ctrl);
2102 }
2103
2104 evo_kick(push, mast);
2105 }
2106
2107 nv_encoder->crtc = encoder->crtc;
2108}
2109
2110static void
2111nv50_pior_disconnect(struct drm_encoder *encoder)
2112{
2113 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2114 struct nv50_mast *mast = nv50_mast(encoder->dev);
2115 const int or = nv_encoder->or;
2116 u32 *push;
2117
2118 if (nv_encoder->crtc) {
2119 nv50_crtc_prepare(nv_encoder->crtc);
2120
2121 push = evo_wait(mast, 4);
2122 if (push) {
2123 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2124 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2125 evo_data(push, 0x00000000);
2126 }
eb6313ad
BS		 2127 evo_kick(push, mast);
2128 }
2129 }
2130
2131 nv_encoder->crtc = NULL;
2132}
2133
2134static void
2135nv50_pior_destroy(struct drm_encoder *encoder)
2136{
2137 drm_encoder_cleanup(encoder);
2138 kfree(encoder);
2139}
2140
2141static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2142 .dpms = nv50_pior_dpms,
2143 .mode_fixup = nv50_pior_mode_fixup,
2144 .prepare = nv50_pior_disconnect,
2145 .commit = nv50_pior_commit,
2146 .mode_set = nv50_pior_mode_set,
2147 .disable = nv50_pior_disconnect,
2148 .get_crtc = nv50_display_crtc_get,
2149};
2150
2151static const struct drm_encoder_funcs nv50_pior_func = {
2152 .destroy = nv50_pior_destroy,
2153};
2154
2155static int
2156nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2157{
2158 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 2159 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
eb6313ad
BS		 2160 struct nouveau_i2c_port *ddc = NULL;
2161 struct nouveau_encoder *nv_encoder;
2162 struct drm_encoder *encoder;
2163 int type;
2164
2165 switch (dcbe->type) {
2166 case DCB_OUTPUT_TMDS:
2167 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2168 type = DRM_MODE_ENCODER_TMDS;
2169 break;
2170 case DCB_OUTPUT_DP:
2171 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2172 type = DRM_MODE_ENCODER_TMDS;
2173 break;
2174 default:
2175 return -ENODEV;
2176 }
2177
2178 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2179 if (!nv_encoder)
2180 return -ENOMEM;
2181 nv_encoder->dcb = dcbe;
2182 nv_encoder->or = ffs(dcbe->or) - 1;
2183 nv_encoder->i2c = ddc;
2184
2185 encoder = to_drm_encoder(nv_encoder);
2186 encoder->possible_crtcs = dcbe->heads;
2187 encoder->possible_clones = 0;
2188 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2189 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2190
2191 drm_mode_connector_attach_encoder(connector, encoder);
2192 return 0;
2193}
2194
ab0af559
BS		 2195/******************************************************************************
2196 * Framebuffer
2197 *****************************************************************************/
2198
8a423647 2199static void
0ad72863 2200nv50_fbdma_fini(struct nv50_fbdma *fbdma)
8a423647 2201{
0ad72863
BS		 2202 int i;
2203 for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2204 nvif_object_fini(&fbdma->base[i]);
2205 nvif_object_fini(&fbdma->core);
8a423647
BS		 2206 list_del(&fbdma->head);
2207 kfree(fbdma);
2208}
2209
2210static int
2211nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2212{
2213 struct nouveau_drm *drm = nouveau_drm(dev);
2214 struct nv50_disp *disp = nv50_disp(dev);
2215 struct nv50_mast *mast = nv50_mast(dev);
4acfd707
BS		 2216 struct __attribute__ ((packed)) {
2217 struct nv_dma_v0 base;
2218 union {
2219 struct nv50_dma_v0 nv50;
2220 struct gf100_dma_v0 gf100;
2221 struct gf110_dma_v0 gf110;
2222 };
2223 } args = {};
8a423647
BS		 2224 struct nv50_fbdma *fbdma;
2225 struct drm_crtc *crtc;
4acfd707 2226 u32 size = sizeof(args.base);
8a423647
BS		 2227 int ret;
2228
2229 list_for_each_entry(fbdma, &disp->fbdma, head) {
0ad72863 2230 if (fbdma->core.handle == name)
8a423647
BS		 2231 return 0;
2232 }
2233
2234 fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2235 if (!fbdma)
2236 return -ENOMEM;
2237 list_add(&fbdma->head, &disp->fbdma);
8a423647 2238
4acfd707
BS		 2239 args.base.target = NV_DMA_V0_TARGET_VRAM;
2240 args.base.access = NV_DMA_V0_ACCESS_RDWR;
2241 args.base.start = offset;
2242 args.base.limit = offset + length - 1;
8a423647 2243
967e7bde 2244 if (drm->device.info.chipset < 0x80) {
4acfd707
BS		 2245 args.nv50.part = NV50_DMA_V0_PART_256;
2246 size += sizeof(args.nv50);
8a423647 2247 } else
967e7bde 2248 if (drm->device.info.chipset < 0xc0) {
4acfd707
BS		 2249 args.nv50.part = NV50_DMA_V0_PART_256;
2250 args.nv50.kind = kind;
2251 size += sizeof(args.nv50);
8a423647 2252 } else
967e7bde 2253 if (drm->device.info.chipset < 0xd0) {
4acfd707
BS		 2254 args.gf100.kind = kind;
2255 size += sizeof(args.gf100);
8a423647 2256 } else {
4acfd707
BS		 2257 args.gf110.page = GF110_DMA_V0_PAGE_LP;
2258 args.gf110.kind = kind;
2259 size += sizeof(args.gf110);
8a423647
BS		 2260 }
2261
2262 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
0ad72863
BS		 2263 struct nv50_head *head = nv50_head(crtc);
2264 int ret = nvif_object_init(&head->sync.base.base.user, NULL,
4acfd707 2265 name, NV_DMA_IN_MEMORY, &args, size,
0ad72863 2266 &fbdma->base[head->base.index]);
8a423647 2267 if (ret) {
0ad72863 2268 nv50_fbdma_fini(fbdma);
8a423647
BS		 2269 return ret;
2270 }
2271 }
2272
0ad72863 2273 ret = nvif_object_init(&mast->base.base.user, NULL, name,
4acfd707 2274 NV_DMA_IN_MEMORY, &args, size,
0ad72863 2275 &fbdma->core);
8a423647 2276 if (ret) {
0ad72863 2277 nv50_fbdma_fini(fbdma);
8a423647
BS		 2278 return ret;
2279 }
2280
2281 return 0;
2282}
2283
ab0af559
BS		 2284static void
2285nv50_fb_dtor(struct drm_framebuffer *fb)
2286{
2287}
2288
2289static int
2290nv50_fb_ctor(struct drm_framebuffer *fb)
2291{
2292 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2293 struct nouveau_drm *drm = nouveau_drm(fb->dev);
2294 struct nouveau_bo *nvbo = nv_fb->nvbo;
8a423647 2295 struct nv50_disp *disp = nv50_disp(fb->dev);
967e7bde 2296 struct nouveau_fb *pfb = nvkm_fb(&drm->device);
8a423647
BS		 2297 u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2298 u8 tile = nvbo->tile_mode;
ab0af559
BS		 2299
2300 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
2301 NV_ERROR(drm, "framebuffer requires contiguous bo\n");
2302 return -EINVAL;
2303 }
2304
967e7bde 2305 if (drm->device.info.chipset >= 0xc0)
8a423647
BS		 2306 tile >>= 4; /* yep.. */
2307
ab0af559
BS		 2308 switch (fb->depth) {
2309 case 8: nv_fb->r_format = 0x1e00; break;
2310 case 15: nv_fb->r_format = 0xe900; break;
2311 case 16: nv_fb->r_format = 0xe800; break;
2312 case 24:
2313 case 32: nv_fb->r_format = 0xcf00; break;
2314 case 30: nv_fb->r_format = 0xd100; break;
2315 default:
2316 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2317 return -EINVAL;
2318 }
2319
0ad72863 2320 if (disp->disp->oclass < NV84_DISP_CLASS) {
8a423647
BS		 2321 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2322 (fb->pitches[0] | 0x00100000);
2323 nv_fb->r_format |= kind << 16;
2324 } else
0ad72863 2325 if (disp->disp->oclass < NVD0_DISP_CLASS) {
8a423647
BS		 2326 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2327 (fb->pitches[0] | 0x00100000);
ab0af559 2328 } else {
8a423647
BS		 2329 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2330 (fb->pitches[0] | 0x01000000);
ab0af559 2331 }
8a423647 2332 nv_fb->r_handle = 0xffff0000 | kind;
ab0af559 2333
8a423647 2334 return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0, pfb->ram->size, kind);
ab0af559
BS		 2335}
2336
26f6d88b
BS		 2337/******************************************************************************
2338 * Init
2339 *****************************************************************************/
ab0af559 2340
2a44e499 2341void
e225f446 2342nv50_display_fini(struct drm_device *dev)
26f6d88b 2343{
26f6d88b
BS		 2344}
2345
2346int
e225f446 2347nv50_display_init(struct drm_device *dev)
26f6d88b 2348{
9f9bdaaf
BS		 2349 struct nv50_disp *disp = nv50_disp(dev);
2350 struct drm_crtc *crtc;
2351 u32 *push;
2352
2353 push = evo_wait(nv50_mast(dev), 32);
2354 if (!push)
2355 return -EBUSY;
2356
2357 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2358 struct nv50_sync *sync = nv50_sync(crtc);
2359 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
bdb8c212 2360 }
efd272a7 2361
9f9bdaaf 2362 evo_mthd(push, 0x0088, 1);
f45f55c4 2363 evo_data(push, nv50_mast(dev)->base.sync.handle);
9f9bdaaf
BS		 2364 evo_kick(push, nv50_mast(dev));
2365 return 0;
26f6d88b
BS		 2366}
2367
2368void
e225f446 2369nv50_display_destroy(struct drm_device *dev)
26f6d88b 2370{
e225f446 2371 struct nv50_disp *disp = nv50_disp(dev);
8a423647
BS		 2372 struct nv50_fbdma *fbdma, *fbtmp;
2373
2374 list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
0ad72863 2375 nv50_fbdma_fini(fbdma);
8a423647 2376 }
bdb8c212 2377
0ad72863 2378 nv50_dmac_destroy(&disp->mast.base, disp->disp);
26f6d88b 2379
816af2f2 2380 nouveau_bo_unmap(disp->sync);
04c8c210
MS		 2381 if (disp->sync)
2382 nouveau_bo_unpin(disp->sync);
816af2f2 2383 nouveau_bo_ref(NULL, &disp->sync);
51beb428 2384
77145f1c 2385 nouveau_display(dev)->priv = NULL;
26f6d88b
BS		 2386 kfree(disp);
2387}
2388
2389int
e225f446 2390nv50_display_create(struct drm_device *dev)
26f6d88b 2391{
967e7bde 2392 struct nvif_device *device = &nouveau_drm(dev)->device;
77145f1c 2393 struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c 2394 struct dcb_table *dcb = &drm->vbios.dcb;
83fc083c 2395 struct drm_connector *connector, *tmp;
e225f446 2396 struct nv50_disp *disp;
cb75d97e 2397 struct dcb_output *dcbe;
7c5f6a87 2398 int crtcs, ret, i;
26f6d88b
BS		 2399
2400 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2401 if (!disp)
2402 return -ENOMEM;
8a423647 2403 INIT_LIST_HEAD(&disp->fbdma);
77145f1c
BS		 2404
2405 nouveau_display(dev)->priv = disp;
e225f446
BS		 2406 nouveau_display(dev)->dtor = nv50_display_destroy;
2407 nouveau_display(dev)->init = nv50_display_init;
2408 nouveau_display(dev)->fini = nv50_display_fini;
ab0af559
BS		 2409 nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2410 nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
0ad72863 2411 disp->disp = &nouveau_display(dev)->disp;
26f6d88b 2412
b5a794b0
BS		 2413 /* small shared memory area we use for notifiers and semaphores */
2414 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2415 0, 0x0000, NULL, &disp->sync);
2416 if (!ret) {
2417 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
04c8c210 2418 if (!ret) {
b5a794b0 2419 ret = nouveau_bo_map(disp->sync);
04c8c210
MS		 2420 if (ret)
2421 nouveau_bo_unpin(disp->sync);
2422 }
b5a794b0
BS		 2423 if (ret)
2424 nouveau_bo_ref(NULL, &disp->sync);
2425 }
2426
b5a794b0
BS		 2427 if (ret)
2428 goto out;
2429
2430 /* allocate master evo channel */
410f3ec6
BS		 2431 ret = nv50_core_create(disp->disp, disp->sync->bo.offset,
2432 &disp->mast);
b5a794b0
BS		 2433 if (ret)
2434 goto out;
2435
438d99e3 2436 /* create crtc objects to represent the hw heads */
0ad72863 2437 if (disp->disp->oclass >= NVD0_DISP_CLASS)
db2bec18 2438 crtcs = nvif_rd32(device, 0x022448);
63718a07
BS		 2439 else
2440 crtcs = 2;
2441
7c5f6a87 2442 for (i = 0; i < crtcs; i++) {
0ad72863 2443 ret = nv50_crtc_create(dev, i);
438d99e3
BS		 2444 if (ret)
2445 goto out;
2446 }
2447
83fc083c
BS		 2448 /* create encoder/connector objects based on VBIOS DCB table */
2449 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2450 connector = nouveau_connector_create(dev, dcbe->connector);
2451 if (IS_ERR(connector))
2452 continue;
2453
eb6313ad
BS		 2454 if (dcbe->location == DCB_LOC_ON_CHIP) {
2455 switch (dcbe->type) {
2456 case DCB_OUTPUT_TMDS:
2457 case DCB_OUTPUT_LVDS:
2458 case DCB_OUTPUT_DP:
2459 ret = nv50_sor_create(connector, dcbe);
2460 break;
2461 case DCB_OUTPUT_ANALOG:
2462 ret = nv50_dac_create(connector, dcbe);
2463 break;
2464 default:
2465 ret = -ENODEV;
2466 break;
2467 }
2468 } else {
2469 ret = nv50_pior_create(connector, dcbe);
83fc083c
BS		 2470 }
2471
eb6313ad
BS		 2472 if (ret) {
2473 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2474 dcbe->location, dcbe->type,
2475 ffs(dcbe->or) - 1, ret);
94f54f53 2476 ret = 0;
83fc083c
BS		 2477 }
2478 }
2479
2480 /* cull any connectors we created that don't have an encoder */
2481 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2482 if (connector->encoder_ids[0])
2483 continue;
2484
77145f1c 2485 NV_WARN(drm, "%s has no encoders, removing\n",
8c6c361a 2486 connector->name);
83fc083c
BS		 2487 connector->funcs->destroy(connector);
2488 }
2489
26f6d88b
BS		 2490out:
2491 if (ret)
e225f446 2492 nv50_display_destroy(dev);
26f6d88b
BS		 2493 return ret;
2494}
Linux 6.x block layer and io_uring tree(s)