Commit | Line | Data |
---|---|---|
56d237d2 | 1 | /* |
26f6d88b BS |
2 | * Copyright 2011 Red Hat Inc. |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
83fc083c | 26 | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/drm_crtc_helper.h> | |
3cb9ae4f | 29 | #include <drm/drm_plane_helper.h> |
4874322e | 30 | #include <drm/drm_dp_helper.h> |
b516a9ef | 31 | #include <drm/drm_fb_helper.h> |
26f6d88b | 32 | |
fdb751ef BS |
33 | #include <nvif/class.h> |
34 | ||
77145f1c BS |
35 | #include "nouveau_drm.h" |
36 | #include "nouveau_dma.h" | |
37 | #include "nouveau_gem.h" | |
26f6d88b BS |
38 | #include "nouveau_connector.h" |
39 | #include "nouveau_encoder.h" | |
40 | #include "nouveau_crtc.h" | |
f589be88 | 41 | #include "nouveau_fence.h" |
3a89cd02 | 42 | #include "nv50_display.h" |
26f6d88b | 43 | |
8a46438a BS |
44 | #define EVO_DMA_NR 9 |
45 | ||
bdb8c212 | 46 | #define EVO_MASTER (0x00) |
a63a97eb | 47 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
48 | #define EVO_OVLY(c) (0x05 + (c)) |
49 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
50 | #define EVO_CURS(c) (0x0d + (c)) |
51 | ||
816af2f2 BS |
52 | /* offsets in shared sync bo of various structures */ |
53 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
9f9bdaaf BS |
54 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
55 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) | |
56 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) | |
816af2f2 | 57 | |
b5a794b0 BS |
58 | /****************************************************************************** |
59 | * EVO channel | |
60 | *****************************************************************************/ | |
61 | ||
e225f446 | 62 | struct nv50_chan { |
0ad72863 | 63 | struct nvif_object user; |
a01ca78c | 64 | struct nvif_device *device; |
b5a794b0 BS |
65 | }; |
66 | ||
67 | static int | |
a01ca78c | 68 | nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 69 | const s32 *oclass, u8 head, void *data, u32 size, |
a01ca78c | 70 | struct nv50_chan *chan) |
b5a794b0 | 71 | { |
41a63406 BS |
72 | struct nvif_sclass *sclass; |
73 | int ret, i, n; | |
6af5289e | 74 | |
a01ca78c BS |
75 | chan->device = device; |
76 | ||
41a63406 | 77 | ret = n = nvif_object_sclass_get(disp, &sclass); |
6af5289e BS |
78 | if (ret < 0) |
79 | return ret; | |
80 | ||
410f3ec6 | 81 | while (oclass[0]) { |
41a63406 BS |
82 | for (i = 0; i < n; i++) { |
83 | if (sclass[i].oclass == oclass[0]) { | |
fcf3f91c | 84 | ret = nvif_object_init(disp, 0, oclass[0], |
a01ca78c | 85 | data, size, &chan->user); |
6af5289e BS |
86 | if (ret == 0) |
87 | nvif_object_map(&chan->user); | |
41a63406 | 88 | nvif_object_sclass_put(&sclass); |
6af5289e BS |
89 | return ret; |
90 | } | |
b76f1529 | 91 | } |
6af5289e | 92 | oclass++; |
410f3ec6 | 93 | } |
6af5289e | 94 | |
41a63406 | 95 | nvif_object_sclass_put(&sclass); |
410f3ec6 | 96 | return -ENOSYS; |
b5a794b0 BS |
97 | } |
98 | ||
99 | static void | |
0ad72863 | 100 | nv50_chan_destroy(struct nv50_chan *chan) |
b5a794b0 | 101 | { |
0ad72863 | 102 | nvif_object_fini(&chan->user); |
b5a794b0 BS |
103 | } |
104 | ||
105 | /****************************************************************************** | |
106 | * PIO EVO channel | |
107 | *****************************************************************************/ | |
108 | ||
e225f446 BS |
109 | struct nv50_pioc { |
110 | struct nv50_chan base; | |
b5a794b0 BS |
111 | }; |
112 | ||
113 | static void | |
0ad72863 | 114 | nv50_pioc_destroy(struct nv50_pioc *pioc) |
b5a794b0 | 115 | { |
0ad72863 | 116 | nv50_chan_destroy(&pioc->base); |
b5a794b0 BS |
117 | } |
118 | ||
119 | static int | |
a01ca78c | 120 | nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 121 | const s32 *oclass, u8 head, void *data, u32 size, |
a01ca78c | 122 | struct nv50_pioc *pioc) |
b5a794b0 | 123 | { |
a01ca78c BS |
124 | return nv50_chan_create(device, disp, oclass, head, data, size, |
125 | &pioc->base); | |
410f3ec6 BS |
126 | } |
127 | ||
128 | /****************************************************************************** | |
129 | * Cursor Immediate | |
130 | *****************************************************************************/ | |
131 | ||
132 | struct nv50_curs { | |
133 | struct nv50_pioc base; | |
134 | }; | |
135 | ||
136 | static int | |
a01ca78c BS |
137 | nv50_curs_create(struct nvif_device *device, struct nvif_object *disp, |
138 | int head, struct nv50_curs *curs) | |
410f3ec6 | 139 | { |
648d4dfd | 140 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
141 | .head = head, |
142 | }; | |
315a8b2e | 143 | static const s32 oclass[] = { |
648d4dfd BS |
144 | GK104_DISP_CURSOR, |
145 | GF110_DISP_CURSOR, | |
146 | GT214_DISP_CURSOR, | |
147 | G82_DISP_CURSOR, | |
148 | NV50_DISP_CURSOR, | |
410f3ec6 BS |
149 | 0 |
150 | }; | |
151 | ||
a01ca78c BS |
152 | return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args), |
153 | &curs->base); | |
410f3ec6 BS |
154 | } |
155 | ||
156 | /****************************************************************************** | |
157 | * Overlay Immediate | |
158 | *****************************************************************************/ | |
159 | ||
160 | struct nv50_oimm { | |
161 | struct nv50_pioc base; | |
162 | }; | |
163 | ||
164 | static int | |
a01ca78c BS |
165 | nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp, |
166 | int head, struct nv50_oimm *oimm) | |
410f3ec6 | 167 | { |
648d4dfd | 168 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
169 | .head = head, |
170 | }; | |
315a8b2e | 171 | static const s32 oclass[] = { |
648d4dfd BS |
172 | GK104_DISP_OVERLAY, |
173 | GF110_DISP_OVERLAY, | |
174 | GT214_DISP_OVERLAY, | |
175 | G82_DISP_OVERLAY, | |
176 | NV50_DISP_OVERLAY, | |
410f3ec6 BS |
177 | 0 |
178 | }; | |
179 | ||
a01ca78c BS |
180 | return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args), |
181 | &oimm->base); | |
b5a794b0 BS |
182 | } |
183 | ||
184 | /****************************************************************************** | |
185 | * DMA EVO channel | |
186 | *****************************************************************************/ | |
187 | ||
e225f446 BS |
188 | struct nv50_dmac { |
189 | struct nv50_chan base; | |
3376ee37 BS |
190 | dma_addr_t handle; |
191 | u32 *ptr; | |
59ad1465 | 192 | |
0ad72863 BS |
193 | struct nvif_object sync; |
194 | struct nvif_object vram; | |
195 | ||
59ad1465 DV |
196 | /* Protects against concurrent pushbuf access to this channel, lock is |
197 | * grabbed by evo_wait (if the pushbuf reservation is successful) and | |
198 | * dropped again by evo_kick. */ | |
199 | struct mutex lock; | |
b5a794b0 BS |
200 | }; |
201 | ||
202 | static void | |
0ad72863 | 203 | nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) |
b5a794b0 | 204 | { |
a01ca78c BS |
205 | struct nvif_device *device = dmac->base.device; |
206 | ||
0ad72863 BS |
207 | nvif_object_fini(&dmac->vram); |
208 | nvif_object_fini(&dmac->sync); | |
209 | ||
210 | nv50_chan_destroy(&dmac->base); | |
211 | ||
b5a794b0 | 212 | if (dmac->ptr) { |
26c9e8ef BS |
213 | struct device *dev = nvxx_device(device)->dev; |
214 | dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle); | |
b5a794b0 | 215 | } |
b5a794b0 BS |
216 | } |
217 | ||
47057302 | 218 | static int |
a01ca78c | 219 | nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 220 | const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, |
e225f446 | 221 | struct nv50_dmac *dmac) |
47057302 | 222 | { |
648d4dfd | 223 | struct nv50_disp_core_channel_dma_v0 *args = data; |
0ad72863 | 224 | struct nvif_object pushbuf; |
47057302 BS |
225 | int ret; |
226 | ||
59ad1465 DV |
227 | mutex_init(&dmac->lock); |
228 | ||
26c9e8ef BS |
229 | dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE, |
230 | &dmac->handle, GFP_KERNEL); | |
47057302 BS |
231 | if (!dmac->ptr) |
232 | return -ENOMEM; | |
233 | ||
fcf3f91c BS |
234 | ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, |
235 | &(struct nv_dma_v0) { | |
4acfd707 BS |
236 | .target = NV_DMA_V0_TARGET_PCI_US, |
237 | .access = NV_DMA_V0_ACCESS_RD, | |
47057302 BS |
238 | .start = dmac->handle + 0x0000, |
239 | .limit = dmac->handle + 0x0fff, | |
4acfd707 | 240 | }, sizeof(struct nv_dma_v0), &pushbuf); |
b5a794b0 | 241 | if (ret) |
47057302 | 242 | return ret; |
b5a794b0 | 243 | |
bf81df9b BS |
244 | args->pushbuf = nvif_handle(&pushbuf); |
245 | ||
a01ca78c BS |
246 | ret = nv50_chan_create(device, disp, oclass, head, data, size, |
247 | &dmac->base); | |
0ad72863 | 248 | nvif_object_fini(&pushbuf); |
47057302 BS |
249 | if (ret) |
250 | return ret; | |
251 | ||
a01ca78c | 252 | ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, |
4acfd707 BS |
253 | &(struct nv_dma_v0) { |
254 | .target = NV_DMA_V0_TARGET_VRAM, | |
255 | .access = NV_DMA_V0_ACCESS_RDWR, | |
47057302 BS |
256 | .start = syncbuf + 0x0000, |
257 | .limit = syncbuf + 0x0fff, | |
4acfd707 | 258 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 259 | &dmac->sync); |
47057302 BS |
260 | if (ret) |
261 | return ret; | |
262 | ||
a01ca78c | 263 | ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, |
4acfd707 BS |
264 | &(struct nv_dma_v0) { |
265 | .target = NV_DMA_V0_TARGET_VRAM, | |
266 | .access = NV_DMA_V0_ACCESS_RDWR, | |
b5a794b0 | 267 | .start = 0, |
f392ec4b | 268 | .limit = device->info.ram_user - 1, |
4acfd707 | 269 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 270 | &dmac->vram); |
b5a794b0 | 271 | if (ret) |
47057302 BS |
272 | return ret; |
273 | ||
b5a794b0 BS |
274 | return ret; |
275 | } | |
276 | ||
410f3ec6 BS |
277 | /****************************************************************************** |
278 | * Core | |
279 | *****************************************************************************/ | |
280 | ||
e225f446 BS |
281 | struct nv50_mast { |
282 | struct nv50_dmac base; | |
b5a794b0 BS |
283 | }; |
284 | ||
410f3ec6 | 285 | static int |
a01ca78c BS |
286 | nv50_core_create(struct nvif_device *device, struct nvif_object *disp, |
287 | u64 syncbuf, struct nv50_mast *core) | |
410f3ec6 | 288 | { |
648d4dfd BS |
289 | struct nv50_disp_core_channel_dma_v0 args = { |
290 | .pushbuf = 0xb0007d00, | |
410f3ec6 | 291 | }; |
315a8b2e | 292 | static const s32 oclass[] = { |
dbbd6bcf | 293 | GM204_DISP_CORE_CHANNEL_DMA, |
648d4dfd BS |
294 | GM107_DISP_CORE_CHANNEL_DMA, |
295 | GK110_DISP_CORE_CHANNEL_DMA, | |
296 | GK104_DISP_CORE_CHANNEL_DMA, | |
297 | GF110_DISP_CORE_CHANNEL_DMA, | |
298 | GT214_DISP_CORE_CHANNEL_DMA, | |
299 | GT206_DISP_CORE_CHANNEL_DMA, | |
300 | GT200_DISP_CORE_CHANNEL_DMA, | |
301 | G82_DISP_CORE_CHANNEL_DMA, | |
302 | NV50_DISP_CORE_CHANNEL_DMA, | |
410f3ec6 BS |
303 | 0 |
304 | }; | |
305 | ||
a01ca78c BS |
306 | return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args), |
307 | syncbuf, &core->base); | |
410f3ec6 BS |
308 | } |
309 | ||
310 | /****************************************************************************** | |
311 | * Base | |
312 | *****************************************************************************/ | |
b5a794b0 | 313 | |
e225f446 BS |
314 | struct nv50_sync { |
315 | struct nv50_dmac base; | |
9f9bdaaf BS |
316 | u32 addr; |
317 | u32 data; | |
3376ee37 BS |
318 | }; |
319 | ||
410f3ec6 | 320 | static int |
a01ca78c BS |
321 | nv50_base_create(struct nvif_device *device, struct nvif_object *disp, |
322 | int head, u64 syncbuf, struct nv50_sync *base) | |
410f3ec6 | 323 | { |
648d4dfd BS |
324 | struct nv50_disp_base_channel_dma_v0 args = { |
325 | .pushbuf = 0xb0007c00 | head, | |
410f3ec6 BS |
326 | .head = head, |
327 | }; | |
315a8b2e | 328 | static const s32 oclass[] = { |
648d4dfd BS |
329 | GK110_DISP_BASE_CHANNEL_DMA, |
330 | GK104_DISP_BASE_CHANNEL_DMA, | |
331 | GF110_DISP_BASE_CHANNEL_DMA, | |
332 | GT214_DISP_BASE_CHANNEL_DMA, | |
333 | GT200_DISP_BASE_CHANNEL_DMA, | |
334 | G82_DISP_BASE_CHANNEL_DMA, | |
335 | NV50_DISP_BASE_CHANNEL_DMA, | |
410f3ec6 BS |
336 | 0 |
337 | }; | |
338 | ||
a01ca78c | 339 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
410f3ec6 BS |
340 | syncbuf, &base->base); |
341 | } | |
342 | ||
343 | /****************************************************************************** | |
344 | * Overlay | |
345 | *****************************************************************************/ | |
346 | ||
e225f446 BS |
347 | struct nv50_ovly { |
348 | struct nv50_dmac base; | |
b5a794b0 | 349 | }; |
f20ce962 | 350 | |
410f3ec6 | 351 | static int |
a01ca78c BS |
352 | nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp, |
353 | int head, u64 syncbuf, struct nv50_ovly *ovly) | |
410f3ec6 | 354 | { |
648d4dfd BS |
355 | struct nv50_disp_overlay_channel_dma_v0 args = { |
356 | .pushbuf = 0xb0007e00 | head, | |
410f3ec6 BS |
357 | .head = head, |
358 | }; | |
315a8b2e | 359 | static const s32 oclass[] = { |
648d4dfd BS |
360 | GK104_DISP_OVERLAY_CONTROL_DMA, |
361 | GF110_DISP_OVERLAY_CONTROL_DMA, | |
362 | GT214_DISP_OVERLAY_CHANNEL_DMA, | |
363 | GT200_DISP_OVERLAY_CHANNEL_DMA, | |
364 | G82_DISP_OVERLAY_CHANNEL_DMA, | |
365 | NV50_DISP_OVERLAY_CHANNEL_DMA, | |
410f3ec6 BS |
366 | 0 |
367 | }; | |
368 | ||
a01ca78c | 369 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
410f3ec6 BS |
370 | syncbuf, &ovly->base); |
371 | } | |
26f6d88b | 372 | |
e225f446 | 373 | struct nv50_head { |
dd0e3d53 | 374 | struct nouveau_crtc base; |
8dda53fc | 375 | struct nouveau_bo *image; |
e225f446 BS |
376 | struct nv50_curs curs; |
377 | struct nv50_sync sync; | |
378 | struct nv50_ovly ovly; | |
379 | struct nv50_oimm oimm; | |
b5a794b0 BS |
380 | }; |
381 | ||
e225f446 BS |
382 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
383 | #define nv50_curs(c) (&nv50_head(c)->curs) | |
384 | #define nv50_sync(c) (&nv50_head(c)->sync) | |
385 | #define nv50_ovly(c) (&nv50_head(c)->ovly) | |
386 | #define nv50_oimm(c) (&nv50_head(c)->oimm) | |
387 | #define nv50_chan(c) (&(c)->base.base) | |
0ad72863 BS |
388 | #define nv50_vers(c) nv50_chan(c)->user.oclass |
389 | ||
390 | struct nv50_fbdma { | |
391 | struct list_head head; | |
392 | struct nvif_object core; | |
393 | struct nvif_object base[4]; | |
394 | }; | |
b5a794b0 | 395 | |
e225f446 | 396 | struct nv50_disp { |
0ad72863 | 397 | struct nvif_object *disp; |
e225f446 | 398 | struct nv50_mast mast; |
b5a794b0 | 399 | |
8a423647 | 400 | struct list_head fbdma; |
b5a794b0 BS |
401 | |
402 | struct nouveau_bo *sync; | |
dd0e3d53 BS |
403 | }; |
404 | ||
e225f446 BS |
405 | static struct nv50_disp * |
406 | nv50_disp(struct drm_device *dev) | |
26f6d88b | 407 | { |
77145f1c | 408 | return nouveau_display(dev)->priv; |
26f6d88b BS |
409 | } |
410 | ||
e225f446 | 411 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
b5a794b0 | 412 | |
bdb8c212 | 413 | static struct drm_crtc * |
e225f446 | 414 | nv50_display_crtc_get(struct drm_encoder *encoder) |
bdb8c212 BS |
415 | { |
416 | return nouveau_encoder(encoder)->crtc; | |
417 | } | |
418 | ||
419 | /****************************************************************************** | |
420 | * EVO channel helpers | |
421 | *****************************************************************************/ | |
51beb428 | 422 | static u32 * |
b5a794b0 | 423 | evo_wait(void *evoc, int nr) |
51beb428 | 424 | { |
e225f446 | 425 | struct nv50_dmac *dmac = evoc; |
a01ca78c | 426 | struct nvif_device *device = dmac->base.device; |
0ad72863 | 427 | u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; |
51beb428 | 428 | |
59ad1465 | 429 | mutex_lock(&dmac->lock); |
de8268c5 | 430 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
b5a794b0 | 431 | dmac->ptr[put] = 0x20000000; |
51beb428 | 432 | |
0ad72863 | 433 | nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); |
54442040 BS |
434 | if (nvif_msec(device, 2000, |
435 | if (!nvif_rd32(&dmac->base.user, 0x0004)) | |
436 | break; | |
437 | ) < 0) { | |
59ad1465 | 438 | mutex_unlock(&dmac->lock); |
9ad97ede | 439 | printk(KERN_ERR "nouveau: evo channel stalled\n"); |
51beb428 BS |
440 | return NULL; |
441 | } | |
442 | ||
443 | put = 0; | |
444 | } | |
445 | ||
b5a794b0 | 446 | return dmac->ptr + put; |
51beb428 BS |
447 | } |
448 | ||
449 | static void | |
b5a794b0 | 450 | evo_kick(u32 *push, void *evoc) |
51beb428 | 451 | { |
e225f446 | 452 | struct nv50_dmac *dmac = evoc; |
0ad72863 | 453 | nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
59ad1465 | 454 | mutex_unlock(&dmac->lock); |
51beb428 BS |
455 | } |
456 | ||
2b1930c3 | 457 | #if 1 |
51beb428 BS |
458 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) |
459 | #define evo_data(p,d) *((p)++) = (d) | |
2b1930c3 BS |
460 | #else |
461 | #define evo_mthd(p,m,s) do { \ | |
462 | const u32 _m = (m), _s = (s); \ | |
463 | printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \ | |
464 | *((p)++) = ((_s << 18) | _m); \ | |
465 | } while(0) | |
466 | #define evo_data(p,d) do { \ | |
467 | const u32 _d = (d); \ | |
468 | printk(KERN_ERR "\t%08x\n", _d); \ | |
469 | *((p)++) = _d; \ | |
470 | } while(0) | |
471 | #endif | |
51beb428 | 472 | |
3376ee37 BS |
473 | static bool |
474 | evo_sync_wait(void *data) | |
475 | { | |
5cc027f6 BS |
476 | if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) |
477 | return true; | |
478 | usleep_range(1, 2); | |
479 | return false; | |
3376ee37 BS |
480 | } |
481 | ||
482 | static int | |
b5a794b0 | 483 | evo_sync(struct drm_device *dev) |
3376ee37 | 484 | { |
967e7bde | 485 | struct nvif_device *device = &nouveau_drm(dev)->device; |
e225f446 BS |
486 | struct nv50_disp *disp = nv50_disp(dev); |
487 | struct nv50_mast *mast = nv50_mast(dev); | |
b5a794b0 | 488 | u32 *push = evo_wait(mast, 8); |
3376ee37 | 489 | if (push) { |
816af2f2 | 490 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
3376ee37 | 491 | evo_mthd(push, 0x0084, 1); |
816af2f2 | 492 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
3376ee37 BS |
493 | evo_mthd(push, 0x0080, 2); |
494 | evo_data(push, 0x00000000); | |
495 | evo_data(push, 0x00000000); | |
b5a794b0 | 496 | evo_kick(push, mast); |
54442040 BS |
497 | if (nvif_msec(device, 2000, |
498 | if (evo_sync_wait(disp->sync)) | |
499 | break; | |
500 | ) >= 0) | |
3376ee37 BS |
501 | return 0; |
502 | } | |
503 | ||
504 | return -EBUSY; | |
505 | } | |
506 | ||
507 | /****************************************************************************** | |
a63a97eb | 508 | * Page flipping channel |
3376ee37 BS |
509 | *****************************************************************************/ |
510 | struct nouveau_bo * | |
e225f446 | 511 | nv50_display_crtc_sema(struct drm_device *dev, int crtc) |
3376ee37 | 512 | { |
e225f446 | 513 | return nv50_disp(dev)->sync; |
3376ee37 BS |
514 | } |
515 | ||
9f9bdaaf BS |
516 | struct nv50_display_flip { |
517 | struct nv50_disp *disp; | |
518 | struct nv50_sync *chan; | |
519 | }; | |
520 | ||
521 | static bool | |
522 | nv50_display_flip_wait(void *data) | |
523 | { | |
524 | struct nv50_display_flip *flip = data; | |
525 | if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == | |
b1ea3e6e | 526 | flip->chan->data) |
9f9bdaaf BS |
527 | return true; |
528 | usleep_range(1, 2); | |
529 | return false; | |
530 | } | |
531 | ||
3376ee37 | 532 | void |
e225f446 | 533 | nv50_display_flip_stop(struct drm_crtc *crtc) |
3376ee37 | 534 | { |
967e7bde | 535 | struct nvif_device *device = &nouveau_drm(crtc->dev)->device; |
9f9bdaaf BS |
536 | struct nv50_display_flip flip = { |
537 | .disp = nv50_disp(crtc->dev), | |
538 | .chan = nv50_sync(crtc), | |
539 | }; | |
3376ee37 BS |
540 | u32 *push; |
541 | ||
9f9bdaaf | 542 | push = evo_wait(flip.chan, 8); |
3376ee37 BS |
543 | if (push) { |
544 | evo_mthd(push, 0x0084, 1); | |
545 | evo_data(push, 0x00000000); | |
546 | evo_mthd(push, 0x0094, 1); | |
547 | evo_data(push, 0x00000000); | |
548 | evo_mthd(push, 0x00c0, 1); | |
549 | evo_data(push, 0x00000000); | |
550 | evo_mthd(push, 0x0080, 1); | |
551 | evo_data(push, 0x00000000); | |
9f9bdaaf | 552 | evo_kick(push, flip.chan); |
3376ee37 | 553 | } |
9f9bdaaf | 554 | |
54442040 BS |
555 | nvif_msec(device, 2000, |
556 | if (nv50_display_flip_wait(&flip)) | |
557 | break; | |
558 | ); | |
3376ee37 BS |
559 | } |
560 | ||
561 | int | |
e225f446 | 562 | nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
3376ee37 BS |
563 | struct nouveau_channel *chan, u32 swap_interval) |
564 | { | |
565 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
3376ee37 | 566 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
8dda53fc | 567 | struct nv50_head *head = nv50_head(crtc); |
e225f446 | 568 | struct nv50_sync *sync = nv50_sync(crtc); |
3376ee37 | 569 | u32 *push; |
8dda53fc | 570 | int ret; |
3376ee37 | 571 | |
9ba83106 BS |
572 | if (crtc->primary->fb->width != fb->width || |
573 | crtc->primary->fb->height != fb->height) | |
574 | return -EINVAL; | |
575 | ||
3376ee37 BS |
576 | swap_interval <<= 4; |
577 | if (swap_interval == 0) | |
578 | swap_interval |= 0x100; | |
f60b6e7a BS |
579 | if (chan == NULL) |
580 | evo_sync(crtc->dev); | |
3376ee37 | 581 | |
b5a794b0 | 582 | push = evo_wait(sync, 128); |
3376ee37 BS |
583 | if (unlikely(push == NULL)) |
584 | return -EBUSY; | |
585 | ||
a01ca78c | 586 | if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) { |
9f9bdaaf BS |
587 | ret = RING_SPACE(chan, 8); |
588 | if (ret) | |
589 | return ret; | |
590 | ||
591 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); | |
8dda53fc | 592 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); |
9f9bdaaf BS |
593 | OUT_RING (chan, sync->addr ^ 0x10); |
594 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); | |
595 | OUT_RING (chan, sync->data + 1); | |
596 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); | |
597 | OUT_RING (chan, sync->addr); | |
598 | OUT_RING (chan, sync->data); | |
599 | } else | |
a01ca78c | 600 | if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) { |
8dda53fc | 601 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
602 | ret = RING_SPACE(chan, 12); |
603 | if (ret) | |
604 | return ret; | |
605 | ||
606 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
0ad72863 | 607 | OUT_RING (chan, chan->vram.handle); |
9f9bdaaf BS |
608 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
609 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
610 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
611 | OUT_RING (chan, sync->data + 1); | |
612 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
613 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
614 | OUT_RING (chan, upper_32_bits(addr)); | |
615 | OUT_RING (chan, lower_32_bits(addr)); | |
616 | OUT_RING (chan, sync->data); | |
617 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); | |
618 | } else | |
619 | if (chan) { | |
8dda53fc | 620 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
621 | ret = RING_SPACE(chan, 10); |
622 | if (ret) | |
623 | return ret; | |
624 | ||
625 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
626 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
627 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
628 | OUT_RING (chan, sync->data + 1); | |
629 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | | |
630 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
631 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
632 | OUT_RING (chan, upper_32_bits(addr)); | |
633 | OUT_RING (chan, lower_32_bits(addr)); | |
634 | OUT_RING (chan, sync->data); | |
635 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | | |
636 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
637 | } | |
35bcf5d5 | 638 | |
9f9bdaaf BS |
639 | if (chan) { |
640 | sync->addr ^= 0x10; | |
641 | sync->data++; | |
3376ee37 | 642 | FIRE_RING (chan); |
3376ee37 BS |
643 | } |
644 | ||
645 | /* queue the flip */ | |
646 | evo_mthd(push, 0x0100, 1); | |
647 | evo_data(push, 0xfffe0000); | |
648 | evo_mthd(push, 0x0084, 1); | |
649 | evo_data(push, swap_interval); | |
650 | if (!(swap_interval & 0x00000100)) { | |
651 | evo_mthd(push, 0x00e0, 1); | |
652 | evo_data(push, 0x40000000); | |
653 | } | |
654 | evo_mthd(push, 0x0088, 4); | |
9f9bdaaf BS |
655 | evo_data(push, sync->addr); |
656 | evo_data(push, sync->data++); | |
657 | evo_data(push, sync->data); | |
f45f55c4 | 658 | evo_data(push, sync->base.sync.handle); |
3376ee37 BS |
659 | evo_mthd(push, 0x00a0, 2); |
660 | evo_data(push, 0x00000000); | |
661 | evo_data(push, 0x00000000); | |
662 | evo_mthd(push, 0x00c0, 1); | |
8a423647 | 663 | evo_data(push, nv_fb->r_handle); |
3376ee37 BS |
664 | evo_mthd(push, 0x0110, 2); |
665 | evo_data(push, 0x00000000); | |
666 | evo_data(push, 0x00000000); | |
648d4dfd | 667 | if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) { |
ed5085a5 BS |
668 | evo_mthd(push, 0x0800, 5); |
669 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
670 | evo_data(push, 0); | |
671 | evo_data(push, (fb->height << 16) | fb->width); | |
672 | evo_data(push, nv_fb->r_pitch); | |
673 | evo_data(push, nv_fb->r_format); | |
674 | } else { | |
675 | evo_mthd(push, 0x0400, 5); | |
676 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
677 | evo_data(push, 0); | |
678 | evo_data(push, (fb->height << 16) | fb->width); | |
679 | evo_data(push, nv_fb->r_pitch); | |
680 | evo_data(push, nv_fb->r_format); | |
681 | } | |
3376ee37 BS |
682 | evo_mthd(push, 0x0080, 1); |
683 | evo_data(push, 0x00000000); | |
b5a794b0 | 684 | evo_kick(push, sync); |
8dda53fc BS |
685 | |
686 | nouveau_bo_ref(nv_fb->nvbo, &head->image); | |
3376ee37 BS |
687 | return 0; |
688 | } | |
689 | ||
438d99e3 BS |
690 | /****************************************************************************** |
691 | * CRTC | |
692 | *****************************************************************************/ | |
693 | static int | |
e225f446 | 694 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 695 | { |
e225f446 | 696 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de691855 BS |
697 | struct nouveau_connector *nv_connector; |
698 | struct drm_connector *connector; | |
699 | u32 *push, mode = 0x00; | |
438d99e3 | 700 | |
488ff207 | 701 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
de691855 BS |
702 | connector = &nv_connector->base; |
703 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
f4510a27 | 704 | if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) |
de691855 BS |
705 | mode = DITHERING_MODE_DYNAMIC2X2; |
706 | } else { | |
707 | mode = nv_connector->dithering_mode; | |
708 | } | |
709 | ||
710 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { | |
711 | if (connector->display_info.bpc >= 8) | |
712 | mode |= DITHERING_DEPTH_8BPC; | |
713 | } else { | |
714 | mode |= nv_connector->dithering_depth; | |
438d99e3 BS |
715 | } |
716 | ||
de8268c5 | 717 | push = evo_wait(mast, 4); |
438d99e3 | 718 | if (push) { |
648d4dfd | 719 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
720 | evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); |
721 | evo_data(push, mode); | |
722 | } else | |
648d4dfd | 723 | if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
724 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); |
725 | evo_data(push, mode); | |
726 | } else { | |
727 | evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); | |
728 | evo_data(push, mode); | |
729 | } | |
730 | ||
438d99e3 BS |
731 | if (update) { |
732 | evo_mthd(push, 0x0080, 1); | |
733 | evo_data(push, 0x00000000); | |
734 | } | |
de8268c5 | 735 | evo_kick(push, mast); |
438d99e3 BS |
736 | } |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
741 | static int | |
e225f446 | 742 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 743 | { |
e225f446 | 744 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
92854622 | 745 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
3376ee37 | 746 | struct drm_crtc *crtc = &nv_crtc->base; |
f3fdc52d | 747 | struct nouveau_connector *nv_connector; |
92854622 BS |
748 | int mode = DRM_MODE_SCALE_NONE; |
749 | u32 oX, oY, *push; | |
f3fdc52d | 750 | |
92854622 BS |
751 | /* start off at the resolution we programmed the crtc for, this |
752 | * effectively handles NONE/FULL scaling | |
753 | */ | |
f3fdc52d | 754 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
576f7911 | 755 | if (nv_connector && nv_connector->native_mode) { |
92854622 | 756 | mode = nv_connector->scaling_mode; |
576f7911 BS |
757 | if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */ |
758 | mode = DRM_MODE_SCALE_FULLSCREEN; | |
759 | } | |
92854622 BS |
760 | |
761 | if (mode != DRM_MODE_SCALE_NONE) | |
762 | omode = nv_connector->native_mode; | |
763 | else | |
764 | omode = umode; | |
765 | ||
766 | oX = omode->hdisplay; | |
767 | oY = omode->vdisplay; | |
768 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
769 | oY *= 2; | |
770 | ||
771 | /* add overscan compensation if necessary, will keep the aspect | |
772 | * ratio the same as the backend mode unless overridden by the | |
773 | * user setting both hborder and vborder properties. | |
774 | */ | |
775 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
776 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
777 | nv_connector->edid && | |
778 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
779 | u32 bX = nv_connector->underscan_hborder; | |
780 | u32 bY = nv_connector->underscan_vborder; | |
781 | u32 aspect = (oY << 19) / oX; | |
782 | ||
783 | if (bX) { | |
784 | oX -= (bX * 2); | |
785 | if (bY) oY -= (bY * 2); | |
786 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
787 | } else { | |
788 | oX -= (oX >> 4) + 32; | |
789 | if (bY) oY -= (bY * 2); | |
790 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
791 | } | |
792 | } | |
793 | ||
794 | /* handle CENTER/ASPECT scaling, taking into account the areas | |
795 | * removed already for overscan compensation | |
796 | */ | |
797 | switch (mode) { | |
798 | case DRM_MODE_SCALE_CENTER: | |
799 | oX = min((u32)umode->hdisplay, oX); | |
800 | oY = min((u32)umode->vdisplay, oY); | |
801 | /* fall-through */ | |
802 | case DRM_MODE_SCALE_ASPECT: | |
803 | if (oY < oX) { | |
804 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; | |
805 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
806 | } else { | |
807 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; | |
808 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
f3fdc52d | 809 | } |
92854622 BS |
810 | break; |
811 | default: | |
812 | break; | |
f3fdc52d | 813 | } |
438d99e3 | 814 | |
de8268c5 | 815 | push = evo_wait(mast, 8); |
438d99e3 | 816 | if (push) { |
648d4dfd | 817 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
818 | /*XXX: SCALE_CTRL_ACTIVE??? */ |
819 | evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); | |
820 | evo_data(push, (oY << 16) | oX); | |
821 | evo_data(push, (oY << 16) | oX); | |
822 | evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); | |
823 | evo_data(push, 0x00000000); | |
824 | evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); | |
825 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
826 | } else { | |
827 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); | |
828 | evo_data(push, (oY << 16) | oX); | |
829 | evo_data(push, (oY << 16) | oX); | |
830 | evo_data(push, (oY << 16) | oX); | |
831 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); | |
832 | evo_data(push, 0x00000000); | |
833 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); | |
834 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
835 | } | |
836 | ||
837 | evo_kick(push, mast); | |
838 | ||
438d99e3 | 839 | if (update) { |
e225f446 | 840 | nv50_display_flip_stop(crtc); |
f4510a27 MR |
841 | nv50_display_flip_next(crtc, crtc->primary->fb, |
842 | NULL, 1); | |
438d99e3 | 843 | } |
438d99e3 BS |
844 | } |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
eae7382b RS |
849 | static int |
850 | nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec) | |
851 | { | |
852 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); | |
853 | u32 *push; | |
854 | ||
855 | push = evo_wait(mast, 8); | |
856 | if (!push) | |
857 | return -ENOMEM; | |
858 | ||
859 | evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1); | |
860 | evo_data(push, usec); | |
861 | evo_kick(push, mast); | |
862 | return 0; | |
863 | } | |
864 | ||
f9887d09 | 865 | static int |
e225f446 | 866 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
f9887d09 | 867 | { |
e225f446 | 868 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
f9887d09 BS |
869 | u32 *push, hue, vib; |
870 | int adj; | |
871 | ||
872 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; | |
873 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; | |
874 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; | |
875 | ||
876 | push = evo_wait(mast, 16); | |
877 | if (push) { | |
648d4dfd | 878 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
f9887d09 BS |
879 | evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); |
880 | evo_data(push, (hue << 20) | (vib << 8)); | |
881 | } else { | |
882 | evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); | |
883 | evo_data(push, (hue << 20) | (vib << 8)); | |
884 | } | |
885 | ||
886 | if (update) { | |
887 | evo_mthd(push, 0x0080, 1); | |
888 | evo_data(push, 0x00000000); | |
889 | } | |
890 | evo_kick(push, mast); | |
891 | } | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
438d99e3 | 896 | static int |
e225f446 | 897 | nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, |
438d99e3 BS |
898 | int x, int y, bool update) |
899 | { | |
900 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); | |
e225f446 | 901 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
438d99e3 BS |
902 | u32 *push; |
903 | ||
de8268c5 | 904 | push = evo_wait(mast, 16); |
438d99e3 | 905 | if (push) { |
648d4dfd | 906 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
907 | evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); |
908 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
909 | evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); | |
910 | evo_data(push, (fb->height << 16) | fb->width); | |
911 | evo_data(push, nvfb->r_pitch); | |
912 | evo_data(push, nvfb->r_format); | |
913 | evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); | |
914 | evo_data(push, (y << 16) | x); | |
648d4dfd | 915 | if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 916 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 917 | evo_data(push, nvfb->r_handle); |
de8268c5 BS |
918 | } |
919 | } else { | |
920 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); | |
921 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
922 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); | |
923 | evo_data(push, (fb->height << 16) | fb->width); | |
924 | evo_data(push, nvfb->r_pitch); | |
925 | evo_data(push, nvfb->r_format); | |
8a423647 | 926 | evo_data(push, nvfb->r_handle); |
de8268c5 BS |
927 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); |
928 | evo_data(push, (y << 16) | x); | |
929 | } | |
930 | ||
a46232ee BS |
931 | if (update) { |
932 | evo_mthd(push, 0x0080, 1); | |
933 | evo_data(push, 0x00000000); | |
934 | } | |
de8268c5 | 935 | evo_kick(push, mast); |
438d99e3 BS |
936 | } |
937 | ||
8a423647 | 938 | nv_crtc->fb.handle = nvfb->r_handle; |
438d99e3 BS |
939 | return 0; |
940 | } | |
941 | ||
942 | static void | |
e225f446 | 943 | nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) |
438d99e3 | 944 | { |
e225f446 | 945 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 | 946 | u32 *push = evo_wait(mast, 16); |
438d99e3 | 947 | if (push) { |
648d4dfd | 948 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
949 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
950 | evo_data(push, 0x85000000); | |
4dc63933 | 951 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
de8268c5 | 952 | } else |
648d4dfd | 953 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
954 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
955 | evo_data(push, 0x85000000); | |
4dc63933 | 956 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
de8268c5 | 957 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); |
f45f55c4 | 958 | evo_data(push, mast->base.vram.handle); |
de8268c5 | 959 | } else { |
438d99e3 BS |
960 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
961 | evo_data(push, 0x85000000); | |
4dc63933 | 962 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
438d99e3 | 963 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); |
f45f55c4 | 964 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
965 | } |
966 | evo_kick(push, mast); | |
967 | } | |
4dc63933 | 968 | nv_crtc->cursor.visible = true; |
de8268c5 BS |
969 | } |
970 | ||
971 | static void | |
e225f446 | 972 | nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) |
de8268c5 | 973 | { |
e225f446 | 974 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
975 | u32 *push = evo_wait(mast, 16); |
976 | if (push) { | |
648d4dfd | 977 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
978 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
979 | evo_data(push, 0x05000000); | |
980 | } else | |
648d4dfd | 981 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
982 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
983 | evo_data(push, 0x05000000); | |
984 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
985 | evo_data(push, 0x00000000); | |
438d99e3 BS |
986 | } else { |
987 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); | |
988 | evo_data(push, 0x05000000); | |
989 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
990 | evo_data(push, 0x00000000); | |
991 | } | |
de8268c5 BS |
992 | evo_kick(push, mast); |
993 | } | |
4dc63933 | 994 | nv_crtc->cursor.visible = false; |
de8268c5 | 995 | } |
438d99e3 | 996 | |
de8268c5 | 997 | static void |
e225f446 | 998 | nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) |
de8268c5 | 999 | { |
e225f446 | 1000 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 | 1001 | |
697bb728 | 1002 | if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled) |
e225f446 | 1003 | nv50_crtc_cursor_show(nv_crtc); |
de8268c5 | 1004 | else |
e225f446 | 1005 | nv50_crtc_cursor_hide(nv_crtc); |
de8268c5 BS |
1006 | |
1007 | if (update) { | |
1008 | u32 *push = evo_wait(mast, 2); | |
1009 | if (push) { | |
438d99e3 BS |
1010 | evo_mthd(push, 0x0080, 1); |
1011 | evo_data(push, 0x00000000); | |
de8268c5 | 1012 | evo_kick(push, mast); |
438d99e3 | 1013 | } |
438d99e3 BS |
1014 | } |
1015 | } | |
1016 | ||
1017 | static void | |
e225f446 | 1018 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
438d99e3 BS |
1019 | { |
1020 | } | |
1021 | ||
1022 | static void | |
e225f446 | 1023 | nv50_crtc_prepare(struct drm_crtc *crtc) |
438d99e3 BS |
1024 | { |
1025 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 1026 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1027 | u32 *push; |
1028 | ||
e225f446 | 1029 | nv50_display_flip_stop(crtc); |
3376ee37 | 1030 | |
56d237d2 | 1031 | push = evo_wait(mast, 6); |
438d99e3 | 1032 | if (push) { |
648d4dfd | 1033 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
1034 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1035 | evo_data(push, 0x00000000); | |
1036 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
1037 | evo_data(push, 0x40000000); | |
1038 | } else | |
648d4dfd | 1039 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
1040 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1041 | evo_data(push, 0x00000000); | |
1042 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
1043 | evo_data(push, 0x40000000); | |
1044 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
1045 | evo_data(push, 0x00000000); | |
1046 | } else { | |
1047 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
1048 | evo_data(push, 0x00000000); | |
1049 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); | |
1050 | evo_data(push, 0x03000000); | |
1051 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
1052 | evo_data(push, 0x00000000); | |
1053 | } | |
1054 | ||
1055 | evo_kick(push, mast); | |
438d99e3 BS |
1056 | } |
1057 | ||
e225f446 | 1058 | nv50_crtc_cursor_show_hide(nv_crtc, false, false); |
438d99e3 BS |
1059 | } |
1060 | ||
1061 | static void | |
e225f446 | 1062 | nv50_crtc_commit(struct drm_crtc *crtc) |
438d99e3 BS |
1063 | { |
1064 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 1065 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1066 | u32 *push; |
1067 | ||
de8268c5 | 1068 | push = evo_wait(mast, 32); |
438d99e3 | 1069 | if (push) { |
648d4dfd | 1070 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 1071 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 1072 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1073 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1074 | evo_data(push, 0xc0000000); | |
1075 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1076 | } else | |
648d4dfd | 1077 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 1078 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 1079 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1080 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1081 | evo_data(push, 0xc0000000); | |
1082 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1083 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
f45f55c4 | 1084 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
1085 | } else { |
1086 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
8a423647 | 1087 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1088 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); |
1089 | evo_data(push, 0x83000000); | |
1090 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1091 | evo_data(push, 0x00000000); | |
1092 | evo_data(push, 0x00000000); | |
1093 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
f45f55c4 | 1094 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
1095 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); |
1096 | evo_data(push, 0xffffff00); | |
1097 | } | |
1098 | ||
1099 | evo_kick(push, mast); | |
438d99e3 BS |
1100 | } |
1101 | ||
5a560252 | 1102 | nv50_crtc_cursor_show_hide(nv_crtc, true, true); |
f4510a27 | 1103 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
438d99e3 BS |
1104 | } |
1105 | ||
1106 | static bool | |
e225f446 | 1107 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
438d99e3 BS |
1108 | struct drm_display_mode *adjusted_mode) |
1109 | { | |
eb2e9686 | 1110 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
438d99e3 BS |
1111 | return true; |
1112 | } | |
1113 | ||
1114 | static int | |
e225f446 | 1115 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
438d99e3 | 1116 | { |
f4510a27 | 1117 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
8dda53fc | 1118 | struct nv50_head *head = nv50_head(crtc); |
438d99e3 BS |
1119 | int ret; |
1120 | ||
547ad072 | 1121 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true); |
8dda53fc BS |
1122 | if (ret == 0) { |
1123 | if (head->image) | |
1124 | nouveau_bo_unpin(head->image); | |
1125 | nouveau_bo_ref(nvfb->nvbo, &head->image); | |
438d99e3 BS |
1126 | } |
1127 | ||
8dda53fc | 1128 | return ret; |
438d99e3 BS |
1129 | } |
1130 | ||
1131 | static int | |
e225f446 | 1132 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
438d99e3 BS |
1133 | struct drm_display_mode *mode, int x, int y, |
1134 | struct drm_framebuffer *old_fb) | |
1135 | { | |
e225f446 | 1136 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1137 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1138 | struct nouveau_connector *nv_connector; | |
2d1d898b BS |
1139 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
1140 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
1141 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; | |
1142 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; | |
1dce6264 | 1143 | u32 vblan2e = 0, vblan2s = 1, vblankus = 0; |
3488c57b | 1144 | u32 *push; |
438d99e3 BS |
1145 | int ret; |
1146 | ||
2d1d898b BS |
1147 | hactive = mode->htotal; |
1148 | hsynce = mode->hsync_end - mode->hsync_start - 1; | |
1149 | hbackp = mode->htotal - mode->hsync_end; | |
1150 | hblanke = hsynce + hbackp; | |
1151 | hfrontp = mode->hsync_start - mode->hdisplay; | |
1152 | hblanks = mode->htotal - hfrontp - 1; | |
1153 | ||
1154 | vactive = mode->vtotal * vscan / ilace; | |
1155 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
1156 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
1157 | vblanke = vsynce + vbackp; | |
1158 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
1159 | vblanks = vactive - vfrontp - 1; | |
1dce6264 RS |
1160 | /* XXX: Safe underestimate, even "0" works */ |
1161 | vblankus = (vactive - mode->vdisplay - 2) * hactive; | |
1162 | vblankus *= 1000; | |
1163 | vblankus /= mode->clock; | |
1164 | ||
2d1d898b BS |
1165 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
1166 | vblan2e = vactive + vsynce + vbackp; | |
1167 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); | |
1168 | vactive = (vactive * 2) + 1; | |
2d1d898b BS |
1169 | } |
1170 | ||
e225f446 | 1171 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1172 | if (ret) |
1173 | return ret; | |
1174 | ||
de8268c5 | 1175 | push = evo_wait(mast, 64); |
438d99e3 | 1176 | if (push) { |
648d4dfd | 1177 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
1178 | evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); |
1179 | evo_data(push, 0x00800000 | mode->clock); | |
1180 | evo_data(push, (ilace == 2) ? 2 : 0); | |
eae7382b | 1181 | evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6); |
de8268c5 BS |
1182 | evo_data(push, 0x00000000); |
1183 | evo_data(push, (vactive << 16) | hactive); | |
1184 | evo_data(push, ( vsynce << 16) | hsynce); | |
1185 | evo_data(push, (vblanke << 16) | hblanke); | |
1186 | evo_data(push, (vblanks << 16) | hblanks); | |
1187 | evo_data(push, (vblan2e << 16) | vblan2s); | |
eae7382b | 1188 | evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1); |
de8268c5 BS |
1189 | evo_data(push, 0x00000000); |
1190 | evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); | |
1191 | evo_data(push, 0x00000311); | |
1192 | evo_data(push, 0x00000100); | |
1193 | } else { | |
1194 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); | |
1195 | evo_data(push, 0x00000000); | |
1196 | evo_data(push, (vactive << 16) | hactive); | |
1197 | evo_data(push, ( vsynce << 16) | hsynce); | |
1198 | evo_data(push, (vblanke << 16) | hblanke); | |
1199 | evo_data(push, (vblanks << 16) | hblanks); | |
1200 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1201 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); | |
1202 | evo_data(push, 0x00000000); /* ??? */ | |
1203 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); | |
1204 | evo_data(push, mode->clock * 1000); | |
1205 | evo_data(push, 0x00200000); /* ??? */ | |
1206 | evo_data(push, mode->clock * 1000); | |
1207 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); | |
1208 | evo_data(push, 0x00000311); | |
1209 | evo_data(push, 0x00000100); | |
1210 | } | |
1211 | ||
1212 | evo_kick(push, mast); | |
438d99e3 BS |
1213 | } |
1214 | ||
1215 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
e225f446 BS |
1216 | nv50_crtc_set_dither(nv_crtc, false); |
1217 | nv50_crtc_set_scale(nv_crtc, false); | |
eae7382b RS |
1218 | |
1219 | /* G94 only accepts this after setting scale */ | |
1220 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) | |
1221 | nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus); | |
1222 | ||
e225f446 | 1223 | nv50_crtc_set_color_vibrance(nv_crtc, false); |
f4510a27 | 1224 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false); |
438d99e3 BS |
1225 | return 0; |
1226 | } | |
1227 | ||
1228 | static int | |
e225f446 | 1229 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
438d99e3 BS |
1230 | struct drm_framebuffer *old_fb) |
1231 | { | |
77145f1c | 1232 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
438d99e3 BS |
1233 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1234 | int ret; | |
1235 | ||
f4510a27 | 1236 | if (!crtc->primary->fb) { |
77145f1c | 1237 | NV_DEBUG(drm, "No FB bound\n"); |
84e2ad8b BS |
1238 | return 0; |
1239 | } | |
1240 | ||
e225f446 | 1241 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1242 | if (ret) |
1243 | return ret; | |
1244 | ||
e225f446 | 1245 | nv50_display_flip_stop(crtc); |
f4510a27 MR |
1246 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true); |
1247 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); | |
438d99e3 BS |
1248 | return 0; |
1249 | } | |
1250 | ||
1251 | static int | |
e225f446 | 1252 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
438d99e3 BS |
1253 | struct drm_framebuffer *fb, int x, int y, |
1254 | enum mode_set_atomic state) | |
1255 | { | |
1256 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1257 | nv50_display_flip_stop(crtc); |
1258 | nv50_crtc_set_image(nv_crtc, fb, x, y, true); | |
438d99e3 BS |
1259 | return 0; |
1260 | } | |
1261 | ||
1262 | static void | |
e225f446 | 1263 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
438d99e3 | 1264 | { |
e225f446 | 1265 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
438d99e3 BS |
1266 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1267 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
1268 | int i; | |
1269 | ||
1270 | for (i = 0; i < 256; i++) { | |
de8268c5 BS |
1271 | u16 r = nv_crtc->lut.r[i] >> 2; |
1272 | u16 g = nv_crtc->lut.g[i] >> 2; | |
1273 | u16 b = nv_crtc->lut.b[i] >> 2; | |
1274 | ||
648d4dfd | 1275 | if (disp->disp->oclass < GF110_DISP) { |
de8268c5 BS |
1276 | writew(r + 0x0000, lut + (i * 0x08) + 0); |
1277 | writew(g + 0x0000, lut + (i * 0x08) + 2); | |
1278 | writew(b + 0x0000, lut + (i * 0x08) + 4); | |
1279 | } else { | |
1280 | writew(r + 0x6000, lut + (i * 0x20) + 0); | |
1281 | writew(g + 0x6000, lut + (i * 0x20) + 2); | |
1282 | writew(b + 0x6000, lut + (i * 0x20) + 4); | |
1283 | } | |
438d99e3 BS |
1284 | } |
1285 | } | |
1286 | ||
8dda53fc BS |
1287 | static void |
1288 | nv50_crtc_disable(struct drm_crtc *crtc) | |
1289 | { | |
1290 | struct nv50_head *head = nv50_head(crtc); | |
efa366fd | 1291 | evo_sync(crtc->dev); |
8dda53fc BS |
1292 | if (head->image) |
1293 | nouveau_bo_unpin(head->image); | |
1294 | nouveau_bo_ref(NULL, &head->image); | |
1295 | } | |
1296 | ||
438d99e3 | 1297 | static int |
e225f446 | 1298 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
438d99e3 BS |
1299 | uint32_t handle, uint32_t width, uint32_t height) |
1300 | { | |
1301 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
1302 | struct drm_device *dev = crtc->dev; | |
5a560252 BS |
1303 | struct drm_gem_object *gem = NULL; |
1304 | struct nouveau_bo *nvbo = NULL; | |
1305 | int ret = 0; | |
438d99e3 | 1306 | |
5a560252 | 1307 | if (handle) { |
438d99e3 BS |
1308 | if (width != 64 || height != 64) |
1309 | return -EINVAL; | |
1310 | ||
1311 | gem = drm_gem_object_lookup(dev, file_priv, handle); | |
1312 | if (unlikely(!gem)) | |
1313 | return -ENOENT; | |
1314 | nvbo = nouveau_gem_object(gem); | |
1315 | ||
5a560252 | 1316 | ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true); |
438d99e3 BS |
1317 | } |
1318 | ||
5a560252 | 1319 | if (ret == 0) { |
4dc63933 ML |
1320 | if (nv_crtc->cursor.nvbo) |
1321 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
1322 | nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo); | |
438d99e3 | 1323 | } |
5a560252 | 1324 | drm_gem_object_unreference_unlocked(gem); |
438d99e3 | 1325 | |
5a560252 | 1326 | nv50_crtc_cursor_show_hide(nv_crtc, true, true); |
438d99e3 BS |
1327 | return ret; |
1328 | } | |
1329 | ||
1330 | static int | |
e225f446 | 1331 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
438d99e3 | 1332 | { |
4dc63933 | 1333 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
e225f446 BS |
1334 | struct nv50_curs *curs = nv50_curs(crtc); |
1335 | struct nv50_chan *chan = nv50_chan(curs); | |
0ad72863 BS |
1336 | nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff)); |
1337 | nvif_wr32(&chan->user, 0x0080, 0x00000000); | |
4dc63933 ML |
1338 | |
1339 | nv_crtc->cursor_saved_x = x; | |
1340 | nv_crtc->cursor_saved_y = y; | |
438d99e3 BS |
1341 | return 0; |
1342 | } | |
1343 | ||
1344 | static void | |
e225f446 | 1345 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
438d99e3 BS |
1346 | uint32_t start, uint32_t size) |
1347 | { | |
1348 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
bdefc8cb | 1349 | u32 end = min_t(u32, start + size, 256); |
438d99e3 BS |
1350 | u32 i; |
1351 | ||
1352 | for (i = start; i < end; i++) { | |
1353 | nv_crtc->lut.r[i] = r[i]; | |
1354 | nv_crtc->lut.g[i] = g[i]; | |
1355 | nv_crtc->lut.b[i] = b[i]; | |
1356 | } | |
1357 | ||
e225f446 | 1358 | nv50_crtc_lut_load(crtc); |
438d99e3 BS |
1359 | } |
1360 | ||
4dc63933 ML |
1361 | static void |
1362 | nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y) | |
1363 | { | |
1364 | nv50_crtc_cursor_move(&nv_crtc->base, x, y); | |
1365 | ||
1366 | nv50_crtc_cursor_show_hide(nv_crtc, true, true); | |
1367 | } | |
1368 | ||
438d99e3 | 1369 | static void |
e225f446 | 1370 | nv50_crtc_destroy(struct drm_crtc *crtc) |
438d99e3 BS |
1371 | { |
1372 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1373 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
1374 | struct nv50_head *head = nv50_head(crtc); | |
0ad72863 | 1375 | struct nv50_fbdma *fbdma; |
8dda53fc | 1376 | |
0ad72863 BS |
1377 | list_for_each_entry(fbdma, &disp->fbdma, head) { |
1378 | nvif_object_fini(&fbdma->base[nv_crtc->index]); | |
1379 | } | |
1380 | ||
1381 | nv50_dmac_destroy(&head->ovly.base, disp->disp); | |
1382 | nv50_pioc_destroy(&head->oimm.base); | |
1383 | nv50_dmac_destroy(&head->sync.base, disp->disp); | |
1384 | nv50_pioc_destroy(&head->curs.base); | |
8dda53fc BS |
1385 | |
1386 | /*XXX: this shouldn't be necessary, but the core doesn't call | |
1387 | * disconnect() during the cleanup paths | |
1388 | */ | |
1389 | if (head->image) | |
1390 | nouveau_bo_unpin(head->image); | |
1391 | nouveau_bo_ref(NULL, &head->image); | |
1392 | ||
5a560252 | 1393 | /*XXX: ditto */ |
4dc63933 ML |
1394 | if (nv_crtc->cursor.nvbo) |
1395 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
1396 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); | |
8dda53fc | 1397 | |
438d99e3 | 1398 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
04c8c210 MS |
1399 | if (nv_crtc->lut.nvbo) |
1400 | nouveau_bo_unpin(nv_crtc->lut.nvbo); | |
438d99e3 | 1401 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
8dda53fc | 1402 | |
438d99e3 BS |
1403 | drm_crtc_cleanup(crtc); |
1404 | kfree(crtc); | |
1405 | } | |
1406 | ||
e225f446 BS |
1407 | static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { |
1408 | .dpms = nv50_crtc_dpms, | |
1409 | .prepare = nv50_crtc_prepare, | |
1410 | .commit = nv50_crtc_commit, | |
1411 | .mode_fixup = nv50_crtc_mode_fixup, | |
1412 | .mode_set = nv50_crtc_mode_set, | |
1413 | .mode_set_base = nv50_crtc_mode_set_base, | |
1414 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, | |
1415 | .load_lut = nv50_crtc_lut_load, | |
8dda53fc | 1416 | .disable = nv50_crtc_disable, |
438d99e3 BS |
1417 | }; |
1418 | ||
e225f446 BS |
1419 | static const struct drm_crtc_funcs nv50_crtc_func = { |
1420 | .cursor_set = nv50_crtc_cursor_set, | |
1421 | .cursor_move = nv50_crtc_cursor_move, | |
1422 | .gamma_set = nv50_crtc_gamma_set, | |
5addcf0a | 1423 | .set_config = nouveau_crtc_set_config, |
e225f446 | 1424 | .destroy = nv50_crtc_destroy, |
3376ee37 | 1425 | .page_flip = nouveau_crtc_page_flip, |
438d99e3 BS |
1426 | }; |
1427 | ||
1428 | static int | |
0ad72863 | 1429 | nv50_crtc_create(struct drm_device *dev, int index) |
438d99e3 | 1430 | { |
a01ca78c BS |
1431 | struct nouveau_drm *drm = nouveau_drm(dev); |
1432 | struct nvif_device *device = &drm->device; | |
e225f446 BS |
1433 | struct nv50_disp *disp = nv50_disp(dev); |
1434 | struct nv50_head *head; | |
438d99e3 BS |
1435 | struct drm_crtc *crtc; |
1436 | int ret, i; | |
1437 | ||
dd0e3d53 BS |
1438 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
1439 | if (!head) | |
438d99e3 BS |
1440 | return -ENOMEM; |
1441 | ||
dd0e3d53 | 1442 | head->base.index = index; |
e225f446 BS |
1443 | head->base.set_dither = nv50_crtc_set_dither; |
1444 | head->base.set_scale = nv50_crtc_set_scale; | |
1445 | head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; | |
f9887d09 BS |
1446 | head->base.color_vibrance = 50; |
1447 | head->base.vibrant_hue = 0; | |
4dc63933 | 1448 | head->base.cursor.set_pos = nv50_crtc_cursor_restore; |
438d99e3 | 1449 | for (i = 0; i < 256; i++) { |
dd0e3d53 BS |
1450 | head->base.lut.r[i] = i << 8; |
1451 | head->base.lut.g[i] = i << 8; | |
1452 | head->base.lut.b[i] = i << 8; | |
438d99e3 BS |
1453 | } |
1454 | ||
dd0e3d53 | 1455 | crtc = &head->base.base; |
e225f446 BS |
1456 | drm_crtc_init(dev, crtc, &nv50_crtc_func); |
1457 | drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); | |
438d99e3 BS |
1458 | drm_mode_crtc_set_gamma_size(crtc, 256); |
1459 | ||
b5a794b0 | 1460 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
bb6178b0 | 1461 | 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); |
b5a794b0 | 1462 | if (!ret) { |
547ad072 | 1463 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 1464 | if (!ret) { |
b5a794b0 | 1465 | ret = nouveau_bo_map(head->base.lut.nvbo); |
04c8c210 MS |
1466 | if (ret) |
1467 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1468 | } | |
b5a794b0 BS |
1469 | if (ret) |
1470 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); | |
1471 | } | |
1472 | ||
1473 | if (ret) | |
1474 | goto out; | |
1475 | ||
b5a794b0 | 1476 | /* allocate cursor resources */ |
a01ca78c | 1477 | ret = nv50_curs_create(device, disp->disp, index, &head->curs); |
438d99e3 BS |
1478 | if (ret) |
1479 | goto out; | |
1480 | ||
b5a794b0 | 1481 | /* allocate page flip / sync resources */ |
a01ca78c BS |
1482 | ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset, |
1483 | &head->sync); | |
b5a794b0 BS |
1484 | if (ret) |
1485 | goto out; | |
1486 | ||
9f9bdaaf BS |
1487 | head->sync.addr = EVO_FLIP_SEM0(index); |
1488 | head->sync.data = 0x00000000; | |
438d99e3 | 1489 | |
b5a794b0 | 1490 | /* allocate overlay resources */ |
a01ca78c | 1491 | ret = nv50_oimm_create(device, disp->disp, index, &head->oimm); |
438d99e3 BS |
1492 | if (ret) |
1493 | goto out; | |
1494 | ||
a01ca78c BS |
1495 | ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset, |
1496 | &head->ovly); | |
b5a794b0 BS |
1497 | if (ret) |
1498 | goto out; | |
438d99e3 BS |
1499 | |
1500 | out: | |
1501 | if (ret) | |
e225f446 | 1502 | nv50_crtc_destroy(crtc); |
438d99e3 BS |
1503 | return ret; |
1504 | } | |
1505 | ||
a91d3221 BS |
1506 | /****************************************************************************** |
1507 | * Encoder helpers | |
1508 | *****************************************************************************/ | |
1509 | static bool | |
1510 | nv50_encoder_mode_fixup(struct drm_encoder *encoder, | |
1511 | const struct drm_display_mode *mode, | |
1512 | struct drm_display_mode *adjusted_mode) | |
1513 | { | |
1514 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1515 | struct nouveau_connector *nv_connector; | |
1516 | ||
1517 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1518 | if (nv_connector && nv_connector->native_mode) { | |
576f7911 BS |
1519 | nv_connector->scaling_full = false; |
1520 | if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) { | |
1521 | switch (nv_connector->type) { | |
1522 | case DCB_CONNECTOR_LVDS: | |
1523 | case DCB_CONNECTOR_LVDS_SPWG: | |
1524 | case DCB_CONNECTOR_eDP: | |
1525 | /* force use of scaler for non-edid modes */ | |
1526 | if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) | |
1527 | return true; | |
1528 | nv_connector->scaling_full = true; | |
1529 | break; | |
1530 | default: | |
1531 | return true; | |
1532 | } | |
1533 | } | |
1534 | ||
1535 | drm_mode_copy(adjusted_mode, nv_connector->native_mode); | |
a91d3221 BS |
1536 | } |
1537 | ||
1538 | return true; | |
1539 | } | |
1540 | ||
26f6d88b BS |
1541 | /****************************************************************************** |
1542 | * DAC | |
1543 | *****************************************************************************/ | |
8eaa9669 | 1544 | static void |
e225f446 | 1545 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
8eaa9669 BS |
1546 | { |
1547 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1548 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
bf0eb898 BS |
1549 | struct { |
1550 | struct nv50_disp_mthd_v1 base; | |
1551 | struct nv50_disp_dac_pwr_v0 pwr; | |
1552 | } args = { | |
1553 | .base.version = 1, | |
1554 | .base.method = NV50_DISP_MTHD_V1_DAC_PWR, | |
1555 | .base.hasht = nv_encoder->dcb->hasht, | |
1556 | .base.hashm = nv_encoder->dcb->hashm, | |
1557 | .pwr.state = 1, | |
1558 | .pwr.data = 1, | |
1559 | .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND && | |
1560 | mode != DRM_MODE_DPMS_OFF), | |
1561 | .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY && | |
1562 | mode != DRM_MODE_DPMS_OFF), | |
1563 | }; | |
8eaa9669 | 1564 | |
bf0eb898 | 1565 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
8eaa9669 BS |
1566 | } |
1567 | ||
8eaa9669 | 1568 | static void |
e225f446 | 1569 | nv50_dac_commit(struct drm_encoder *encoder) |
8eaa9669 BS |
1570 | { |
1571 | } | |
1572 | ||
1573 | static void | |
e225f446 | 1574 | nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
8eaa9669 BS |
1575 | struct drm_display_mode *adjusted_mode) |
1576 | { | |
e225f446 | 1577 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
8eaa9669 BS |
1578 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1579 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
97b19b5c | 1580 | u32 *push; |
8eaa9669 | 1581 | |
e225f446 | 1582 | nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
8eaa9669 | 1583 | |
97b19b5c | 1584 | push = evo_wait(mast, 8); |
8eaa9669 | 1585 | if (push) { |
648d4dfd | 1586 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
1587 | u32 syncs = 0x00000000; |
1588 | ||
1589 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1590 | syncs |= 0x00000001; | |
1591 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1592 | syncs |= 0x00000002; | |
1593 | ||
1594 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); | |
1595 | evo_data(push, 1 << nv_crtc->index); | |
1596 | evo_data(push, syncs); | |
1597 | } else { | |
1598 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1599 | u32 syncs = 0x00000001; | |
1600 | ||
1601 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1602 | syncs |= 0x00000008; | |
1603 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1604 | syncs |= 0x00000010; | |
1605 | ||
1606 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1607 | magic |= 0x00000001; | |
1608 | ||
1609 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
1610 | evo_data(push, syncs); | |
1611 | evo_data(push, magic); | |
1612 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); | |
1613 | evo_data(push, 1 << nv_crtc->index); | |
1614 | } | |
1615 | ||
1616 | evo_kick(push, mast); | |
8eaa9669 BS |
1617 | } |
1618 | ||
1619 | nv_encoder->crtc = encoder->crtc; | |
1620 | } | |
1621 | ||
1622 | static void | |
e225f446 | 1623 | nv50_dac_disconnect(struct drm_encoder *encoder) |
8eaa9669 BS |
1624 | { |
1625 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1626 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
97b19b5c | 1627 | const int or = nv_encoder->or; |
8eaa9669 BS |
1628 | u32 *push; |
1629 | ||
1630 | if (nv_encoder->crtc) { | |
e225f446 | 1631 | nv50_crtc_prepare(nv_encoder->crtc); |
8eaa9669 | 1632 | |
97b19b5c | 1633 | push = evo_wait(mast, 4); |
8eaa9669 | 1634 | if (push) { |
648d4dfd | 1635 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
1636 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
1637 | evo_data(push, 0x00000000); | |
1638 | } else { | |
1639 | evo_mthd(push, 0x0180 + (or * 0x020), 1); | |
1640 | evo_data(push, 0x00000000); | |
1641 | } | |
97b19b5c | 1642 | evo_kick(push, mast); |
8eaa9669 | 1643 | } |
8eaa9669 | 1644 | } |
97b19b5c BS |
1645 | |
1646 | nv_encoder->crtc = NULL; | |
8eaa9669 BS |
1647 | } |
1648 | ||
b6d8e7ec | 1649 | static enum drm_connector_status |
e225f446 | 1650 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
b6d8e7ec | 1651 | { |
c4abd317 | 1652 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 1653 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
c4abd317 BS |
1654 | struct { |
1655 | struct nv50_disp_mthd_v1 base; | |
1656 | struct nv50_disp_dac_load_v0 load; | |
1657 | } args = { | |
1658 | .base.version = 1, | |
1659 | .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, | |
1660 | .base.hasht = nv_encoder->dcb->hasht, | |
1661 | .base.hashm = nv_encoder->dcb->hashm, | |
1662 | }; | |
1663 | int ret; | |
1664 | ||
1665 | args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; | |
1666 | if (args.load.data == 0) | |
1667 | args.load.data = 340; | |
b681993f | 1668 | |
c4abd317 BS |
1669 | ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
1670 | if (ret || !args.load.load) | |
35b21d39 | 1671 | return connector_status_disconnected; |
b681993f | 1672 | |
35b21d39 | 1673 | return connector_status_connected; |
b6d8e7ec BS |
1674 | } |
1675 | ||
8eaa9669 | 1676 | static void |
e225f446 | 1677 | nv50_dac_destroy(struct drm_encoder *encoder) |
8eaa9669 BS |
1678 | { |
1679 | drm_encoder_cleanup(encoder); | |
1680 | kfree(encoder); | |
1681 | } | |
1682 | ||
e225f446 BS |
1683 | static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { |
1684 | .dpms = nv50_dac_dpms, | |
a91d3221 | 1685 | .mode_fixup = nv50_encoder_mode_fixup, |
e225f446 BS |
1686 | .prepare = nv50_dac_disconnect, |
1687 | .commit = nv50_dac_commit, | |
1688 | .mode_set = nv50_dac_mode_set, | |
1689 | .disable = nv50_dac_disconnect, | |
1690 | .get_crtc = nv50_display_crtc_get, | |
1691 | .detect = nv50_dac_detect | |
8eaa9669 BS |
1692 | }; |
1693 | ||
e225f446 BS |
1694 | static const struct drm_encoder_funcs nv50_dac_func = { |
1695 | .destroy = nv50_dac_destroy, | |
8eaa9669 BS |
1696 | }; |
1697 | ||
1698 | static int | |
e225f446 | 1699 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
8eaa9669 | 1700 | { |
5ed50209 | 1701 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
be83cd4e | 1702 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
2aa5eac5 | 1703 | struct nvkm_i2c_bus *bus; |
8eaa9669 BS |
1704 | struct nouveau_encoder *nv_encoder; |
1705 | struct drm_encoder *encoder; | |
5ed50209 | 1706 | int type = DRM_MODE_ENCODER_DAC; |
8eaa9669 BS |
1707 | |
1708 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1709 | if (!nv_encoder) | |
1710 | return -ENOMEM; | |
1711 | nv_encoder->dcb = dcbe; | |
1712 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2aa5eac5 BS |
1713 | |
1714 | bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); | |
1715 | if (bus) | |
1716 | nv_encoder->i2c = &bus->i2c; | |
8eaa9669 BS |
1717 | |
1718 | encoder = to_drm_encoder(nv_encoder); | |
1719 | encoder->possible_crtcs = dcbe->heads; | |
1720 | encoder->possible_clones = 0; | |
13a3d91f | 1721 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, NULL); |
e225f446 | 1722 | drm_encoder_helper_add(encoder, &nv50_dac_hfunc); |
8eaa9669 BS |
1723 | |
1724 | drm_mode_connector_attach_encoder(connector, encoder); | |
1725 | return 0; | |
1726 | } | |
26f6d88b | 1727 | |
78951d22 BS |
1728 | /****************************************************************************** |
1729 | * Audio | |
1730 | *****************************************************************************/ | |
1731 | static void | |
e225f446 | 1732 | nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 BS |
1733 | { |
1734 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
cc2a9071 | 1735 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
78951d22 | 1736 | struct nouveau_connector *nv_connector; |
e225f446 | 1737 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
d889c524 BS |
1738 | struct __packed { |
1739 | struct { | |
1740 | struct nv50_disp_mthd_v1 mthd; | |
1741 | struct nv50_disp_sor_hda_eld_v0 eld; | |
1742 | } base; | |
120b0c39 BS |
1743 | u8 data[sizeof(nv_connector->base.eld)]; |
1744 | } args = { | |
d889c524 BS |
1745 | .base.mthd.version = 1, |
1746 | .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
1747 | .base.mthd.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
1748 | .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
1749 | (0x0100 << nv_crtc->index), | |
120b0c39 | 1750 | }; |
78951d22 BS |
1751 | |
1752 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1753 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
1754 | return; | |
1755 | ||
78951d22 | 1756 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
120b0c39 | 1757 | memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); |
78951d22 | 1758 | |
938fd8aa JN |
1759 | nvif_mthd(disp->disp, 0, &args, |
1760 | sizeof(args.base) + drm_eld_size(args.data)); | |
78951d22 BS |
1761 | } |
1762 | ||
1763 | static void | |
cc2a9071 | 1764 | nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 BS |
1765 | { |
1766 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1767 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
120b0c39 BS |
1768 | struct { |
1769 | struct nv50_disp_mthd_v1 base; | |
1770 | struct nv50_disp_sor_hda_eld_v0 eld; | |
1771 | } args = { | |
1772 | .base.version = 1, | |
1773 | .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
1774 | .base.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
1775 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
1776 | (0x0100 << nv_crtc->index), | |
120b0c39 | 1777 | }; |
78951d22 | 1778 | |
120b0c39 | 1779 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
1780 | } |
1781 | ||
1782 | /****************************************************************************** | |
1783 | * HDMI | |
1784 | *****************************************************************************/ | |
1785 | static void | |
e225f446 | 1786 | nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 | 1787 | { |
64d9cc04 BS |
1788 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1789 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
e225f446 | 1790 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
1791 | struct { |
1792 | struct nv50_disp_mthd_v1 base; | |
1793 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
1794 | } args = { | |
1795 | .base.version = 1, | |
1796 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
1797 | .base.hasht = nv_encoder->dcb->hasht, | |
1798 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
1799 | (0x0100 << nv_crtc->index), | |
1800 | .pwr.state = 1, | |
1801 | .pwr.rekey = 56, /* binary driver, and tegra, constant */ | |
1802 | }; | |
1803 | struct nouveau_connector *nv_connector; | |
64d9cc04 BS |
1804 | u32 max_ac_packet; |
1805 | ||
1806 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1807 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
1808 | return; | |
1809 | ||
1810 | max_ac_packet = mode->htotal - mode->hdisplay; | |
e00f2235 | 1811 | max_ac_packet -= args.pwr.rekey; |
64d9cc04 | 1812 | max_ac_packet -= 18; /* constant from tegra */ |
e00f2235 | 1813 | args.pwr.max_ac_packet = max_ac_packet / 32; |
091e40cd | 1814 | |
e00f2235 | 1815 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
e225f446 | 1816 | nv50_audio_mode_set(encoder, mode); |
78951d22 BS |
1817 | } |
1818 | ||
1819 | static void | |
e84a35a8 | 1820 | nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 | 1821 | { |
64d9cc04 | 1822 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 1823 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
1824 | struct { |
1825 | struct nv50_disp_mthd_v1 base; | |
1826 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
1827 | } args = { | |
1828 | .base.version = 1, | |
1829 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
1830 | .base.hasht = nv_encoder->dcb->hasht, | |
1831 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
1832 | (0x0100 << nv_crtc->index), | |
1833 | }; | |
64d9cc04 | 1834 | |
e00f2235 | 1835 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
1836 | } |
1837 | ||
26f6d88b BS |
1838 | /****************************************************************************** |
1839 | * SOR | |
1840 | *****************************************************************************/ | |
83fc083c | 1841 | static void |
e225f446 | 1842 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
83fc083c BS |
1843 | { |
1844 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
d55b4af9 BS |
1845 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1846 | struct { | |
1847 | struct nv50_disp_mthd_v1 base; | |
1848 | struct nv50_disp_sor_pwr_v0 pwr; | |
1849 | } args = { | |
1850 | .base.version = 1, | |
1851 | .base.method = NV50_DISP_MTHD_V1_SOR_PWR, | |
1852 | .base.hasht = nv_encoder->dcb->hasht, | |
1853 | .base.hashm = nv_encoder->dcb->hashm, | |
1854 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
1855 | }; | |
c02ed2bf BS |
1856 | struct { |
1857 | struct nv50_disp_mthd_v1 base; | |
1858 | struct nv50_disp_sor_dp_pwr_v0 pwr; | |
1859 | } link = { | |
1860 | .base.version = 1, | |
1861 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR, | |
1862 | .base.hasht = nv_encoder->dcb->hasht, | |
1863 | .base.hashm = nv_encoder->dcb->hashm, | |
1864 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
1865 | }; | |
83fc083c BS |
1866 | struct drm_device *dev = encoder->dev; |
1867 | struct drm_encoder *partner; | |
83fc083c BS |
1868 | |
1869 | nv_encoder->last_dpms = mode; | |
1870 | ||
1871 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { | |
1872 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); | |
1873 | ||
1874 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) | |
1875 | continue; | |
1876 | ||
1877 | if (nv_partner != nv_encoder && | |
26cfa813 | 1878 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
83fc083c BS |
1879 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
1880 | return; | |
1881 | break; | |
1882 | } | |
1883 | } | |
1884 | ||
4874322e | 1885 | if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { |
d55b4af9 BS |
1886 | args.pwr.state = 1; |
1887 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
c02ed2bf | 1888 | nvif_mthd(disp->disp, 0, &link, sizeof(link)); |
4874322e | 1889 | } else { |
d55b4af9 | 1890 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
4874322e | 1891 | } |
83fc083c BS |
1892 | } |
1893 | ||
4cbb0f8d | 1894 | static void |
e84a35a8 | 1895 | nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data) |
4cbb0f8d | 1896 | { |
e84a35a8 BS |
1897 | struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev); |
1898 | u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push; | |
1899 | if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) { | |
648d4dfd | 1900 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
e84a35a8 BS |
1901 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); |
1902 | evo_data(push, (nv_encoder->ctrl = temp)); | |
1903 | } else { | |
1904 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); | |
1905 | evo_data(push, (nv_encoder->ctrl = temp)); | |
4cbb0f8d | 1906 | } |
e84a35a8 | 1907 | evo_kick(push, mast); |
4cbb0f8d | 1908 | } |
e84a35a8 BS |
1909 | } |
1910 | ||
1911 | static void | |
1912 | nv50_sor_disconnect(struct drm_encoder *encoder) | |
1913 | { | |
1914 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1915 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
419e8dc0 BS |
1916 | |
1917 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
1918 | nv_encoder->crtc = NULL; | |
e84a35a8 BS |
1919 | |
1920 | if (nv_crtc) { | |
1921 | nv50_crtc_prepare(&nv_crtc->base); | |
1922 | nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0); | |
cc2a9071 | 1923 | nv50_audio_disconnect(encoder, nv_crtc); |
e84a35a8 BS |
1924 | nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc); |
1925 | } | |
4cbb0f8d BS |
1926 | } |
1927 | ||
83fc083c | 1928 | static void |
e225f446 | 1929 | nv50_sor_commit(struct drm_encoder *encoder) |
83fc083c BS |
1930 | { |
1931 | } | |
1932 | ||
1933 | static void | |
e225f446 | 1934 | nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
3b6d83d1 | 1935 | struct drm_display_mode *mode) |
83fc083c | 1936 | { |
a3761fa2 BS |
1937 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1938 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
1939 | struct { | |
1940 | struct nv50_disp_mthd_v1 base; | |
1941 | struct nv50_disp_sor_lvds_script_v0 lvds; | |
1942 | } lvds = { | |
1943 | .base.version = 1, | |
1944 | .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, | |
1945 | .base.hasht = nv_encoder->dcb->hasht, | |
1946 | .base.hashm = nv_encoder->dcb->hashm, | |
1947 | }; | |
e225f446 BS |
1948 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1949 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
78951d22 | 1950 | struct drm_device *dev = encoder->dev; |
77145f1c | 1951 | struct nouveau_drm *drm = nouveau_drm(dev); |
3b6d83d1 | 1952 | struct nouveau_connector *nv_connector; |
77145f1c | 1953 | struct nvbios *bios = &drm->vbios; |
a3761fa2 | 1954 | u32 mask, ctrl; |
419e8dc0 BS |
1955 | u8 owner = 1 << nv_crtc->index; |
1956 | u8 proto = 0xf; | |
1957 | u8 depth = 0x0; | |
83fc083c | 1958 | |
3b6d83d1 | 1959 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
e84a35a8 BS |
1960 | nv_encoder->crtc = encoder->crtc; |
1961 | ||
3b6d83d1 | 1962 | switch (nv_encoder->dcb->type) { |
cb75d97e | 1963 | case DCB_OUTPUT_TMDS: |
3b6d83d1 BS |
1964 | if (nv_encoder->dcb->sorconf.link & 1) { |
1965 | if (mode->clock < 165000) | |
419e8dc0 | 1966 | proto = 0x1; |
3b6d83d1 | 1967 | else |
419e8dc0 | 1968 | proto = 0x5; |
3b6d83d1 | 1969 | } else { |
419e8dc0 | 1970 | proto = 0x2; |
3b6d83d1 BS |
1971 | } |
1972 | ||
e84a35a8 | 1973 | nv50_hdmi_mode_set(&nv_encoder->base.base, mode); |
3b6d83d1 | 1974 | break; |
cb75d97e | 1975 | case DCB_OUTPUT_LVDS: |
419e8dc0 BS |
1976 | proto = 0x0; |
1977 | ||
3b6d83d1 BS |
1978 | if (bios->fp_no_ddc) { |
1979 | if (bios->fp.dual_link) | |
a3761fa2 | 1980 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 1981 | if (bios->fp.if_is_24bit) |
a3761fa2 | 1982 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 1983 | } else { |
befb51e9 | 1984 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 | 1985 | if (((u8 *)nv_connector->edid)[121] == 2) |
a3761fa2 | 1986 | lvds.lvds.script |= 0x0100; |
3b6d83d1 BS |
1987 | } else |
1988 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
a3761fa2 | 1989 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 1990 | } |
83fc083c | 1991 | |
a3761fa2 | 1992 | if (lvds.lvds.script & 0x0100) { |
3b6d83d1 | 1993 | if (bios->fp.strapless_is_24bit & 2) |
a3761fa2 | 1994 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
1995 | } else { |
1996 | if (bios->fp.strapless_is_24bit & 1) | |
a3761fa2 | 1997 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
1998 | } |
1999 | ||
2000 | if (nv_connector->base.display_info.bpc == 8) | |
a3761fa2 | 2001 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 2002 | } |
4a230fa6 | 2003 | |
a3761fa2 | 2004 | nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); |
3b6d83d1 | 2005 | break; |
cb75d97e | 2006 | case DCB_OUTPUT_DP: |
3488c57b | 2007 | if (nv_connector->base.display_info.bpc == 6) { |
6e83fda2 | 2008 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
419e8dc0 | 2009 | depth = 0x2; |
bf2c886a BS |
2010 | } else |
2011 | if (nv_connector->base.display_info.bpc == 8) { | |
6e83fda2 | 2012 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
419e8dc0 | 2013 | depth = 0x5; |
bf2c886a BS |
2014 | } else { |
2015 | nv_encoder->dp.datarate = mode->clock * 30 / 8; | |
2016 | depth = 0x6; | |
3488c57b | 2017 | } |
6e83fda2 BS |
2018 | |
2019 | if (nv_encoder->dcb->sorconf.link & 1) | |
419e8dc0 | 2020 | proto = 0x8; |
6e83fda2 | 2021 | else |
419e8dc0 | 2022 | proto = 0x9; |
3eee8646 | 2023 | nv50_audio_mode_set(encoder, mode); |
6e83fda2 | 2024 | break; |
3b6d83d1 BS |
2025 | default: |
2026 | BUG_ON(1); | |
2027 | break; | |
2028 | } | |
ff8ff503 | 2029 | |
e84a35a8 | 2030 | nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON); |
83fc083c | 2031 | |
648d4dfd | 2032 | if (nv50_vers(mast) >= GF110_DISP) { |
e84a35a8 BS |
2033 | u32 *push = evo_wait(mast, 3); |
2034 | if (push) { | |
419e8dc0 BS |
2035 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
2036 | u32 syncs = 0x00000001; | |
2037 | ||
2038 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2039 | syncs |= 0x00000008; | |
2040 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2041 | syncs |= 0x00000010; | |
2042 | ||
2043 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2044 | magic |= 0x00000001; | |
2045 | ||
2046 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
2047 | evo_data(push, syncs | (depth << 6)); | |
2048 | evo_data(push, magic); | |
e84a35a8 | 2049 | evo_kick(push, mast); |
419e8dc0 BS |
2050 | } |
2051 | ||
e84a35a8 BS |
2052 | ctrl = proto << 8; |
2053 | mask = 0x00000f00; | |
2054 | } else { | |
2055 | ctrl = (depth << 16) | (proto << 8); | |
2056 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2057 | ctrl |= 0x00001000; | |
2058 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2059 | ctrl |= 0x00002000; | |
2060 | mask = 0x000f3f00; | |
83fc083c BS |
2061 | } |
2062 | ||
e84a35a8 | 2063 | nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner); |
83fc083c BS |
2064 | } |
2065 | ||
83fc083c | 2066 | static void |
e225f446 | 2067 | nv50_sor_destroy(struct drm_encoder *encoder) |
83fc083c BS |
2068 | { |
2069 | drm_encoder_cleanup(encoder); | |
2070 | kfree(encoder); | |
2071 | } | |
2072 | ||
e225f446 BS |
2073 | static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { |
2074 | .dpms = nv50_sor_dpms, | |
a91d3221 | 2075 | .mode_fixup = nv50_encoder_mode_fixup, |
5a885f0b | 2076 | .prepare = nv50_sor_disconnect, |
e225f446 BS |
2077 | .commit = nv50_sor_commit, |
2078 | .mode_set = nv50_sor_mode_set, | |
2079 | .disable = nv50_sor_disconnect, | |
2080 | .get_crtc = nv50_display_crtc_get, | |
83fc083c BS |
2081 | }; |
2082 | ||
e225f446 BS |
2083 | static const struct drm_encoder_funcs nv50_sor_func = { |
2084 | .destroy = nv50_sor_destroy, | |
83fc083c BS |
2085 | }; |
2086 | ||
2087 | static int | |
e225f446 | 2088 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
83fc083c | 2089 | { |
5ed50209 | 2090 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
be83cd4e | 2091 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
83fc083c BS |
2092 | struct nouveau_encoder *nv_encoder; |
2093 | struct drm_encoder *encoder; | |
5ed50209 BS |
2094 | int type; |
2095 | ||
2096 | switch (dcbe->type) { | |
2097 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; | |
2098 | case DCB_OUTPUT_TMDS: | |
2099 | case DCB_OUTPUT_DP: | |
2100 | default: | |
2101 | type = DRM_MODE_ENCODER_TMDS; | |
2102 | break; | |
2103 | } | |
83fc083c BS |
2104 | |
2105 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2106 | if (!nv_encoder) | |
2107 | return -ENOMEM; | |
2108 | nv_encoder->dcb = dcbe; | |
2109 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2110 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
2111 | ||
2aa5eac5 BS |
2112 | if (dcbe->type == DCB_OUTPUT_DP) { |
2113 | struct nvkm_i2c_aux *aux = | |
2114 | nvkm_i2c_aux_find(i2c, dcbe->i2c_index); | |
2115 | if (aux) { | |
2116 | nv_encoder->i2c = &aux->i2c; | |
2117 | nv_encoder->aux = aux; | |
2118 | } | |
2119 | } else { | |
2120 | struct nvkm_i2c_bus *bus = | |
2121 | nvkm_i2c_bus_find(i2c, dcbe->i2c_index); | |
2122 | if (bus) | |
2123 | nv_encoder->i2c = &bus->i2c; | |
2124 | } | |
2125 | ||
83fc083c BS |
2126 | encoder = to_drm_encoder(nv_encoder); |
2127 | encoder->possible_crtcs = dcbe->heads; | |
2128 | encoder->possible_clones = 0; | |
13a3d91f | 2129 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, NULL); |
e225f446 | 2130 | drm_encoder_helper_add(encoder, &nv50_sor_hfunc); |
83fc083c BS |
2131 | |
2132 | drm_mode_connector_attach_encoder(connector, encoder); | |
2133 | return 0; | |
2134 | } | |
26f6d88b | 2135 | |
eb6313ad BS |
2136 | /****************************************************************************** |
2137 | * PIOR | |
2138 | *****************************************************************************/ | |
2139 | ||
2140 | static void | |
2141 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) | |
2142 | { | |
2143 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2144 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
67cb49c4 BS |
2145 | struct { |
2146 | struct nv50_disp_mthd_v1 base; | |
2147 | struct nv50_disp_pior_pwr_v0 pwr; | |
2148 | } args = { | |
2149 | .base.version = 1, | |
2150 | .base.method = NV50_DISP_MTHD_V1_PIOR_PWR, | |
2151 | .base.hasht = nv_encoder->dcb->hasht, | |
2152 | .base.hashm = nv_encoder->dcb->hashm, | |
2153 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
2154 | .pwr.type = nv_encoder->dcb->type, | |
2155 | }; | |
2156 | ||
2157 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
eb6313ad BS |
2158 | } |
2159 | ||
2160 | static bool | |
2161 | nv50_pior_mode_fixup(struct drm_encoder *encoder, | |
2162 | const struct drm_display_mode *mode, | |
2163 | struct drm_display_mode *adjusted_mode) | |
2164 | { | |
a91d3221 BS |
2165 | if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode)) |
2166 | return false; | |
eb6313ad BS |
2167 | adjusted_mode->clock *= 2; |
2168 | return true; | |
2169 | } | |
2170 | ||
2171 | static void | |
2172 | nv50_pior_commit(struct drm_encoder *encoder) | |
2173 | { | |
2174 | } | |
2175 | ||
2176 | static void | |
2177 | nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
2178 | struct drm_display_mode *adjusted_mode) | |
2179 | { | |
2180 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2181 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2182 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
2183 | struct nouveau_connector *nv_connector; | |
2184 | u8 owner = 1 << nv_crtc->index; | |
2185 | u8 proto, depth; | |
2186 | u32 *push; | |
2187 | ||
2188 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2189 | switch (nv_connector->base.display_info.bpc) { | |
2190 | case 10: depth = 0x6; break; | |
2191 | case 8: depth = 0x5; break; | |
2192 | case 6: depth = 0x2; break; | |
2193 | default: depth = 0x0; break; | |
2194 | } | |
2195 | ||
2196 | switch (nv_encoder->dcb->type) { | |
2197 | case DCB_OUTPUT_TMDS: | |
2198 | case DCB_OUTPUT_DP: | |
2199 | proto = 0x0; | |
2200 | break; | |
2201 | default: | |
2202 | BUG_ON(1); | |
2203 | break; | |
2204 | } | |
2205 | ||
2206 | nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); | |
2207 | ||
2208 | push = evo_wait(mast, 8); | |
2209 | if (push) { | |
648d4dfd | 2210 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
2211 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
2212 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2213 | ctrl |= 0x00001000; | |
2214 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2215 | ctrl |= 0x00002000; | |
2216 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); | |
2217 | evo_data(push, ctrl); | |
2218 | } | |
2219 | ||
2220 | evo_kick(push, mast); | |
2221 | } | |
2222 | ||
2223 | nv_encoder->crtc = encoder->crtc; | |
2224 | } | |
2225 | ||
2226 | static void | |
2227 | nv50_pior_disconnect(struct drm_encoder *encoder) | |
2228 | { | |
2229 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2230 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2231 | const int or = nv_encoder->or; | |
2232 | u32 *push; | |
2233 | ||
2234 | if (nv_encoder->crtc) { | |
2235 | nv50_crtc_prepare(nv_encoder->crtc); | |
2236 | ||
2237 | push = evo_wait(mast, 4); | |
2238 | if (push) { | |
648d4dfd | 2239 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
2240 | evo_mthd(push, 0x0700 + (or * 0x040), 1); |
2241 | evo_data(push, 0x00000000); | |
2242 | } | |
eb6313ad BS |
2243 | evo_kick(push, mast); |
2244 | } | |
2245 | } | |
2246 | ||
2247 | nv_encoder->crtc = NULL; | |
2248 | } | |
2249 | ||
2250 | static void | |
2251 | nv50_pior_destroy(struct drm_encoder *encoder) | |
2252 | { | |
2253 | drm_encoder_cleanup(encoder); | |
2254 | kfree(encoder); | |
2255 | } | |
2256 | ||
2257 | static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { | |
2258 | .dpms = nv50_pior_dpms, | |
2259 | .mode_fixup = nv50_pior_mode_fixup, | |
2260 | .prepare = nv50_pior_disconnect, | |
2261 | .commit = nv50_pior_commit, | |
2262 | .mode_set = nv50_pior_mode_set, | |
2263 | .disable = nv50_pior_disconnect, | |
2264 | .get_crtc = nv50_display_crtc_get, | |
2265 | }; | |
2266 | ||
2267 | static const struct drm_encoder_funcs nv50_pior_func = { | |
2268 | .destroy = nv50_pior_destroy, | |
2269 | }; | |
2270 | ||
2271 | static int | |
2272 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) | |
2273 | { | |
2274 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
be83cd4e | 2275 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
2aa5eac5 BS |
2276 | struct nvkm_i2c_bus *bus = NULL; |
2277 | struct nvkm_i2c_aux *aux = NULL; | |
2278 | struct i2c_adapter *ddc; | |
eb6313ad BS |
2279 | struct nouveau_encoder *nv_encoder; |
2280 | struct drm_encoder *encoder; | |
2281 | int type; | |
2282 | ||
2283 | switch (dcbe->type) { | |
2284 | case DCB_OUTPUT_TMDS: | |
2aa5eac5 BS |
2285 | bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); |
2286 | ddc = bus ? &bus->i2c : NULL; | |
eb6313ad BS |
2287 | type = DRM_MODE_ENCODER_TMDS; |
2288 | break; | |
2289 | case DCB_OUTPUT_DP: | |
2aa5eac5 BS |
2290 | aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); |
2291 | ddc = aux ? &aux->i2c : NULL; | |
eb6313ad BS |
2292 | type = DRM_MODE_ENCODER_TMDS; |
2293 | break; | |
2294 | default: | |
2295 | return -ENODEV; | |
2296 | } | |
2297 | ||
2298 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2299 | if (!nv_encoder) | |
2300 | return -ENOMEM; | |
2301 | nv_encoder->dcb = dcbe; | |
2302 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2303 | nv_encoder->i2c = ddc; | |
2aa5eac5 | 2304 | nv_encoder->aux = aux; |
eb6313ad BS |
2305 | |
2306 | encoder = to_drm_encoder(nv_encoder); | |
2307 | encoder->possible_crtcs = dcbe->heads; | |
2308 | encoder->possible_clones = 0; | |
13a3d91f | 2309 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, NULL); |
eb6313ad BS |
2310 | drm_encoder_helper_add(encoder, &nv50_pior_hfunc); |
2311 | ||
2312 | drm_mode_connector_attach_encoder(connector, encoder); | |
2313 | return 0; | |
2314 | } | |
2315 | ||
ab0af559 BS |
2316 | /****************************************************************************** |
2317 | * Framebuffer | |
2318 | *****************************************************************************/ | |
2319 | ||
8a423647 | 2320 | static void |
0ad72863 | 2321 | nv50_fbdma_fini(struct nv50_fbdma *fbdma) |
8a423647 | 2322 | { |
0ad72863 BS |
2323 | int i; |
2324 | for (i = 0; i < ARRAY_SIZE(fbdma->base); i++) | |
2325 | nvif_object_fini(&fbdma->base[i]); | |
2326 | nvif_object_fini(&fbdma->core); | |
8a423647 BS |
2327 | list_del(&fbdma->head); |
2328 | kfree(fbdma); | |
2329 | } | |
2330 | ||
2331 | static int | |
2332 | nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind) | |
2333 | { | |
2334 | struct nouveau_drm *drm = nouveau_drm(dev); | |
2335 | struct nv50_disp *disp = nv50_disp(dev); | |
2336 | struct nv50_mast *mast = nv50_mast(dev); | |
4acfd707 BS |
2337 | struct __attribute__ ((packed)) { |
2338 | struct nv_dma_v0 base; | |
2339 | union { | |
2340 | struct nv50_dma_v0 nv50; | |
2341 | struct gf100_dma_v0 gf100; | |
bd70563f | 2342 | struct gf119_dma_v0 gf119; |
4acfd707 BS |
2343 | }; |
2344 | } args = {}; | |
8a423647 BS |
2345 | struct nv50_fbdma *fbdma; |
2346 | struct drm_crtc *crtc; | |
4acfd707 | 2347 | u32 size = sizeof(args.base); |
8a423647 BS |
2348 | int ret; |
2349 | ||
2350 | list_for_each_entry(fbdma, &disp->fbdma, head) { | |
0ad72863 | 2351 | if (fbdma->core.handle == name) |
8a423647 BS |
2352 | return 0; |
2353 | } | |
2354 | ||
2355 | fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL); | |
2356 | if (!fbdma) | |
2357 | return -ENOMEM; | |
2358 | list_add(&fbdma->head, &disp->fbdma); | |
8a423647 | 2359 | |
4acfd707 BS |
2360 | args.base.target = NV_DMA_V0_TARGET_VRAM; |
2361 | args.base.access = NV_DMA_V0_ACCESS_RDWR; | |
2362 | args.base.start = offset; | |
2363 | args.base.limit = offset + length - 1; | |
8a423647 | 2364 | |
967e7bde | 2365 | if (drm->device.info.chipset < 0x80) { |
4acfd707 BS |
2366 | args.nv50.part = NV50_DMA_V0_PART_256; |
2367 | size += sizeof(args.nv50); | |
8a423647 | 2368 | } else |
967e7bde | 2369 | if (drm->device.info.chipset < 0xc0) { |
4acfd707 BS |
2370 | args.nv50.part = NV50_DMA_V0_PART_256; |
2371 | args.nv50.kind = kind; | |
2372 | size += sizeof(args.nv50); | |
8a423647 | 2373 | } else |
967e7bde | 2374 | if (drm->device.info.chipset < 0xd0) { |
4acfd707 BS |
2375 | args.gf100.kind = kind; |
2376 | size += sizeof(args.gf100); | |
8a423647 | 2377 | } else { |
bd70563f BS |
2378 | args.gf119.page = GF119_DMA_V0_PAGE_LP; |
2379 | args.gf119.kind = kind; | |
2380 | size += sizeof(args.gf119); | |
8a423647 BS |
2381 | } |
2382 | ||
2383 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
0ad72863 | 2384 | struct nv50_head *head = nv50_head(crtc); |
a01ca78c BS |
2385 | int ret = nvif_object_init(&head->sync.base.base.user, name, |
2386 | NV_DMA_IN_MEMORY, &args, size, | |
0ad72863 | 2387 | &fbdma->base[head->base.index]); |
8a423647 | 2388 | if (ret) { |
0ad72863 | 2389 | nv50_fbdma_fini(fbdma); |
8a423647 BS |
2390 | return ret; |
2391 | } | |
2392 | } | |
2393 | ||
a01ca78c BS |
2394 | ret = nvif_object_init(&mast->base.base.user, name, NV_DMA_IN_MEMORY, |
2395 | &args, size, &fbdma->core); | |
8a423647 | 2396 | if (ret) { |
0ad72863 | 2397 | nv50_fbdma_fini(fbdma); |
8a423647 BS |
2398 | return ret; |
2399 | } | |
2400 | ||
2401 | return 0; | |
2402 | } | |
2403 | ||
ab0af559 BS |
2404 | static void |
2405 | nv50_fb_dtor(struct drm_framebuffer *fb) | |
2406 | { | |
2407 | } | |
2408 | ||
2409 | static int | |
2410 | nv50_fb_ctor(struct drm_framebuffer *fb) | |
2411 | { | |
2412 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
2413 | struct nouveau_drm *drm = nouveau_drm(fb->dev); | |
2414 | struct nouveau_bo *nvbo = nv_fb->nvbo; | |
8a423647 | 2415 | struct nv50_disp *disp = nv50_disp(fb->dev); |
8a423647 BS |
2416 | u8 kind = nouveau_bo_tile_layout(nvbo) >> 8; |
2417 | u8 tile = nvbo->tile_mode; | |
ab0af559 | 2418 | |
967e7bde | 2419 | if (drm->device.info.chipset >= 0xc0) |
8a423647 BS |
2420 | tile >>= 4; /* yep.. */ |
2421 | ||
ab0af559 BS |
2422 | switch (fb->depth) { |
2423 | case 8: nv_fb->r_format = 0x1e00; break; | |
2424 | case 15: nv_fb->r_format = 0xe900; break; | |
2425 | case 16: nv_fb->r_format = 0xe800; break; | |
2426 | case 24: | |
2427 | case 32: nv_fb->r_format = 0xcf00; break; | |
2428 | case 30: nv_fb->r_format = 0xd100; break; | |
2429 | default: | |
2430 | NV_ERROR(drm, "unknown depth %d\n", fb->depth); | |
2431 | return -EINVAL; | |
2432 | } | |
2433 | ||
648d4dfd | 2434 | if (disp->disp->oclass < G82_DISP) { |
8a423647 BS |
2435 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2436 | (fb->pitches[0] | 0x00100000); | |
2437 | nv_fb->r_format |= kind << 16; | |
2438 | } else | |
648d4dfd | 2439 | if (disp->disp->oclass < GF110_DISP) { |
8a423647 BS |
2440 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2441 | (fb->pitches[0] | 0x00100000); | |
ab0af559 | 2442 | } else { |
8a423647 BS |
2443 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2444 | (fb->pitches[0] | 0x01000000); | |
ab0af559 | 2445 | } |
8a423647 | 2446 | nv_fb->r_handle = 0xffff0000 | kind; |
ab0af559 | 2447 | |
f392ec4b BS |
2448 | return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0, |
2449 | drm->device.info.ram_user, kind); | |
ab0af559 BS |
2450 | } |
2451 | ||
26f6d88b BS |
2452 | /****************************************************************************** |
2453 | * Init | |
2454 | *****************************************************************************/ | |
ab0af559 | 2455 | |
2a44e499 | 2456 | void |
e225f446 | 2457 | nv50_display_fini(struct drm_device *dev) |
26f6d88b | 2458 | { |
26f6d88b BS |
2459 | } |
2460 | ||
2461 | int | |
e225f446 | 2462 | nv50_display_init(struct drm_device *dev) |
26f6d88b | 2463 | { |
9f9bdaaf BS |
2464 | struct nv50_disp *disp = nv50_disp(dev); |
2465 | struct drm_crtc *crtc; | |
2466 | u32 *push; | |
2467 | ||
2468 | push = evo_wait(nv50_mast(dev), 32); | |
2469 | if (!push) | |
2470 | return -EBUSY; | |
2471 | ||
2472 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2473 | struct nv50_sync *sync = nv50_sync(crtc); | |
4dc63933 ML |
2474 | |
2475 | nv50_crtc_lut_load(crtc); | |
9f9bdaaf | 2476 | nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); |
bdb8c212 | 2477 | } |
efd272a7 | 2478 | |
9f9bdaaf | 2479 | evo_mthd(push, 0x0088, 1); |
f45f55c4 | 2480 | evo_data(push, nv50_mast(dev)->base.sync.handle); |
9f9bdaaf BS |
2481 | evo_kick(push, nv50_mast(dev)); |
2482 | return 0; | |
26f6d88b BS |
2483 | } |
2484 | ||
2485 | void | |
e225f446 | 2486 | nv50_display_destroy(struct drm_device *dev) |
26f6d88b | 2487 | { |
e225f446 | 2488 | struct nv50_disp *disp = nv50_disp(dev); |
8a423647 BS |
2489 | struct nv50_fbdma *fbdma, *fbtmp; |
2490 | ||
2491 | list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) { | |
0ad72863 | 2492 | nv50_fbdma_fini(fbdma); |
8a423647 | 2493 | } |
bdb8c212 | 2494 | |
0ad72863 | 2495 | nv50_dmac_destroy(&disp->mast.base, disp->disp); |
26f6d88b | 2496 | |
816af2f2 | 2497 | nouveau_bo_unmap(disp->sync); |
04c8c210 MS |
2498 | if (disp->sync) |
2499 | nouveau_bo_unpin(disp->sync); | |
816af2f2 | 2500 | nouveau_bo_ref(NULL, &disp->sync); |
51beb428 | 2501 | |
77145f1c | 2502 | nouveau_display(dev)->priv = NULL; |
26f6d88b BS |
2503 | kfree(disp); |
2504 | } | |
2505 | ||
2506 | int | |
e225f446 | 2507 | nv50_display_create(struct drm_device *dev) |
26f6d88b | 2508 | { |
967e7bde | 2509 | struct nvif_device *device = &nouveau_drm(dev)->device; |
77145f1c | 2510 | struct nouveau_drm *drm = nouveau_drm(dev); |
77145f1c | 2511 | struct dcb_table *dcb = &drm->vbios.dcb; |
83fc083c | 2512 | struct drm_connector *connector, *tmp; |
e225f446 | 2513 | struct nv50_disp *disp; |
cb75d97e | 2514 | struct dcb_output *dcbe; |
7c5f6a87 | 2515 | int crtcs, ret, i; |
26f6d88b BS |
2516 | |
2517 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
2518 | if (!disp) | |
2519 | return -ENOMEM; | |
8a423647 | 2520 | INIT_LIST_HEAD(&disp->fbdma); |
77145f1c BS |
2521 | |
2522 | nouveau_display(dev)->priv = disp; | |
e225f446 BS |
2523 | nouveau_display(dev)->dtor = nv50_display_destroy; |
2524 | nouveau_display(dev)->init = nv50_display_init; | |
2525 | nouveau_display(dev)->fini = nv50_display_fini; | |
ab0af559 BS |
2526 | nouveau_display(dev)->fb_ctor = nv50_fb_ctor; |
2527 | nouveau_display(dev)->fb_dtor = nv50_fb_dtor; | |
0ad72863 | 2528 | disp->disp = &nouveau_display(dev)->disp; |
26f6d88b | 2529 | |
b5a794b0 BS |
2530 | /* small shared memory area we use for notifiers and semaphores */ |
2531 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
bb6178b0 | 2532 | 0, 0x0000, NULL, NULL, &disp->sync); |
b5a794b0 | 2533 | if (!ret) { |
547ad072 | 2534 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 2535 | if (!ret) { |
b5a794b0 | 2536 | ret = nouveau_bo_map(disp->sync); |
04c8c210 MS |
2537 | if (ret) |
2538 | nouveau_bo_unpin(disp->sync); | |
2539 | } | |
b5a794b0 BS |
2540 | if (ret) |
2541 | nouveau_bo_ref(NULL, &disp->sync); | |
2542 | } | |
2543 | ||
b5a794b0 BS |
2544 | if (ret) |
2545 | goto out; | |
2546 | ||
2547 | /* allocate master evo channel */ | |
a01ca78c | 2548 | ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset, |
410f3ec6 | 2549 | &disp->mast); |
b5a794b0 BS |
2550 | if (ret) |
2551 | goto out; | |
2552 | ||
438d99e3 | 2553 | /* create crtc objects to represent the hw heads */ |
648d4dfd | 2554 | if (disp->disp->oclass >= GF110_DISP) |
a01ca78c | 2555 | crtcs = nvif_rd32(&device->object, 0x022448); |
63718a07 BS |
2556 | else |
2557 | crtcs = 2; | |
2558 | ||
7c5f6a87 | 2559 | for (i = 0; i < crtcs; i++) { |
0ad72863 | 2560 | ret = nv50_crtc_create(dev, i); |
438d99e3 BS |
2561 | if (ret) |
2562 | goto out; | |
2563 | } | |
2564 | ||
83fc083c BS |
2565 | /* create encoder/connector objects based on VBIOS DCB table */ |
2566 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
2567 | connector = nouveau_connector_create(dev, dcbe->connector); | |
2568 | if (IS_ERR(connector)) | |
2569 | continue; | |
2570 | ||
eb6313ad BS |
2571 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
2572 | switch (dcbe->type) { | |
2573 | case DCB_OUTPUT_TMDS: | |
2574 | case DCB_OUTPUT_LVDS: | |
2575 | case DCB_OUTPUT_DP: | |
2576 | ret = nv50_sor_create(connector, dcbe); | |
2577 | break; | |
2578 | case DCB_OUTPUT_ANALOG: | |
2579 | ret = nv50_dac_create(connector, dcbe); | |
2580 | break; | |
2581 | default: | |
2582 | ret = -ENODEV; | |
2583 | break; | |
2584 | } | |
2585 | } else { | |
2586 | ret = nv50_pior_create(connector, dcbe); | |
83fc083c BS |
2587 | } |
2588 | ||
eb6313ad BS |
2589 | if (ret) { |
2590 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", | |
2591 | dcbe->location, dcbe->type, | |
2592 | ffs(dcbe->or) - 1, ret); | |
94f54f53 | 2593 | ret = 0; |
83fc083c BS |
2594 | } |
2595 | } | |
2596 | ||
2597 | /* cull any connectors we created that don't have an encoder */ | |
2598 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
2599 | if (connector->encoder_ids[0]) | |
2600 | continue; | |
2601 | ||
77145f1c | 2602 | NV_WARN(drm, "%s has no encoders, removing\n", |
8c6c361a | 2603 | connector->name); |
83fc083c BS |
2604 | connector->funcs->destroy(connector); |
2605 | } | |
2606 | ||
26f6d88b BS |
2607 | out: |
2608 | if (ret) | |
e225f446 | 2609 | nv50_display_destroy(dev); |
26f6d88b BS |
2610 | return ret; |
2611 | } |