Commit | Line | Data |
---|---|---|
56d237d2 | 1 | /* |
26f6d88b BS |
2 | * Copyright 2011 Red Hat Inc. |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
34fd3e5d | 26 | #include <linux/hdmi.h> |
83fc083c | 27 | |
760285e7 | 28 | #include <drm/drmP.h> |
ad633619 | 29 | #include <drm/drm_atomic.h> |
973f10c2 | 30 | #include <drm/drm_atomic_helper.h> |
760285e7 | 31 | #include <drm/drm_crtc_helper.h> |
4874322e | 32 | #include <drm/drm_dp_helper.h> |
b516a9ef | 33 | #include <drm/drm_fb_helper.h> |
ad633619 | 34 | #include <drm/drm_plane_helper.h> |
34fd3e5d | 35 | #include <drm/drm_edid.h> |
26f6d88b | 36 | |
fdb751ef | 37 | #include <nvif/class.h> |
845f2725 | 38 | #include <nvif/cl0002.h> |
7568b106 BS |
39 | #include <nvif/cl5070.h> |
40 | #include <nvif/cl507a.h> | |
41 | #include <nvif/cl507b.h> | |
42 | #include <nvif/cl507c.h> | |
43 | #include <nvif/cl507d.h> | |
44 | #include <nvif/cl507e.h> | |
973f10c2 | 45 | #include <nvif/event.h> |
fdb751ef | 46 | |
4dc28134 | 47 | #include "nouveau_drv.h" |
77145f1c BS |
48 | #include "nouveau_dma.h" |
49 | #include "nouveau_gem.h" | |
26f6d88b BS |
50 | #include "nouveau_connector.h" |
51 | #include "nouveau_encoder.h" | |
52 | #include "nouveau_crtc.h" | |
f589be88 | 53 | #include "nouveau_fence.h" |
839ca903 | 54 | #include "nouveau_fbcon.h" |
3a89cd02 | 55 | #include "nv50_display.h" |
26f6d88b | 56 | |
8a46438a BS |
57 | #define EVO_DMA_NR 9 |
58 | ||
bdb8c212 | 59 | #define EVO_MASTER (0x00) |
a63a97eb | 60 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
61 | #define EVO_OVLY(c) (0x05 + (c)) |
62 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
63 | #define EVO_CURS(c) (0x0d + (c)) |
64 | ||
816af2f2 BS |
65 | /* offsets in shared sync bo of various structures */ |
66 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
9f9bdaaf BS |
67 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
68 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) | |
69 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) | |
973f10c2 BS |
70 | #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20) |
71 | #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30) | |
816af2f2 | 72 | |
3dbd036b BS |
73 | /****************************************************************************** |
74 | * Atomic state | |
75 | *****************************************************************************/ | |
839ca903 BS |
76 | #define nv50_atom(p) container_of((p), struct nv50_atom, state) |
77 | ||
78 | struct nv50_atom { | |
79 | struct drm_atomic_state state; | |
80 | ||
81 | struct list_head outp; | |
82 | bool lock_core; | |
83 | bool flush_disable; | |
84 | }; | |
85 | ||
86 | struct nv50_outp_atom { | |
87 | struct list_head head; | |
88 | ||
89 | struct drm_encoder *encoder; | |
90 | bool flush_disable; | |
91 | ||
92 | union { | |
93 | struct { | |
94 | bool ctrl:1; | |
95 | }; | |
96 | u8 mask; | |
97 | } clr; | |
98 | ||
99 | union { | |
100 | struct { | |
101 | bool ctrl:1; | |
102 | }; | |
103 | u8 mask; | |
104 | } set; | |
105 | }; | |
106 | ||
3dbd036b BS |
107 | #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state) |
108 | ||
109 | struct nv50_head_atom { | |
110 | struct drm_crtc_state state; | |
111 | ||
c4e6812c BS |
112 | struct { |
113 | u16 iW; | |
114 | u16 iH; | |
115 | u16 oW; | |
116 | u16 oH; | |
117 | } view; | |
118 | ||
3dbd036b BS |
119 | struct nv50_head_mode { |
120 | bool interlace; | |
121 | u32 clock; | |
122 | struct { | |
123 | u16 active; | |
124 | u16 synce; | |
125 | u16 blanke; | |
126 | u16 blanks; | |
127 | } h; | |
128 | struct { | |
129 | u32 active; | |
130 | u16 synce; | |
131 | u16 blanke; | |
132 | u16 blanks; | |
133 | u16 blank2s; | |
134 | u16 blank2e; | |
135 | u16 blankus; | |
136 | } v; | |
137 | } mode; | |
138 | ||
a7ae1561 BS |
139 | struct { |
140 | u32 handle; | |
141 | u64 offset:40; | |
142 | } lut; | |
143 | ||
ad633619 BS |
144 | struct { |
145 | bool visible; | |
146 | u32 handle; | |
147 | u64 offset:40; | |
148 | u8 format; | |
149 | u8 kind:7; | |
150 | u8 layout:1; | |
151 | u8 block:4; | |
152 | u32 pitch:20; | |
153 | u16 x; | |
154 | u16 y; | |
155 | u16 w; | |
156 | u16 h; | |
157 | } core; | |
158 | ||
ea8ee390 BS |
159 | struct { |
160 | bool visible; | |
161 | u32 handle; | |
162 | u64 offset:40; | |
163 | u8 layout:1; | |
164 | u8 format:1; | |
165 | } curs; | |
166 | ||
ad633619 BS |
167 | struct { |
168 | u8 depth; | |
169 | u8 cpp; | |
170 | u16 x; | |
171 | u16 y; | |
172 | u16 w; | |
173 | u16 h; | |
174 | } base; | |
175 | ||
6bbab3b6 BS |
176 | struct { |
177 | u8 cpp; | |
178 | } ovly; | |
179 | ||
7e91833d BS |
180 | struct { |
181 | bool enable:1; | |
182 | u8 bits:2; | |
183 | u8 mode:4; | |
184 | } dither; | |
185 | ||
7e08d67c BS |
186 | struct { |
187 | struct { | |
188 | u16 cos:12; | |
189 | u16 sin:12; | |
190 | } sat; | |
191 | } procamp; | |
192 | ||
ad633619 BS |
193 | union { |
194 | struct { | |
195 | bool core:1; | |
ea8ee390 | 196 | bool curs:1; |
ad633619 BS |
197 | }; |
198 | u8 mask; | |
199 | } clr; | |
200 | ||
3dbd036b BS |
201 | union { |
202 | struct { | |
ad633619 | 203 | bool core:1; |
ea8ee390 | 204 | bool curs:1; |
ad633619 | 205 | bool view:1; |
3dbd036b | 206 | bool mode:1; |
6bbab3b6 BS |
207 | bool base:1; |
208 | bool ovly:1; | |
7e91833d | 209 | bool dither:1; |
7e08d67c | 210 | bool procamp:1; |
3dbd036b BS |
211 | }; |
212 | u16 mask; | |
213 | } set; | |
214 | }; | |
215 | ||
839ca903 BS |
216 | static inline struct nv50_head_atom * |
217 | nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) | |
218 | { | |
219 | struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc); | |
220 | if (IS_ERR(statec)) | |
221 | return (void *)statec; | |
222 | return nv50_head_atom(statec); | |
223 | } | |
224 | ||
973f10c2 BS |
225 | #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state) |
226 | ||
227 | struct nv50_wndw_atom { | |
228 | struct drm_plane_state state; | |
229 | u8 interval; | |
230 | ||
231 | struct drm_rect clip; | |
232 | ||
233 | struct { | |
234 | u32 handle; | |
235 | u16 offset:12; | |
236 | bool awaken:1; | |
237 | } ntfy; | |
238 | ||
239 | struct { | |
240 | u32 handle; | |
241 | u16 offset:12; | |
242 | u32 acquire; | |
243 | u32 release; | |
244 | } sema; | |
245 | ||
246 | struct { | |
247 | u8 enable:2; | |
248 | } lut; | |
249 | ||
250 | struct { | |
251 | u8 mode:2; | |
252 | u8 interval:4; | |
253 | ||
254 | u8 format; | |
255 | u8 kind:7; | |
256 | u8 layout:1; | |
257 | u8 block:4; | |
258 | u32 pitch:20; | |
259 | u16 w; | |
260 | u16 h; | |
261 | ||
262 | u32 handle; | |
263 | u64 offset; | |
264 | } image; | |
265 | ||
266 | struct { | |
267 | u16 x; | |
268 | u16 y; | |
269 | } point; | |
270 | ||
271 | union { | |
272 | struct { | |
273 | bool ntfy:1; | |
274 | bool sema:1; | |
275 | bool image:1; | |
276 | }; | |
277 | u8 mask; | |
278 | } clr; | |
279 | ||
280 | union { | |
281 | struct { | |
282 | bool ntfy:1; | |
283 | bool sema:1; | |
284 | bool image:1; | |
285 | bool lut:1; | |
286 | bool point:1; | |
287 | }; | |
288 | u8 mask; | |
289 | } set; | |
290 | }; | |
291 | ||
b5a794b0 BS |
292 | /****************************************************************************** |
293 | * EVO channel | |
294 | *****************************************************************************/ | |
295 | ||
e225f446 | 296 | struct nv50_chan { |
0ad72863 | 297 | struct nvif_object user; |
a01ca78c | 298 | struct nvif_device *device; |
b5a794b0 BS |
299 | }; |
300 | ||
301 | static int | |
a01ca78c | 302 | nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 303 | const s32 *oclass, u8 head, void *data, u32 size, |
a01ca78c | 304 | struct nv50_chan *chan) |
b5a794b0 | 305 | { |
41a63406 BS |
306 | struct nvif_sclass *sclass; |
307 | int ret, i, n; | |
6af5289e | 308 | |
a01ca78c BS |
309 | chan->device = device; |
310 | ||
41a63406 | 311 | ret = n = nvif_object_sclass_get(disp, &sclass); |
6af5289e BS |
312 | if (ret < 0) |
313 | return ret; | |
314 | ||
410f3ec6 | 315 | while (oclass[0]) { |
41a63406 BS |
316 | for (i = 0; i < n; i++) { |
317 | if (sclass[i].oclass == oclass[0]) { | |
fcf3f91c | 318 | ret = nvif_object_init(disp, 0, oclass[0], |
a01ca78c | 319 | data, size, &chan->user); |
6af5289e BS |
320 | if (ret == 0) |
321 | nvif_object_map(&chan->user); | |
41a63406 | 322 | nvif_object_sclass_put(&sclass); |
6af5289e BS |
323 | return ret; |
324 | } | |
b76f1529 | 325 | } |
6af5289e | 326 | oclass++; |
410f3ec6 | 327 | } |
6af5289e | 328 | |
41a63406 | 329 | nvif_object_sclass_put(&sclass); |
410f3ec6 | 330 | return -ENOSYS; |
b5a794b0 BS |
331 | } |
332 | ||
333 | static void | |
0ad72863 | 334 | nv50_chan_destroy(struct nv50_chan *chan) |
b5a794b0 | 335 | { |
0ad72863 | 336 | nvif_object_fini(&chan->user); |
b5a794b0 BS |
337 | } |
338 | ||
339 | /****************************************************************************** | |
340 | * PIO EVO channel | |
341 | *****************************************************************************/ | |
342 | ||
e225f446 BS |
343 | struct nv50_pioc { |
344 | struct nv50_chan base; | |
b5a794b0 BS |
345 | }; |
346 | ||
347 | static void | |
0ad72863 | 348 | nv50_pioc_destroy(struct nv50_pioc *pioc) |
b5a794b0 | 349 | { |
0ad72863 | 350 | nv50_chan_destroy(&pioc->base); |
b5a794b0 BS |
351 | } |
352 | ||
353 | static int | |
a01ca78c | 354 | nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 355 | const s32 *oclass, u8 head, void *data, u32 size, |
a01ca78c | 356 | struct nv50_pioc *pioc) |
b5a794b0 | 357 | { |
a01ca78c BS |
358 | return nv50_chan_create(device, disp, oclass, head, data, size, |
359 | &pioc->base); | |
410f3ec6 BS |
360 | } |
361 | ||
410f3ec6 BS |
362 | /****************************************************************************** |
363 | * Overlay Immediate | |
364 | *****************************************************************************/ | |
365 | ||
366 | struct nv50_oimm { | |
367 | struct nv50_pioc base; | |
368 | }; | |
369 | ||
370 | static int | |
a01ca78c BS |
371 | nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp, |
372 | int head, struct nv50_oimm *oimm) | |
410f3ec6 | 373 | { |
648d4dfd | 374 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
375 | .head = head, |
376 | }; | |
315a8b2e | 377 | static const s32 oclass[] = { |
648d4dfd BS |
378 | GK104_DISP_OVERLAY, |
379 | GF110_DISP_OVERLAY, | |
380 | GT214_DISP_OVERLAY, | |
381 | G82_DISP_OVERLAY, | |
382 | NV50_DISP_OVERLAY, | |
410f3ec6 BS |
383 | 0 |
384 | }; | |
385 | ||
a01ca78c BS |
386 | return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args), |
387 | &oimm->base); | |
b5a794b0 BS |
388 | } |
389 | ||
390 | /****************************************************************************** | |
391 | * DMA EVO channel | |
392 | *****************************************************************************/ | |
393 | ||
accdea2e BS |
394 | struct nv50_dmac_ctxdma { |
395 | struct list_head head; | |
396 | struct nvif_object object; | |
397 | }; | |
398 | ||
e225f446 BS |
399 | struct nv50_dmac { |
400 | struct nv50_chan base; | |
3376ee37 BS |
401 | dma_addr_t handle; |
402 | u32 *ptr; | |
59ad1465 | 403 | |
0ad72863 BS |
404 | struct nvif_object sync; |
405 | struct nvif_object vram; | |
accdea2e | 406 | struct list_head ctxdma; |
0ad72863 | 407 | |
59ad1465 DV |
408 | /* Protects against concurrent pushbuf access to this channel, lock is |
409 | * grabbed by evo_wait (if the pushbuf reservation is successful) and | |
410 | * dropped again by evo_kick. */ | |
411 | struct mutex lock; | |
b5a794b0 BS |
412 | }; |
413 | ||
accdea2e BS |
414 | static void |
415 | nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma) | |
416 | { | |
417 | nvif_object_fini(&ctxdma->object); | |
418 | list_del(&ctxdma->head); | |
419 | kfree(ctxdma); | |
420 | } | |
421 | ||
422 | static struct nv50_dmac_ctxdma * | |
f00f0e21 | 423 | nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb) |
accdea2e BS |
424 | { |
425 | struct nouveau_drm *drm = nouveau_drm(fb->base.dev); | |
426 | struct nv50_dmac_ctxdma *ctxdma; | |
f00f0e21 BS |
427 | const u8 kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8; |
428 | const u32 handle = 0xfb000000 | kind; | |
accdea2e BS |
429 | struct { |
430 | struct nv_dma_v0 base; | |
431 | union { | |
432 | struct nv50_dma_v0 nv50; | |
433 | struct gf100_dma_v0 gf100; | |
434 | struct gf119_dma_v0 gf119; | |
435 | }; | |
436 | } args = {}; | |
437 | u32 argc = sizeof(args.base); | |
438 | int ret; | |
439 | ||
440 | list_for_each_entry(ctxdma, &dmac->ctxdma, head) { | |
441 | if (ctxdma->object.handle == handle) | |
442 | return ctxdma; | |
443 | } | |
444 | ||
445 | if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) | |
446 | return ERR_PTR(-ENOMEM); | |
447 | list_add(&ctxdma->head, &dmac->ctxdma); | |
448 | ||
449 | args.base.target = NV_DMA_V0_TARGET_VRAM; | |
450 | args.base.access = NV_DMA_V0_ACCESS_RDWR; | |
451 | args.base.start = 0; | |
1167c6bc | 452 | args.base.limit = drm->client.device.info.ram_user - 1; |
accdea2e | 453 | |
1167c6bc | 454 | if (drm->client.device.info.chipset < 0x80) { |
accdea2e BS |
455 | args.nv50.part = NV50_DMA_V0_PART_256; |
456 | argc += sizeof(args.nv50); | |
457 | } else | |
1167c6bc | 458 | if (drm->client.device.info.chipset < 0xc0) { |
accdea2e BS |
459 | args.nv50.part = NV50_DMA_V0_PART_256; |
460 | args.nv50.kind = kind; | |
461 | argc += sizeof(args.nv50); | |
462 | } else | |
1167c6bc | 463 | if (drm->client.device.info.chipset < 0xd0) { |
accdea2e BS |
464 | args.gf100.kind = kind; |
465 | argc += sizeof(args.gf100); | |
466 | } else { | |
467 | args.gf119.page = GF119_DMA_V0_PAGE_LP; | |
468 | args.gf119.kind = kind; | |
469 | argc += sizeof(args.gf119); | |
470 | } | |
471 | ||
472 | ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY, | |
473 | &args, argc, &ctxdma->object); | |
474 | if (ret) { | |
475 | nv50_dmac_ctxdma_del(ctxdma); | |
476 | return ERR_PTR(ret); | |
477 | } | |
478 | ||
479 | return ctxdma; | |
480 | } | |
481 | ||
b5a794b0 | 482 | static void |
0ad72863 | 483 | nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) |
b5a794b0 | 484 | { |
a01ca78c | 485 | struct nvif_device *device = dmac->base.device; |
accdea2e BS |
486 | struct nv50_dmac_ctxdma *ctxdma, *ctxtmp; |
487 | ||
488 | list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) { | |
489 | nv50_dmac_ctxdma_del(ctxdma); | |
490 | } | |
a01ca78c | 491 | |
0ad72863 BS |
492 | nvif_object_fini(&dmac->vram); |
493 | nvif_object_fini(&dmac->sync); | |
494 | ||
495 | nv50_chan_destroy(&dmac->base); | |
496 | ||
b5a794b0 | 497 | if (dmac->ptr) { |
26c9e8ef BS |
498 | struct device *dev = nvxx_device(device)->dev; |
499 | dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle); | |
b5a794b0 | 500 | } |
b5a794b0 BS |
501 | } |
502 | ||
47057302 | 503 | static int |
a01ca78c | 504 | nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 505 | const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, |
e225f446 | 506 | struct nv50_dmac *dmac) |
47057302 | 507 | { |
648d4dfd | 508 | struct nv50_disp_core_channel_dma_v0 *args = data; |
0ad72863 | 509 | struct nvif_object pushbuf; |
47057302 BS |
510 | int ret; |
511 | ||
59ad1465 DV |
512 | mutex_init(&dmac->lock); |
513 | ||
26c9e8ef BS |
514 | dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE, |
515 | &dmac->handle, GFP_KERNEL); | |
47057302 BS |
516 | if (!dmac->ptr) |
517 | return -ENOMEM; | |
518 | ||
fcf3f91c BS |
519 | ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, |
520 | &(struct nv_dma_v0) { | |
4acfd707 BS |
521 | .target = NV_DMA_V0_TARGET_PCI_US, |
522 | .access = NV_DMA_V0_ACCESS_RD, | |
47057302 BS |
523 | .start = dmac->handle + 0x0000, |
524 | .limit = dmac->handle + 0x0fff, | |
4acfd707 | 525 | }, sizeof(struct nv_dma_v0), &pushbuf); |
b5a794b0 | 526 | if (ret) |
47057302 | 527 | return ret; |
b5a794b0 | 528 | |
bf81df9b BS |
529 | args->pushbuf = nvif_handle(&pushbuf); |
530 | ||
a01ca78c BS |
531 | ret = nv50_chan_create(device, disp, oclass, head, data, size, |
532 | &dmac->base); | |
0ad72863 | 533 | nvif_object_fini(&pushbuf); |
47057302 BS |
534 | if (ret) |
535 | return ret; | |
536 | ||
a01ca78c | 537 | ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, |
4acfd707 BS |
538 | &(struct nv_dma_v0) { |
539 | .target = NV_DMA_V0_TARGET_VRAM, | |
540 | .access = NV_DMA_V0_ACCESS_RDWR, | |
47057302 BS |
541 | .start = syncbuf + 0x0000, |
542 | .limit = syncbuf + 0x0fff, | |
4acfd707 | 543 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 544 | &dmac->sync); |
47057302 BS |
545 | if (ret) |
546 | return ret; | |
547 | ||
a01ca78c | 548 | ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, |
4acfd707 BS |
549 | &(struct nv_dma_v0) { |
550 | .target = NV_DMA_V0_TARGET_VRAM, | |
551 | .access = NV_DMA_V0_ACCESS_RDWR, | |
b5a794b0 | 552 | .start = 0, |
f392ec4b | 553 | .limit = device->info.ram_user - 1, |
4acfd707 | 554 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 555 | &dmac->vram); |
b5a794b0 | 556 | if (ret) |
47057302 BS |
557 | return ret; |
558 | ||
accdea2e | 559 | INIT_LIST_HEAD(&dmac->ctxdma); |
b5a794b0 BS |
560 | return ret; |
561 | } | |
562 | ||
410f3ec6 BS |
563 | /****************************************************************************** |
564 | * Core | |
565 | *****************************************************************************/ | |
566 | ||
e225f446 BS |
567 | struct nv50_mast { |
568 | struct nv50_dmac base; | |
b5a794b0 BS |
569 | }; |
570 | ||
410f3ec6 | 571 | static int |
a01ca78c BS |
572 | nv50_core_create(struct nvif_device *device, struct nvif_object *disp, |
573 | u64 syncbuf, struct nv50_mast *core) | |
410f3ec6 | 574 | { |
648d4dfd BS |
575 | struct nv50_disp_core_channel_dma_v0 args = { |
576 | .pushbuf = 0xb0007d00, | |
410f3ec6 | 577 | }; |
315a8b2e | 578 | static const s32 oclass[] = { |
ed828666 | 579 | GP102_DISP_CORE_CHANNEL_DMA, |
f9d5cbb3 | 580 | GP100_DISP_CORE_CHANNEL_DMA, |
db1eb528 | 581 | GM200_DISP_CORE_CHANNEL_DMA, |
648d4dfd BS |
582 | GM107_DISP_CORE_CHANNEL_DMA, |
583 | GK110_DISP_CORE_CHANNEL_DMA, | |
584 | GK104_DISP_CORE_CHANNEL_DMA, | |
585 | GF110_DISP_CORE_CHANNEL_DMA, | |
586 | GT214_DISP_CORE_CHANNEL_DMA, | |
587 | GT206_DISP_CORE_CHANNEL_DMA, | |
588 | GT200_DISP_CORE_CHANNEL_DMA, | |
589 | G82_DISP_CORE_CHANNEL_DMA, | |
590 | NV50_DISP_CORE_CHANNEL_DMA, | |
410f3ec6 BS |
591 | 0 |
592 | }; | |
593 | ||
a01ca78c BS |
594 | return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args), |
595 | syncbuf, &core->base); | |
410f3ec6 BS |
596 | } |
597 | ||
598 | /****************************************************************************** | |
599 | * Base | |
600 | *****************************************************************************/ | |
b5a794b0 | 601 | |
e225f446 BS |
602 | struct nv50_sync { |
603 | struct nv50_dmac base; | |
9f9bdaaf BS |
604 | u32 addr; |
605 | u32 data; | |
3376ee37 BS |
606 | }; |
607 | ||
410f3ec6 | 608 | static int |
a01ca78c BS |
609 | nv50_base_create(struct nvif_device *device, struct nvif_object *disp, |
610 | int head, u64 syncbuf, struct nv50_sync *base) | |
410f3ec6 | 611 | { |
648d4dfd BS |
612 | struct nv50_disp_base_channel_dma_v0 args = { |
613 | .pushbuf = 0xb0007c00 | head, | |
410f3ec6 BS |
614 | .head = head, |
615 | }; | |
315a8b2e | 616 | static const s32 oclass[] = { |
648d4dfd BS |
617 | GK110_DISP_BASE_CHANNEL_DMA, |
618 | GK104_DISP_BASE_CHANNEL_DMA, | |
619 | GF110_DISP_BASE_CHANNEL_DMA, | |
620 | GT214_DISP_BASE_CHANNEL_DMA, | |
621 | GT200_DISP_BASE_CHANNEL_DMA, | |
622 | G82_DISP_BASE_CHANNEL_DMA, | |
623 | NV50_DISP_BASE_CHANNEL_DMA, | |
410f3ec6 BS |
624 | 0 |
625 | }; | |
626 | ||
a01ca78c | 627 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
410f3ec6 BS |
628 | syncbuf, &base->base); |
629 | } | |
630 | ||
631 | /****************************************************************************** | |
632 | * Overlay | |
633 | *****************************************************************************/ | |
634 | ||
e225f446 BS |
635 | struct nv50_ovly { |
636 | struct nv50_dmac base; | |
b5a794b0 | 637 | }; |
f20ce962 | 638 | |
410f3ec6 | 639 | static int |
a01ca78c BS |
640 | nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp, |
641 | int head, u64 syncbuf, struct nv50_ovly *ovly) | |
410f3ec6 | 642 | { |
648d4dfd BS |
643 | struct nv50_disp_overlay_channel_dma_v0 args = { |
644 | .pushbuf = 0xb0007e00 | head, | |
410f3ec6 BS |
645 | .head = head, |
646 | }; | |
315a8b2e | 647 | static const s32 oclass[] = { |
648d4dfd BS |
648 | GK104_DISP_OVERLAY_CONTROL_DMA, |
649 | GF110_DISP_OVERLAY_CONTROL_DMA, | |
650 | GT214_DISP_OVERLAY_CHANNEL_DMA, | |
651 | GT200_DISP_OVERLAY_CHANNEL_DMA, | |
652 | G82_DISP_OVERLAY_CHANNEL_DMA, | |
653 | NV50_DISP_OVERLAY_CHANNEL_DMA, | |
410f3ec6 BS |
654 | 0 |
655 | }; | |
656 | ||
a01ca78c | 657 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
410f3ec6 BS |
658 | syncbuf, &ovly->base); |
659 | } | |
26f6d88b | 660 | |
e225f446 | 661 | struct nv50_head { |
dd0e3d53 | 662 | struct nouveau_crtc base; |
e225f446 BS |
663 | struct nv50_ovly ovly; |
664 | struct nv50_oimm oimm; | |
b5a794b0 BS |
665 | }; |
666 | ||
e225f446 | 667 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
e225f446 BS |
668 | #define nv50_ovly(c) (&nv50_head(c)->ovly) |
669 | #define nv50_oimm(c) (&nv50_head(c)->oimm) | |
670 | #define nv50_chan(c) (&(c)->base.base) | |
0ad72863 BS |
671 | #define nv50_vers(c) nv50_chan(c)->user.oclass |
672 | ||
e225f446 | 673 | struct nv50_disp { |
0ad72863 | 674 | struct nvif_object *disp; |
e225f446 | 675 | struct nv50_mast mast; |
b5a794b0 | 676 | |
b5a794b0 | 677 | struct nouveau_bo *sync; |
839ca903 BS |
678 | |
679 | struct mutex mutex; | |
dd0e3d53 BS |
680 | }; |
681 | ||
e225f446 BS |
682 | static struct nv50_disp * |
683 | nv50_disp(struct drm_device *dev) | |
26f6d88b | 684 | { |
77145f1c | 685 | return nouveau_display(dev)->priv; |
26f6d88b BS |
686 | } |
687 | ||
e225f446 | 688 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
b5a794b0 | 689 | |
bdb8c212 BS |
690 | /****************************************************************************** |
691 | * EVO channel helpers | |
692 | *****************************************************************************/ | |
51beb428 | 693 | static u32 * |
b5a794b0 | 694 | evo_wait(void *evoc, int nr) |
51beb428 | 695 | { |
e225f446 | 696 | struct nv50_dmac *dmac = evoc; |
a01ca78c | 697 | struct nvif_device *device = dmac->base.device; |
0ad72863 | 698 | u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; |
51beb428 | 699 | |
59ad1465 | 700 | mutex_lock(&dmac->lock); |
de8268c5 | 701 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
b5a794b0 | 702 | dmac->ptr[put] = 0x20000000; |
51beb428 | 703 | |
0ad72863 | 704 | nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); |
54442040 BS |
705 | if (nvif_msec(device, 2000, |
706 | if (!nvif_rd32(&dmac->base.user, 0x0004)) | |
707 | break; | |
708 | ) < 0) { | |
59ad1465 | 709 | mutex_unlock(&dmac->lock); |
8dfe162a | 710 | pr_err("nouveau: evo channel stalled\n"); |
51beb428 BS |
711 | return NULL; |
712 | } | |
713 | ||
714 | put = 0; | |
715 | } | |
716 | ||
b5a794b0 | 717 | return dmac->ptr + put; |
51beb428 BS |
718 | } |
719 | ||
720 | static void | |
b5a794b0 | 721 | evo_kick(u32 *push, void *evoc) |
51beb428 | 722 | { |
e225f446 | 723 | struct nv50_dmac *dmac = evoc; |
0ad72863 | 724 | nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
59ad1465 | 725 | mutex_unlock(&dmac->lock); |
51beb428 BS |
726 | } |
727 | ||
8dfe162a JP |
728 | #define evo_mthd(p, m, s) do { \ |
729 | const u32 _m = (m), _s = (s); \ | |
730 | if (drm_debug & DRM_UT_KMS) \ | |
731 | pr_err("%04x %d %s\n", _m, _s, __func__); \ | |
732 | *((p)++) = ((_s << 18) | _m); \ | |
2b1930c3 | 733 | } while(0) |
7f55a072 | 734 | |
8dfe162a JP |
735 | #define evo_data(p, d) do { \ |
736 | const u32 _d = (d); \ | |
737 | if (drm_debug & DRM_UT_KMS) \ | |
738 | pr_err("\t%08x\n", _d); \ | |
739 | *((p)++) = _d; \ | |
2b1930c3 | 740 | } while(0) |
51beb428 | 741 | |
973f10c2 BS |
742 | /****************************************************************************** |
743 | * Plane | |
744 | *****************************************************************************/ | |
745 | #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane) | |
746 | ||
747 | struct nv50_wndw { | |
748 | const struct nv50_wndw_func *func; | |
749 | struct nv50_dmac *dmac; | |
750 | ||
751 | struct drm_plane plane; | |
752 | ||
753 | struct nvif_notify notify; | |
754 | u16 ntfy; | |
755 | u16 sema; | |
756 | u32 data; | |
973f10c2 BS |
757 | }; |
758 | ||
759 | struct nv50_wndw_func { | |
760 | void *(*dtor)(struct nv50_wndw *); | |
761 | int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, | |
762 | struct nv50_head_atom *asyh); | |
763 | void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, | |
764 | struct nv50_head_atom *asyh); | |
765 | void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh, | |
766 | struct nv50_wndw_atom *asyw); | |
767 | ||
768 | void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
769 | void (*sema_clr)(struct nv50_wndw *); | |
770 | void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
771 | void (*ntfy_clr)(struct nv50_wndw *); | |
772 | int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
773 | void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
774 | void (*image_clr)(struct nv50_wndw *); | |
775 | void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
776 | void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
777 | ||
778 | u32 (*update)(struct nv50_wndw *, u32 interlock); | |
779 | }; | |
780 | ||
781 | static int | |
782 | nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
783 | { | |
784 | if (asyw->set.ntfy) | |
785 | return wndw->func->ntfy_wait_begun(wndw, asyw); | |
786 | return 0; | |
787 | } | |
788 | ||
789 | static u32 | |
790 | nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush, | |
791 | struct nv50_wndw_atom *asyw) | |
792 | { | |
793 | if (asyw->clr.sema && (!asyw->set.sema || flush)) | |
794 | wndw->func->sema_clr(wndw); | |
795 | if (asyw->clr.ntfy && (!asyw->set.ntfy || flush)) | |
796 | wndw->func->ntfy_clr(wndw); | |
797 | if (asyw->clr.image && (!asyw->set.image || flush)) | |
798 | wndw->func->image_clr(wndw); | |
799 | ||
800 | return flush ? wndw->func->update(wndw, interlock) : 0; | |
801 | } | |
802 | ||
803 | static u32 | |
804 | nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock, | |
805 | struct nv50_wndw_atom *asyw) | |
806 | { | |
807 | if (interlock) { | |
808 | asyw->image.mode = 0; | |
809 | asyw->image.interval = 1; | |
810 | } | |
811 | ||
812 | if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); | |
813 | if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); | |
814 | if (asyw->set.image) wndw->func->image_set(wndw, asyw); | |
815 | if (asyw->set.lut ) wndw->func->lut (wndw, asyw); | |
816 | if (asyw->set.point) wndw->func->point (wndw, asyw); | |
817 | ||
818 | return wndw->func->update(wndw, interlock); | |
819 | } | |
820 | ||
821 | static void | |
822 | nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, | |
823 | struct nv50_wndw_atom *asyw, | |
824 | struct nv50_head_atom *asyh) | |
825 | { | |
826 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); | |
827 | NV_ATOMIC(drm, "%s release\n", wndw->plane.name); | |
828 | wndw->func->release(wndw, asyw, asyh); | |
829 | asyw->ntfy.handle = 0; | |
830 | asyw->sema.handle = 0; | |
831 | } | |
832 | ||
833 | static int | |
834 | nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, | |
835 | struct nv50_wndw_atom *asyw, | |
f42c5707 | 836 | struct nv50_head_atom *asyh) |
973f10c2 BS |
837 | { |
838 | struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb); | |
839 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); | |
840 | int ret; | |
841 | ||
842 | NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); | |
843 | asyw->clip.x1 = 0; | |
844 | asyw->clip.y1 = 0; | |
845 | asyw->clip.x2 = asyh->state.mode.hdisplay; | |
846 | asyw->clip.y2 = asyh->state.mode.vdisplay; | |
847 | ||
848 | asyw->image.w = fb->base.width; | |
849 | asyw->image.h = fb->base.height; | |
850 | asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8; | |
612fb5d9 | 851 | |
f42c5707 BS |
852 | if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) |
853 | asyw->interval = 0; | |
854 | else | |
855 | asyw->interval = 1; | |
612fb5d9 | 856 | |
973f10c2 BS |
857 | if (asyw->image.kind) { |
858 | asyw->image.layout = 0; | |
1167c6bc | 859 | if (drm->client.device.info.chipset >= 0xc0) |
973f10c2 BS |
860 | asyw->image.block = fb->nvbo->tile_mode >> 4; |
861 | else | |
862 | asyw->image.block = fb->nvbo->tile_mode; | |
863 | asyw->image.pitch = (fb->base.pitches[0] / 4) << 4; | |
864 | } else { | |
865 | asyw->image.layout = 1; | |
866 | asyw->image.block = 0; | |
867 | asyw->image.pitch = fb->base.pitches[0]; | |
868 | } | |
869 | ||
870 | ret = wndw->func->acquire(wndw, asyw, asyh); | |
871 | if (ret) | |
872 | return ret; | |
873 | ||
874 | if (asyw->set.image) { | |
875 | if (!(asyw->image.mode = asyw->interval ? 0 : 1)) | |
876 | asyw->image.interval = asyw->interval; | |
877 | else | |
878 | asyw->image.interval = 0; | |
879 | } | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | static int | |
885 | nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) | |
886 | { | |
887 | struct nouveau_drm *drm = nouveau_drm(plane->dev); | |
888 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
839ca903 BS |
889 | struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); |
890 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); | |
973f10c2 BS |
891 | struct nv50_head_atom *harm = NULL, *asyh = NULL; |
892 | bool varm = false, asyv = false, asym = false; | |
893 | int ret; | |
894 | ||
973f10c2 BS |
895 | NV_ATOMIC(drm, "%s atomic_check\n", plane->name); |
896 | if (asyw->state.crtc) { | |
839ca903 | 897 | asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); |
973f10c2 BS |
898 | if (IS_ERR(asyh)) |
899 | return PTR_ERR(asyh); | |
900 | asym = drm_atomic_crtc_needs_modeset(&asyh->state); | |
901 | asyv = asyh->state.active; | |
902 | } | |
903 | ||
904 | if (armw->state.crtc) { | |
839ca903 | 905 | harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); |
973f10c2 BS |
906 | if (IS_ERR(harm)) |
907 | return PTR_ERR(harm); | |
839ca903 | 908 | varm = harm->state.crtc->state->active; |
973f10c2 BS |
909 | } |
910 | ||
911 | if (asyv) { | |
912 | asyw->point.x = asyw->state.crtc_x; | |
913 | asyw->point.y = asyw->state.crtc_y; | |
914 | if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) | |
915 | asyw->set.point = true; | |
916 | ||
36601c2b BS |
917 | ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh); |
918 | if (ret) | |
919 | return ret; | |
973f10c2 BS |
920 | } else |
921 | if (varm) { | |
922 | nv50_wndw_atomic_check_release(wndw, asyw, harm); | |
923 | } else { | |
924 | return 0; | |
925 | } | |
926 | ||
927 | if (!asyv || asym) { | |
928 | asyw->clr.ntfy = armw->ntfy.handle != 0; | |
929 | asyw->clr.sema = armw->sema.handle != 0; | |
930 | if (wndw->func->image_clr) | |
931 | asyw->clr.image = armw->image.handle != 0; | |
932 | asyw->set.lut = wndw->func->lut && asyv; | |
933 | } | |
934 | ||
973f10c2 BS |
935 | return 0; |
936 | } | |
937 | ||
839ca903 BS |
938 | static void |
939 | nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) | |
940 | { | |
941 | struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb); | |
942 | struct nouveau_drm *drm = nouveau_drm(plane->dev); | |
943 | ||
944 | NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); | |
945 | if (!old_state->fb) | |
946 | return; | |
947 | ||
948 | nouveau_bo_unpin(fb->nvbo); | |
949 | } | |
950 | ||
951 | static int | |
952 | nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) | |
953 | { | |
954 | struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb); | |
955 | struct nouveau_drm *drm = nouveau_drm(plane->dev); | |
956 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
957 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); | |
958 | struct nv50_head_atom *asyh; | |
959 | struct nv50_dmac_ctxdma *ctxdma; | |
839ca903 BS |
960 | int ret; |
961 | ||
962 | NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb); | |
963 | if (!asyw->state.fb) | |
964 | return 0; | |
839ca903 BS |
965 | |
966 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true); | |
967 | if (ret) | |
968 | return ret; | |
969 | ||
f00f0e21 | 970 | ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb); |
839ca903 BS |
971 | if (IS_ERR(ctxdma)) { |
972 | nouveau_bo_unpin(fb->nvbo); | |
973 | return PTR_ERR(ctxdma); | |
974 | } | |
975 | ||
976 | asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv); | |
977 | asyw->image.handle = ctxdma->object.handle; | |
978 | asyw->image.offset = fb->nvbo->bo.offset; | |
979 | ||
980 | if (wndw->func->prepare) { | |
981 | asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); | |
982 | if (IS_ERR(asyh)) | |
983 | return PTR_ERR(asyh); | |
984 | ||
985 | wndw->func->prepare(wndw, asyh, asyw); | |
986 | } | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static const struct drm_plane_helper_funcs | |
992 | nv50_wndw_helper = { | |
993 | .prepare_fb = nv50_wndw_prepare_fb, | |
994 | .cleanup_fb = nv50_wndw_cleanup_fb, | |
995 | .atomic_check = nv50_wndw_atomic_check, | |
996 | }; | |
997 | ||
973f10c2 BS |
998 | static void |
999 | nv50_wndw_atomic_destroy_state(struct drm_plane *plane, | |
1000 | struct drm_plane_state *state) | |
1001 | { | |
1002 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); | |
1003 | __drm_atomic_helper_plane_destroy_state(&asyw->state); | |
973f10c2 BS |
1004 | kfree(asyw); |
1005 | } | |
1006 | ||
1007 | static struct drm_plane_state * | |
1008 | nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) | |
1009 | { | |
1010 | struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); | |
1011 | struct nv50_wndw_atom *asyw; | |
1012 | if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) | |
1013 | return NULL; | |
1014 | __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); | |
973f10c2 BS |
1015 | asyw->interval = 1; |
1016 | asyw->sema = armw->sema; | |
1017 | asyw->ntfy = armw->ntfy; | |
1018 | asyw->image = armw->image; | |
1019 | asyw->point = armw->point; | |
1020 | asyw->lut = armw->lut; | |
1021 | asyw->clr.mask = 0; | |
1022 | asyw->set.mask = 0; | |
1023 | return &asyw->state; | |
1024 | } | |
1025 | ||
1026 | static void | |
1027 | nv50_wndw_reset(struct drm_plane *plane) | |
1028 | { | |
1029 | struct nv50_wndw_atom *asyw; | |
1030 | ||
1031 | if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) | |
1032 | return; | |
1033 | ||
1034 | if (plane->state) | |
1035 | plane->funcs->atomic_destroy_state(plane, plane->state); | |
1036 | plane->state = &asyw->state; | |
1037 | plane->state->plane = plane; | |
c2c446ad | 1038 | plane->state->rotation = DRM_MODE_ROTATE_0; |
973f10c2 BS |
1039 | } |
1040 | ||
1041 | static void | |
1042 | nv50_wndw_destroy(struct drm_plane *plane) | |
1043 | { | |
1044 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
1045 | void *data; | |
1046 | nvif_notify_fini(&wndw->notify); | |
1047 | data = wndw->func->dtor(wndw); | |
1048 | drm_plane_cleanup(&wndw->plane); | |
1049 | kfree(data); | |
1050 | } | |
1051 | ||
1052 | static const struct drm_plane_funcs | |
1053 | nv50_wndw = { | |
839ca903 BS |
1054 | .update_plane = drm_atomic_helper_update_plane, |
1055 | .disable_plane = drm_atomic_helper_disable_plane, | |
973f10c2 BS |
1056 | .destroy = nv50_wndw_destroy, |
1057 | .reset = nv50_wndw_reset, | |
973f10c2 BS |
1058 | .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, |
1059 | .atomic_destroy_state = nv50_wndw_atomic_destroy_state, | |
1060 | }; | |
1061 | ||
1062 | static void | |
1063 | nv50_wndw_fini(struct nv50_wndw *wndw) | |
1064 | { | |
1065 | nvif_notify_put(&wndw->notify); | |
1066 | } | |
1067 | ||
1068 | static void | |
1069 | nv50_wndw_init(struct nv50_wndw *wndw) | |
1070 | { | |
1071 | nvif_notify_get(&wndw->notify); | |
1072 | } | |
1073 | ||
1074 | static int | |
1075 | nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev, | |
1076 | enum drm_plane_type type, const char *name, int index, | |
1077 | struct nv50_dmac *dmac, const u32 *format, int nformat, | |
1078 | struct nv50_wndw *wndw) | |
1079 | { | |
1080 | int ret; | |
1081 | ||
1082 | wndw->func = func; | |
1083 | wndw->dmac = dmac; | |
1084 | ||
e6fc3b68 BW |
1085 | ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, |
1086 | format, nformat, NULL, | |
1087 | type, "%s-%d", name, index); | |
973f10c2 BS |
1088 | if (ret) |
1089 | return ret; | |
1090 | ||
839ca903 | 1091 | drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); |
973f10c2 BS |
1092 | return 0; |
1093 | } | |
1094 | ||
22e927d2 BS |
1095 | /****************************************************************************** |
1096 | * Cursor plane | |
1097 | *****************************************************************************/ | |
1098 | #define nv50_curs(p) container_of((p), struct nv50_curs, wndw) | |
1099 | ||
1100 | struct nv50_curs { | |
1101 | struct nv50_wndw wndw; | |
1102 | struct nvif_object chan; | |
1103 | }; | |
1104 | ||
1105 | static u32 | |
1106 | nv50_curs_update(struct nv50_wndw *wndw, u32 interlock) | |
1107 | { | |
1108 | struct nv50_curs *curs = nv50_curs(wndw); | |
1109 | nvif_wr32(&curs->chan, 0x0080, 0x00000000); | |
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | static void | |
1114 | nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1115 | { | |
1116 | struct nv50_curs *curs = nv50_curs(wndw); | |
1117 | nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x); | |
1118 | } | |
1119 | ||
1120 | static void | |
1121 | nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh, | |
1122 | struct nv50_wndw_atom *asyw) | |
1123 | { | |
e6db9579 BS |
1124 | u32 handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle; |
1125 | u32 offset = asyw->image.offset; | |
1126 | if (asyh->curs.handle != handle || asyh->curs.offset != offset) { | |
1127 | asyh->curs.handle = handle; | |
1128 | asyh->curs.offset = offset; | |
1129 | asyh->set.curs = asyh->curs.visible; | |
1130 | } | |
22e927d2 BS |
1131 | } |
1132 | ||
1133 | static void | |
1134 | nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1135 | struct nv50_head_atom *asyh) | |
1136 | { | |
1137 | asyh->curs.visible = false; | |
1138 | } | |
1139 | ||
1140 | static int | |
1141 | nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1142 | struct nv50_head_atom *asyh) | |
1143 | { | |
1144 | int ret; | |
1145 | ||
1146 | ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip, | |
1147 | DRM_PLANE_HELPER_NO_SCALING, | |
1148 | DRM_PLANE_HELPER_NO_SCALING, | |
1149 | true, true); | |
1150 | asyh->curs.visible = asyw->state.visible; | |
1151 | if (ret || !asyh->curs.visible) | |
1152 | return ret; | |
1153 | ||
1154 | switch (asyw->state.fb->width) { | |
1155 | case 32: asyh->curs.layout = 0; break; | |
1156 | case 64: asyh->curs.layout = 1; break; | |
1157 | default: | |
1158 | return -EINVAL; | |
1159 | } | |
1160 | ||
1161 | if (asyw->state.fb->width != asyw->state.fb->height) | |
1162 | return -EINVAL; | |
1163 | ||
438b74a5 | 1164 | switch (asyw->state.fb->format->format) { |
22e927d2 BS |
1165 | case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break; |
1166 | default: | |
1167 | WARN_ON(1); | |
1168 | return -EINVAL; | |
1169 | } | |
1170 | ||
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | static void * | |
1175 | nv50_curs_dtor(struct nv50_wndw *wndw) | |
1176 | { | |
1177 | struct nv50_curs *curs = nv50_curs(wndw); | |
1178 | nvif_object_fini(&curs->chan); | |
1179 | return curs; | |
1180 | } | |
1181 | ||
1182 | static const u32 | |
1183 | nv50_curs_format[] = { | |
1184 | DRM_FORMAT_ARGB8888, | |
1185 | }; | |
1186 | ||
1187 | static const struct nv50_wndw_func | |
1188 | nv50_curs = { | |
1189 | .dtor = nv50_curs_dtor, | |
1190 | .acquire = nv50_curs_acquire, | |
1191 | .release = nv50_curs_release, | |
1192 | .prepare = nv50_curs_prepare, | |
1193 | .point = nv50_curs_point, | |
1194 | .update = nv50_curs_update, | |
1195 | }; | |
1196 | ||
1197 | static int | |
1198 | nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head, | |
1199 | struct nv50_curs **pcurs) | |
1200 | { | |
1201 | static const struct nvif_mclass curses[] = { | |
1202 | { GK104_DISP_CURSOR, 0 }, | |
1203 | { GF110_DISP_CURSOR, 0 }, | |
1204 | { GT214_DISP_CURSOR, 0 }, | |
1205 | { G82_DISP_CURSOR, 0 }, | |
1206 | { NV50_DISP_CURSOR, 0 }, | |
1207 | {} | |
1208 | }; | |
1209 | struct nv50_disp_cursor_v0 args = { | |
1210 | .head = head->base.index, | |
1211 | }; | |
1212 | struct nv50_disp *disp = nv50_disp(drm->dev); | |
1213 | struct nv50_curs *curs; | |
1214 | int cid, ret; | |
1215 | ||
1216 | cid = nvif_mclass(disp->disp, curses); | |
1217 | if (cid < 0) { | |
1218 | NV_ERROR(drm, "No supported cursor immediate class\n"); | |
1219 | return cid; | |
1220 | } | |
1221 | ||
1222 | if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL))) | |
1223 | return -ENOMEM; | |
1224 | ||
1225 | ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR, | |
1226 | "curs", head->base.index, &disp->mast.base, | |
1227 | nv50_curs_format, ARRAY_SIZE(nv50_curs_format), | |
1228 | &curs->wndw); | |
1229 | if (ret) { | |
1230 | kfree(curs); | |
1231 | return ret; | |
1232 | } | |
1233 | ||
1234 | ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args, | |
1235 | sizeof(args), &curs->chan); | |
1236 | if (ret) { | |
1237 | NV_ERROR(drm, "curs%04x allocation failed: %d\n", | |
1238 | curses[cid].oclass, ret); | |
1239 | return ret; | |
1240 | } | |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
973f10c2 BS |
1245 | /****************************************************************************** |
1246 | * Primary plane | |
1247 | *****************************************************************************/ | |
1248 | #define nv50_base(p) container_of((p), struct nv50_base, wndw) | |
1249 | ||
1250 | struct nv50_base { | |
1251 | struct nv50_wndw wndw; | |
1252 | struct nv50_sync chan; | |
1253 | int id; | |
1254 | }; | |
1255 | ||
1256 | static int | |
1257 | nv50_base_notify(struct nvif_notify *notify) | |
1258 | { | |
1259 | return NVIF_NOTIFY_KEEP; | |
1260 | } | |
1261 | ||
1262 | static void | |
1263 | nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1264 | { | |
1265 | struct nv50_base *base = nv50_base(wndw); | |
1266 | u32 *push; | |
1267 | if ((push = evo_wait(&base->chan, 2))) { | |
1268 | evo_mthd(push, 0x00e0, 1); | |
1269 | evo_data(push, asyw->lut.enable << 30); | |
1270 | evo_kick(push, &base->chan); | |
1271 | } | |
1272 | } | |
1273 | ||
1274 | static void | |
1275 | nv50_base_image_clr(struct nv50_wndw *wndw) | |
1276 | { | |
1277 | struct nv50_base *base = nv50_base(wndw); | |
1278 | u32 *push; | |
1279 | if ((push = evo_wait(&base->chan, 4))) { | |
1280 | evo_mthd(push, 0x0084, 1); | |
1281 | evo_data(push, 0x00000000); | |
1282 | evo_mthd(push, 0x00c0, 1); | |
1283 | evo_data(push, 0x00000000); | |
1284 | evo_kick(push, &base->chan); | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | static void | |
1289 | nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1290 | { | |
1291 | struct nv50_base *base = nv50_base(wndw); | |
1292 | const s32 oclass = base->chan.base.base.user.oclass; | |
1293 | u32 *push; | |
1294 | if ((push = evo_wait(&base->chan, 10))) { | |
1295 | evo_mthd(push, 0x0084, 1); | |
1296 | evo_data(push, (asyw->image.mode << 8) | | |
1297 | (asyw->image.interval << 4)); | |
1298 | evo_mthd(push, 0x00c0, 1); | |
1299 | evo_data(push, asyw->image.handle); | |
1300 | if (oclass < G82_DISP_BASE_CHANNEL_DMA) { | |
1301 | evo_mthd(push, 0x0800, 5); | |
1302 | evo_data(push, asyw->image.offset >> 8); | |
1303 | evo_data(push, 0x00000000); | |
1304 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); | |
1305 | evo_data(push, (asyw->image.layout << 20) | | |
1306 | asyw->image.pitch | | |
1307 | asyw->image.block); | |
1308 | evo_data(push, (asyw->image.kind << 16) | | |
1309 | (asyw->image.format << 8)); | |
1310 | } else | |
1311 | if (oclass < GF110_DISP_BASE_CHANNEL_DMA) { | |
1312 | evo_mthd(push, 0x0800, 5); | |
1313 | evo_data(push, asyw->image.offset >> 8); | |
1314 | evo_data(push, 0x00000000); | |
1315 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); | |
1316 | evo_data(push, (asyw->image.layout << 20) | | |
1317 | asyw->image.pitch | | |
1318 | asyw->image.block); | |
1319 | evo_data(push, asyw->image.format << 8); | |
1320 | } else { | |
1321 | evo_mthd(push, 0x0400, 5); | |
1322 | evo_data(push, asyw->image.offset >> 8); | |
1323 | evo_data(push, 0x00000000); | |
1324 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); | |
1325 | evo_data(push, (asyw->image.layout << 24) | | |
1326 | asyw->image.pitch | | |
1327 | asyw->image.block); | |
1328 | evo_data(push, asyw->image.format << 8); | |
1329 | } | |
1330 | evo_kick(push, &base->chan); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static void | |
1335 | nv50_base_ntfy_clr(struct nv50_wndw *wndw) | |
1336 | { | |
1337 | struct nv50_base *base = nv50_base(wndw); | |
1338 | u32 *push; | |
1339 | if ((push = evo_wait(&base->chan, 2))) { | |
1340 | evo_mthd(push, 0x00a4, 1); | |
1341 | evo_data(push, 0x00000000); | |
1342 | evo_kick(push, &base->chan); | |
1343 | } | |
1344 | } | |
1345 | ||
1346 | static void | |
1347 | nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1348 | { | |
1349 | struct nv50_base *base = nv50_base(wndw); | |
1350 | u32 *push; | |
1351 | if ((push = evo_wait(&base->chan, 3))) { | |
1352 | evo_mthd(push, 0x00a0, 2); | |
1353 | evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset); | |
1354 | evo_data(push, asyw->ntfy.handle); | |
1355 | evo_kick(push, &base->chan); | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | static void | |
1360 | nv50_base_sema_clr(struct nv50_wndw *wndw) | |
1361 | { | |
1362 | struct nv50_base *base = nv50_base(wndw); | |
1363 | u32 *push; | |
1364 | if ((push = evo_wait(&base->chan, 2))) { | |
1365 | evo_mthd(push, 0x0094, 1); | |
1366 | evo_data(push, 0x00000000); | |
1367 | evo_kick(push, &base->chan); | |
1368 | } | |
1369 | } | |
1370 | ||
1371 | static void | |
1372 | nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1373 | { | |
1374 | struct nv50_base *base = nv50_base(wndw); | |
1375 | u32 *push; | |
1376 | if ((push = evo_wait(&base->chan, 5))) { | |
1377 | evo_mthd(push, 0x0088, 4); | |
1378 | evo_data(push, asyw->sema.offset); | |
1379 | evo_data(push, asyw->sema.acquire); | |
1380 | evo_data(push, asyw->sema.release); | |
1381 | evo_data(push, asyw->sema.handle); | |
1382 | evo_kick(push, &base->chan); | |
1383 | } | |
1384 | } | |
1385 | ||
1386 | static u32 | |
1387 | nv50_base_update(struct nv50_wndw *wndw, u32 interlock) | |
1388 | { | |
1389 | struct nv50_base *base = nv50_base(wndw); | |
1390 | u32 *push; | |
1391 | ||
1392 | if (!(push = evo_wait(&base->chan, 2))) | |
1393 | return 0; | |
1394 | evo_mthd(push, 0x0080, 1); | |
1395 | evo_data(push, interlock); | |
1396 | evo_kick(push, &base->chan); | |
1397 | ||
1398 | if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) | |
1399 | return interlock ? 2 << (base->id * 8) : 0; | |
1400 | return interlock ? 2 << (base->id * 4) : 0; | |
1401 | } | |
1402 | ||
1403 | static int | |
1404 | nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1405 | { | |
1406 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); | |
1407 | struct nv50_disp *disp = nv50_disp(wndw->plane.dev); | |
1167c6bc | 1408 | if (nvif_msec(&drm->client.device, 2000ULL, |
973f10c2 BS |
1409 | u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4); |
1410 | if ((data & 0xc0000000) == 0x40000000) | |
1411 | break; | |
1412 | usleep_range(1, 2); | |
1413 | ) < 0) | |
1414 | return -ETIMEDOUT; | |
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static void | |
1419 | nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1420 | struct nv50_head_atom *asyh) | |
1421 | { | |
1422 | asyh->base.cpp = 0; | |
1423 | } | |
1424 | ||
1425 | static int | |
1426 | nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1427 | struct nv50_head_atom *asyh) | |
1428 | { | |
9857ecbe | 1429 | const struct drm_framebuffer *fb = asyw->state.fb; |
973f10c2 BS |
1430 | int ret; |
1431 | ||
9857ecbe | 1432 | if (!fb->format->depth) |
973f10c2 BS |
1433 | return -EINVAL; |
1434 | ||
1435 | ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip, | |
1436 | DRM_PLANE_HELPER_NO_SCALING, | |
1437 | DRM_PLANE_HELPER_NO_SCALING, | |
1438 | false, true); | |
1439 | if (ret) | |
1440 | return ret; | |
1441 | ||
9857ecbe VS |
1442 | asyh->base.depth = fb->format->depth; |
1443 | asyh->base.cpp = fb->format->cpp[0]; | |
973f10c2 BS |
1444 | asyh->base.x = asyw->state.src.x1 >> 16; |
1445 | asyh->base.y = asyw->state.src.y1 >> 16; | |
1446 | asyh->base.w = asyw->state.fb->width; | |
1447 | asyh->base.h = asyw->state.fb->height; | |
1448 | ||
438b74a5 | 1449 | switch (fb->format->format) { |
973f10c2 BS |
1450 | case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; |
1451 | case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; | |
1452 | case DRM_FORMAT_XRGB1555 : | |
1453 | case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; | |
1454 | case DRM_FORMAT_XRGB8888 : | |
1455 | case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; | |
1456 | case DRM_FORMAT_XBGR2101010: | |
1457 | case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break; | |
1458 | case DRM_FORMAT_XBGR8888 : | |
1459 | case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; | |
1460 | default: | |
1461 | WARN_ON(1); | |
1462 | return -EINVAL; | |
1463 | } | |
1464 | ||
1465 | asyw->lut.enable = 1; | |
1466 | asyw->set.image = true; | |
1467 | return 0; | |
1468 | } | |
1469 | ||
1470 | static void * | |
1471 | nv50_base_dtor(struct nv50_wndw *wndw) | |
1472 | { | |
1473 | struct nv50_disp *disp = nv50_disp(wndw->plane.dev); | |
1474 | struct nv50_base *base = nv50_base(wndw); | |
1475 | nv50_dmac_destroy(&base->chan.base, disp->disp); | |
1476 | return base; | |
1477 | } | |
1478 | ||
1479 | static const u32 | |
1480 | nv50_base_format[] = { | |
1481 | DRM_FORMAT_C8, | |
1482 | DRM_FORMAT_RGB565, | |
1483 | DRM_FORMAT_XRGB1555, | |
1484 | DRM_FORMAT_ARGB1555, | |
1485 | DRM_FORMAT_XRGB8888, | |
1486 | DRM_FORMAT_ARGB8888, | |
1487 | DRM_FORMAT_XBGR2101010, | |
1488 | DRM_FORMAT_ABGR2101010, | |
1489 | DRM_FORMAT_XBGR8888, | |
1490 | DRM_FORMAT_ABGR8888, | |
1491 | }; | |
1492 | ||
1493 | static const struct nv50_wndw_func | |
1494 | nv50_base = { | |
1495 | .dtor = nv50_base_dtor, | |
1496 | .acquire = nv50_base_acquire, | |
1497 | .release = nv50_base_release, | |
1498 | .sema_set = nv50_base_sema_set, | |
1499 | .sema_clr = nv50_base_sema_clr, | |
1500 | .ntfy_set = nv50_base_ntfy_set, | |
1501 | .ntfy_clr = nv50_base_ntfy_clr, | |
1502 | .ntfy_wait_begun = nv50_base_ntfy_wait_begun, | |
1503 | .image_set = nv50_base_image_set, | |
1504 | .image_clr = nv50_base_image_clr, | |
1505 | .lut = nv50_base_lut, | |
1506 | .update = nv50_base_update, | |
1507 | }; | |
1508 | ||
1509 | static int | |
1510 | nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head, | |
1511 | struct nv50_base **pbase) | |
1512 | { | |
1513 | struct nv50_disp *disp = nv50_disp(drm->dev); | |
1514 | struct nv50_base *base; | |
1515 | int ret; | |
1516 | ||
1517 | if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL))) | |
1518 | return -ENOMEM; | |
1519 | base->id = head->base.index; | |
1520 | base->wndw.ntfy = EVO_FLIP_NTFY0(base->id); | |
1521 | base->wndw.sema = EVO_FLIP_SEM0(base->id); | |
1522 | base->wndw.data = 0x00000000; | |
1523 | ||
1524 | ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY, | |
1525 | "base", base->id, &base->chan.base, | |
1526 | nv50_base_format, ARRAY_SIZE(nv50_base_format), | |
1527 | &base->wndw); | |
1528 | if (ret) { | |
1529 | kfree(base); | |
1530 | return ret; | |
1531 | } | |
1532 | ||
1167c6bc | 1533 | ret = nv50_base_create(&drm->client.device, disp->disp, base->id, |
973f10c2 BS |
1534 | disp->sync->bo.offset, &base->chan); |
1535 | if (ret) | |
1536 | return ret; | |
1537 | ||
1538 | return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify, | |
1539 | false, | |
1540 | NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT, | |
1541 | &(struct nvif_notify_uevent_req) {}, | |
1542 | sizeof(struct nvif_notify_uevent_req), | |
1543 | sizeof(struct nvif_notify_uevent_rep), | |
1544 | &base->wndw.notify); | |
1545 | } | |
1546 | ||
3dbd036b BS |
1547 | /****************************************************************************** |
1548 | * Head | |
1549 | *****************************************************************************/ | |
7e08d67c BS |
1550 | static void |
1551 | nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1552 | { | |
1553 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1554 | u32 *push; | |
1555 | if ((push = evo_wait(core, 2))) { | |
1556 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1557 | evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1); | |
1558 | else | |
1559 | evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1); | |
1560 | evo_data(push, (asyh->procamp.sat.sin << 20) | | |
1561 | (asyh->procamp.sat.cos << 8)); | |
1562 | evo_kick(push, core); | |
1563 | } | |
1564 | } | |
1565 | ||
7e91833d BS |
1566 | static void |
1567 | nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1568 | { | |
1569 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1570 | u32 *push; | |
1571 | if ((push = evo_wait(core, 2))) { | |
1572 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1573 | evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1); | |
1574 | else | |
1575 | if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA) | |
1576 | evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1); | |
1577 | else | |
1578 | evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1); | |
1579 | evo_data(push, (asyh->dither.mode << 3) | | |
1580 | (asyh->dither.bits << 1) | | |
1581 | asyh->dither.enable); | |
1582 | evo_kick(push, core); | |
1583 | } | |
1584 | } | |
1585 | ||
6bbab3b6 BS |
1586 | static void |
1587 | nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1588 | { | |
1589 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1590 | u32 bounds = 0; | |
1591 | u32 *push; | |
1592 | ||
1593 | if (asyh->base.cpp) { | |
1594 | switch (asyh->base.cpp) { | |
1595 | case 8: bounds |= 0x00000500; break; | |
1596 | case 4: bounds |= 0x00000300; break; | |
1597 | case 2: bounds |= 0x00000100; break; | |
1598 | default: | |
1599 | WARN_ON(1); | |
1600 | break; | |
1601 | } | |
1602 | bounds |= 0x00000001; | |
1603 | } | |
1604 | ||
1605 | if ((push = evo_wait(core, 2))) { | |
1606 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1607 | evo_mthd(push, 0x0904 + head->base.index * 0x400, 1); | |
1608 | else | |
1609 | evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1); | |
1610 | evo_data(push, bounds); | |
1611 | evo_kick(push, core); | |
1612 | } | |
1613 | } | |
1614 | ||
1615 | static void | |
1616 | nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1617 | { | |
1618 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1619 | u32 bounds = 0; | |
1620 | u32 *push; | |
1621 | ||
1622 | if (asyh->base.cpp) { | |
1623 | switch (asyh->base.cpp) { | |
1624 | case 8: bounds |= 0x00000500; break; | |
1625 | case 4: bounds |= 0x00000300; break; | |
1626 | case 2: bounds |= 0x00000100; break; | |
1627 | case 1: bounds |= 0x00000000; break; | |
1628 | default: | |
1629 | WARN_ON(1); | |
1630 | break; | |
1631 | } | |
1632 | bounds |= 0x00000001; | |
1633 | } | |
1634 | ||
1635 | if ((push = evo_wait(core, 2))) { | |
1636 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1637 | evo_mthd(push, 0x0900 + head->base.index * 0x400, 1); | |
1638 | else | |
1639 | evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1); | |
1640 | evo_data(push, bounds); | |
1641 | evo_kick(push, core); | |
1642 | } | |
1643 | } | |
1644 | ||
ea8ee390 BS |
1645 | static void |
1646 | nv50_head_curs_clr(struct nv50_head *head) | |
1647 | { | |
1648 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1649 | u32 *push; | |
1650 | if ((push = evo_wait(core, 4))) { | |
1651 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1652 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); | |
1653 | evo_data(push, 0x05000000); | |
1654 | } else | |
1655 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1656 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); | |
1657 | evo_data(push, 0x05000000); | |
1658 | evo_mthd(push, 0x089c + head->base.index * 0x400, 1); | |
1659 | evo_data(push, 0x00000000); | |
1660 | } else { | |
1661 | evo_mthd(push, 0x0480 + head->base.index * 0x300, 1); | |
1662 | evo_data(push, 0x05000000); | |
1663 | evo_mthd(push, 0x048c + head->base.index * 0x300, 1); | |
1664 | evo_data(push, 0x00000000); | |
1665 | } | |
1666 | evo_kick(push, core); | |
1667 | } | |
1668 | } | |
1669 | ||
1670 | static void | |
1671 | nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1672 | { | |
1673 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1674 | u32 *push; | |
1675 | if ((push = evo_wait(core, 5))) { | |
1676 | if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) { | |
1677 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); | |
1678 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | | |
1679 | (asyh->curs.format << 24)); | |
1680 | evo_data(push, asyh->curs.offset >> 8); | |
1681 | } else | |
1682 | if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) { | |
1683 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); | |
1684 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | | |
1685 | (asyh->curs.format << 24)); | |
1686 | evo_data(push, asyh->curs.offset >> 8); | |
1687 | evo_mthd(push, 0x089c + head->base.index * 0x400, 1); | |
1688 | evo_data(push, asyh->curs.handle); | |
1689 | } else { | |
1690 | evo_mthd(push, 0x0480 + head->base.index * 0x300, 2); | |
1691 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | | |
1692 | (asyh->curs.format << 24)); | |
1693 | evo_data(push, asyh->curs.offset >> 8); | |
1694 | evo_mthd(push, 0x048c + head->base.index * 0x300, 1); | |
1695 | evo_data(push, asyh->curs.handle); | |
1696 | } | |
1697 | evo_kick(push, core); | |
1698 | } | |
1699 | } | |
1700 | ||
ad633619 BS |
1701 | static void |
1702 | nv50_head_core_clr(struct nv50_head *head) | |
1703 | { | |
1704 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1705 | u32 *push; | |
1706 | if ((push = evo_wait(core, 2))) { | |
1707 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1708 | evo_mthd(push, 0x0874 + head->base.index * 0x400, 1); | |
1709 | else | |
1710 | evo_mthd(push, 0x0474 + head->base.index * 0x300, 1); | |
1711 | evo_data(push, 0x00000000); | |
1712 | evo_kick(push, core); | |
1713 | } | |
1714 | } | |
1715 | ||
1716 | static void | |
1717 | nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1718 | { | |
1719 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1720 | u32 *push; | |
1721 | if ((push = evo_wait(core, 9))) { | |
1722 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1723 | evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); | |
1724 | evo_data(push, asyh->core.offset >> 8); | |
1725 | evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); | |
1726 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); | |
1727 | evo_data(push, asyh->core.layout << 20 | | |
1728 | (asyh->core.pitch >> 8) << 8 | | |
1729 | asyh->core.block); | |
1730 | evo_data(push, asyh->core.kind << 16 | | |
1731 | asyh->core.format << 8); | |
1732 | evo_data(push, asyh->core.handle); | |
1733 | evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); | |
1734 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); | |
19d53d01 BS |
1735 | /* EVO will complain with INVALID_STATE if we have an |
1736 | * active cursor and (re)specify HeadSetContextDmaIso | |
1737 | * without also updating HeadSetOffsetCursor. | |
1738 | */ | |
1739 | asyh->set.curs = asyh->curs.visible; | |
ad633619 BS |
1740 | } else |
1741 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1742 | evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); | |
1743 | evo_data(push, asyh->core.offset >> 8); | |
1744 | evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); | |
1745 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); | |
1746 | evo_data(push, asyh->core.layout << 20 | | |
1747 | (asyh->core.pitch >> 8) << 8 | | |
1748 | asyh->core.block); | |
1749 | evo_data(push, asyh->core.format << 8); | |
1750 | evo_data(push, asyh->core.handle); | |
1751 | evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); | |
1752 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); | |
1753 | } else { | |
1754 | evo_mthd(push, 0x0460 + head->base.index * 0x300, 1); | |
1755 | evo_data(push, asyh->core.offset >> 8); | |
1756 | evo_mthd(push, 0x0468 + head->base.index * 0x300, 4); | |
1757 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); | |
1758 | evo_data(push, asyh->core.layout << 24 | | |
1759 | (asyh->core.pitch >> 8) << 8 | | |
1760 | asyh->core.block); | |
1761 | evo_data(push, asyh->core.format << 8); | |
1762 | evo_data(push, asyh->core.handle); | |
1763 | evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1); | |
1764 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); | |
1765 | } | |
1766 | evo_kick(push, core); | |
1767 | } | |
1768 | } | |
1769 | ||
a7ae1561 BS |
1770 | static void |
1771 | nv50_head_lut_clr(struct nv50_head *head) | |
1772 | { | |
1773 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1774 | u32 *push; | |
1775 | if ((push = evo_wait(core, 4))) { | |
1776 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1777 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); | |
1778 | evo_data(push, 0x40000000); | |
1779 | } else | |
1780 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1781 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); | |
1782 | evo_data(push, 0x40000000); | |
1783 | evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); | |
1784 | evo_data(push, 0x00000000); | |
1785 | } else { | |
1786 | evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1); | |
1787 | evo_data(push, 0x03000000); | |
1788 | evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); | |
1789 | evo_data(push, 0x00000000); | |
1790 | } | |
1791 | evo_kick(push, core); | |
1792 | } | |
1793 | } | |
1794 | ||
1795 | static void | |
1796 | nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1797 | { | |
1798 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1799 | u32 *push; | |
1800 | if ((push = evo_wait(core, 7))) { | |
1801 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1802 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); | |
1803 | evo_data(push, 0xc0000000); | |
1804 | evo_data(push, asyh->lut.offset >> 8); | |
1805 | } else | |
1806 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1807 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); | |
1808 | evo_data(push, 0xc0000000); | |
1809 | evo_data(push, asyh->lut.offset >> 8); | |
1810 | evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); | |
1811 | evo_data(push, asyh->lut.handle); | |
1812 | } else { | |
1813 | evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4); | |
1814 | evo_data(push, 0x83000000); | |
1815 | evo_data(push, asyh->lut.offset >> 8); | |
1816 | evo_data(push, 0x00000000); | |
1817 | evo_data(push, 0x00000000); | |
1818 | evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); | |
1819 | evo_data(push, asyh->lut.handle); | |
1820 | } | |
1821 | evo_kick(push, core); | |
1822 | } | |
1823 | } | |
1824 | ||
3dbd036b BS |
1825 | static void |
1826 | nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1827 | { | |
1828 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1829 | struct nv50_head_mode *m = &asyh->mode; | |
1830 | u32 *push; | |
1831 | if ((push = evo_wait(core, 14))) { | |
1832 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1833 | evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2); | |
1834 | evo_data(push, 0x00800000 | m->clock); | |
1835 | evo_data(push, m->interlace ? 0x00000002 : 0x00000000); | |
06ab282f | 1836 | evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7); |
3dbd036b BS |
1837 | evo_data(push, 0x00000000); |
1838 | evo_data(push, (m->v.active << 16) | m->h.active ); | |
1839 | evo_data(push, (m->v.synce << 16) | m->h.synce ); | |
1840 | evo_data(push, (m->v.blanke << 16) | m->h.blanke ); | |
1841 | evo_data(push, (m->v.blanks << 16) | m->h.blanks ); | |
1842 | evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); | |
06ab282f | 1843 | evo_data(push, asyh->mode.v.blankus); |
3dbd036b BS |
1844 | evo_mthd(push, 0x082c + (head->base.index * 0x400), 1); |
1845 | evo_data(push, 0x00000000); | |
1846 | } else { | |
1847 | evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6); | |
1848 | evo_data(push, 0x00000000); | |
1849 | evo_data(push, (m->v.active << 16) | m->h.active ); | |
1850 | evo_data(push, (m->v.synce << 16) | m->h.synce ); | |
1851 | evo_data(push, (m->v.blanke << 16) | m->h.blanke ); | |
1852 | evo_data(push, (m->v.blanks << 16) | m->h.blanks ); | |
1853 | evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); | |
1854 | evo_mthd(push, 0x042c + (head->base.index * 0x300), 2); | |
1855 | evo_data(push, 0x00000000); /* ??? */ | |
1856 | evo_data(push, 0xffffff00); | |
1857 | evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3); | |
1858 | evo_data(push, m->clock * 1000); | |
1859 | evo_data(push, 0x00200000); /* ??? */ | |
1860 | evo_data(push, m->clock * 1000); | |
1861 | } | |
1862 | evo_kick(push, core); | |
1863 | } | |
1864 | } | |
1865 | ||
c4e6812c BS |
1866 | static void |
1867 | nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1868 | { | |
1869 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1870 | u32 *push; | |
1871 | if ((push = evo_wait(core, 10))) { | |
1872 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1873 | evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1); | |
1874 | evo_data(push, 0x00000000); | |
1875 | evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1); | |
1876 | evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); | |
1877 | evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2); | |
1878 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1879 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1880 | } else { | |
1881 | evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1); | |
1882 | evo_data(push, 0x00000000); | |
1883 | evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1); | |
1884 | evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); | |
1885 | evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3); | |
1886 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1887 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1888 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1889 | } | |
1890 | evo_kick(push, core); | |
1891 | } | |
1892 | } | |
1893 | ||
ad633619 BS |
1894 | static void |
1895 | nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y) | |
1896 | { | |
a7ae1561 BS |
1897 | if (asyh->clr.core && (!asyh->set.core || y)) |
1898 | nv50_head_lut_clr(head); | |
ad633619 BS |
1899 | if (asyh->clr.core && (!asyh->set.core || y)) |
1900 | nv50_head_core_clr(head); | |
ea8ee390 BS |
1901 | if (asyh->clr.curs && (!asyh->set.curs || y)) |
1902 | nv50_head_curs_clr(head); | |
ad633619 BS |
1903 | } |
1904 | ||
3dbd036b BS |
1905 | static void |
1906 | nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1907 | { | |
c4e6812c | 1908 | if (asyh->set.view ) nv50_head_view (head, asyh); |
3dbd036b | 1909 | if (asyh->set.mode ) nv50_head_mode (head, asyh); |
a7ae1561 | 1910 | if (asyh->set.core ) nv50_head_lut_set (head, asyh); |
ad633619 | 1911 | if (asyh->set.core ) nv50_head_core_set(head, asyh); |
ea8ee390 | 1912 | if (asyh->set.curs ) nv50_head_curs_set(head, asyh); |
6bbab3b6 BS |
1913 | if (asyh->set.base ) nv50_head_base (head, asyh); |
1914 | if (asyh->set.ovly ) nv50_head_ovly (head, asyh); | |
7e91833d | 1915 | if (asyh->set.dither ) nv50_head_dither (head, asyh); |
7e08d67c BS |
1916 | if (asyh->set.procamp) nv50_head_procamp (head, asyh); |
1917 | } | |
1918 | ||
1919 | static void | |
1920 | nv50_head_atomic_check_procamp(struct nv50_head_atom *armh, | |
1921 | struct nv50_head_atom *asyh, | |
1922 | struct nouveau_conn_atom *asyc) | |
1923 | { | |
1924 | const int vib = asyc->procamp.color_vibrance - 100; | |
1925 | const int hue = asyc->procamp.vibrant_hue - 90; | |
1926 | const int adj = (vib > 0) ? 50 : 0; | |
1927 | asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff; | |
1928 | asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff; | |
1929 | asyh->set.procamp = true; | |
7e91833d BS |
1930 | } |
1931 | ||
1932 | static void | |
1933 | nv50_head_atomic_check_dither(struct nv50_head_atom *armh, | |
1934 | struct nv50_head_atom *asyh, | |
1935 | struct nouveau_conn_atom *asyc) | |
1936 | { | |
1937 | struct drm_connector *connector = asyc->state.connector; | |
1938 | u32 mode = 0x00; | |
1939 | ||
1940 | if (asyc->dither.mode == DITHERING_MODE_AUTO) { | |
1941 | if (asyh->base.depth > connector->display_info.bpc * 3) | |
1942 | mode = DITHERING_MODE_DYNAMIC2X2; | |
1943 | } else { | |
1944 | mode = asyc->dither.mode; | |
1945 | } | |
1946 | ||
1947 | if (asyc->dither.depth == DITHERING_DEPTH_AUTO) { | |
1948 | if (connector->display_info.bpc >= 8) | |
1949 | mode |= DITHERING_DEPTH_8BPC; | |
1950 | } else { | |
1951 | mode |= asyc->dither.depth; | |
1952 | } | |
1953 | ||
1954 | asyh->dither.enable = mode; | |
1955 | asyh->dither.bits = mode >> 1; | |
1956 | asyh->dither.mode = mode >> 3; | |
1957 | asyh->set.dither = true; | |
3dbd036b BS |
1958 | } |
1959 | ||
c4e6812c BS |
1960 | static void |
1961 | nv50_head_atomic_check_view(struct nv50_head_atom *armh, | |
1962 | struct nv50_head_atom *asyh, | |
1963 | struct nouveau_conn_atom *asyc) | |
1964 | { | |
1965 | struct drm_connector *connector = asyc->state.connector; | |
1966 | struct drm_display_mode *omode = &asyh->state.adjusted_mode; | |
1967 | struct drm_display_mode *umode = &asyh->state.mode; | |
1968 | int mode = asyc->scaler.mode; | |
1969 | struct edid *edid; | |
37aa2243 | 1970 | int umode_vdisplay, omode_hdisplay, omode_vdisplay; |
c4e6812c BS |
1971 | |
1972 | if (connector->edid_blob_ptr) | |
1973 | edid = (struct edid *)connector->edid_blob_ptr->data; | |
1974 | else | |
1975 | edid = NULL; | |
1976 | ||
1977 | if (!asyc->scaler.full) { | |
1978 | if (mode == DRM_MODE_SCALE_NONE) | |
1979 | omode = umode; | |
1980 | } else { | |
1981 | /* Non-EDID LVDS/eDP mode. */ | |
1982 | mode = DRM_MODE_SCALE_FULLSCREEN; | |
1983 | } | |
1984 | ||
37aa2243 AB |
1985 | /* For the user-specified mode, we must ignore doublescan and |
1986 | * the like, but honor frame packing. | |
1987 | */ | |
1988 | umode_vdisplay = umode->vdisplay; | |
1989 | if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1990 | umode_vdisplay += umode->vtotal; | |
c4e6812c | 1991 | asyh->view.iW = umode->hdisplay; |
37aa2243 AB |
1992 | asyh->view.iH = umode_vdisplay; |
1993 | /* For the output mode, we can just use the stock helper. */ | |
1994 | drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay); | |
1995 | asyh->view.oW = omode_hdisplay; | |
1996 | asyh->view.oH = omode_vdisplay; | |
c4e6812c BS |
1997 | |
1998 | /* Add overscan compensation if necessary, will keep the aspect | |
1999 | * ratio the same as the backend mode unless overridden by the | |
2000 | * user setting both hborder and vborder properties. | |
2001 | */ | |
2002 | if ((asyc->scaler.underscan.mode == UNDERSCAN_ON || | |
2003 | (asyc->scaler.underscan.mode == UNDERSCAN_AUTO && | |
2004 | drm_detect_hdmi_monitor(edid)))) { | |
2005 | u32 bX = asyc->scaler.underscan.hborder; | |
2006 | u32 bY = asyc->scaler.underscan.vborder; | |
2007 | u32 r = (asyh->view.oH << 19) / asyh->view.oW; | |
2008 | ||
2009 | if (bX) { | |
2010 | asyh->view.oW -= (bX * 2); | |
2011 | if (bY) asyh->view.oH -= (bY * 2); | |
2012 | else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; | |
2013 | } else { | |
2014 | asyh->view.oW -= (asyh->view.oW >> 4) + 32; | |
2015 | if (bY) asyh->view.oH -= (bY * 2); | |
2016 | else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; | |
2017 | } | |
2018 | } | |
2019 | ||
2020 | /* Handle CENTER/ASPECT scaling, taking into account the areas | |
2021 | * removed already for overscan compensation. | |
2022 | */ | |
2023 | switch (mode) { | |
2024 | case DRM_MODE_SCALE_CENTER: | |
2025 | asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW); | |
37aa2243 | 2026 | asyh->view.oH = min((u16)umode_vdisplay, asyh->view.oH); |
c4e6812c BS |
2027 | /* fall-through */ |
2028 | case DRM_MODE_SCALE_ASPECT: | |
2029 | if (asyh->view.oH < asyh->view.oW) { | |
2030 | u32 r = (asyh->view.iW << 19) / asyh->view.iH; | |
2031 | asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; | |
2032 | } else { | |
2033 | u32 r = (asyh->view.iH << 19) / asyh->view.iW; | |
2034 | asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; | |
2035 | } | |
2036 | break; | |
2037 | default: | |
2038 | break; | |
2039 | } | |
2040 | ||
2041 | asyh->set.view = true; | |
2042 | } | |
2043 | ||
3dbd036b BS |
2044 | static void |
2045 | nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) | |
2046 | { | |
2047 | struct drm_display_mode *mode = &asyh->state.adjusted_mode; | |
3dbd036b | 2048 | struct nv50_head_mode *m = &asyh->mode; |
35dd9874 | 2049 | u32 blankus; |
3dbd036b | 2050 | |
37aa2243 | 2051 | drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); |
3dbd036b | 2052 | |
35dd9874 AB |
2053 | /* |
2054 | * DRM modes are defined in terms of a repeating interval | |
2055 | * starting with the active display area. The hardware modes | |
2056 | * are defined in terms of a repeating interval starting one | |
2057 | * unit (pixel or line) into the sync pulse. So, add bias. | |
2058 | */ | |
2059 | ||
2060 | m->h.active = mode->crtc_htotal; | |
2061 | m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1; | |
2062 | m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1; | |
2063 | m->h.blanks = m->h.blanke + mode->crtc_hdisplay; | |
2064 | ||
2065 | m->v.active = mode->crtc_vtotal; | |
2066 | m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1; | |
2067 | m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1; | |
2068 | m->v.blanks = m->v.blanke + mode->crtc_vdisplay; | |
3dbd036b BS |
2069 | |
2070 | /*XXX: Safe underestimate, even "0" works */ | |
35dd9874 | 2071 | blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active; |
aeecfcd7 | 2072 | blankus *= 1000; |
35dd9874 | 2073 | blankus /= mode->crtc_clock; |
aeecfcd7 | 2074 | m->v.blankus = blankus; |
3dbd036b BS |
2075 | |
2076 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
35dd9874 AB |
2077 | m->v.blank2e = m->v.active + m->v.blanke; |
2078 | m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay; | |
3dbd036b BS |
2079 | m->v.active = (m->v.active * 2) + 1; |
2080 | m->interlace = true; | |
2081 | } else { | |
2082 | m->v.blank2e = 0; | |
2083 | m->v.blank2s = 1; | |
2084 | m->interlace = false; | |
2085 | } | |
35dd9874 | 2086 | m->clock = mode->crtc_clock; |
3dbd036b | 2087 | |
3dbd036b BS |
2088 | asyh->set.mode = true; |
2089 | } | |
2090 | ||
2091 | static int | |
2092 | nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) | |
2093 | { | |
2094 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); | |
ad633619 | 2095 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
3dbd036b | 2096 | struct nv50_head *head = nv50_head(crtc); |
839ca903 | 2097 | struct nv50_head_atom *armh = nv50_head_atom(crtc->state); |
3dbd036b | 2098 | struct nv50_head_atom *asyh = nv50_head_atom(state); |
839ca903 BS |
2099 | struct nouveau_conn_atom *asyc = NULL; |
2100 | struct drm_connector_state *conns; | |
2101 | struct drm_connector *conn; | |
2102 | int i; | |
3dbd036b BS |
2103 | |
2104 | NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active); | |
3dbd036b | 2105 | if (asyh->state.active) { |
3c847d6c | 2106 | for_each_new_connector_in_state(asyh->state.state, conn, conns, i) { |
839ca903 BS |
2107 | if (conns->crtc == crtc) { |
2108 | asyc = nouveau_conn_atom(conns); | |
2109 | break; | |
2110 | } | |
2111 | } | |
2112 | ||
2113 | if (armh->state.active) { | |
2114 | if (asyc) { | |
2115 | if (asyh->state.mode_changed) | |
2116 | asyc->set.scaler = true; | |
2117 | if (armh->base.depth != asyh->base.depth) | |
2118 | asyc->set.dither = true; | |
2119 | } | |
2120 | } else { | |
86276921 GS |
2121 | if (asyc) |
2122 | asyc->set.mask = ~0; | |
839ca903 BS |
2123 | asyh->set.mask = ~0; |
2124 | } | |
2125 | ||
3dbd036b BS |
2126 | if (asyh->state.mode_changed) |
2127 | nv50_head_atomic_check_mode(head, asyh); | |
ad633619 | 2128 | |
839ca903 BS |
2129 | if (asyc) { |
2130 | if (asyc->set.scaler) | |
2131 | nv50_head_atomic_check_view(armh, asyh, asyc); | |
2132 | if (asyc->set.dither) | |
2133 | nv50_head_atomic_check_dither(armh, asyh, asyc); | |
2134 | if (asyc->set.procamp) | |
2135 | nv50_head_atomic_check_procamp(armh, asyh, asyc); | |
2136 | } | |
2137 | ||
ad633619 BS |
2138 | if ((asyh->core.visible = (asyh->base.cpp != 0))) { |
2139 | asyh->core.x = asyh->base.x; | |
2140 | asyh->core.y = asyh->base.y; | |
2141 | asyh->core.w = asyh->base.w; | |
2142 | asyh->core.h = asyh->base.h; | |
2143 | } else | |
ea8ee390 | 2144 | if ((asyh->core.visible = asyh->curs.visible)) { |
ad633619 BS |
2145 | /*XXX: We need to either find some way of having the |
2146 | * primary base layer appear black, while still | |
2147 | * being able to display the other layers, or we | |
2148 | * need to allocate a dummy black surface here. | |
2149 | */ | |
2150 | asyh->core.x = 0; | |
2151 | asyh->core.y = 0; | |
2152 | asyh->core.w = asyh->state.mode.hdisplay; | |
2153 | asyh->core.h = asyh->state.mode.vdisplay; | |
2154 | } | |
2155 | asyh->core.handle = disp->mast.base.vram.handle; | |
2156 | asyh->core.offset = 0; | |
2157 | asyh->core.format = 0xcf; | |
2158 | asyh->core.kind = 0; | |
2159 | asyh->core.layout = 1; | |
2160 | asyh->core.block = 0; | |
2161 | asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4; | |
a7ae1561 BS |
2162 | asyh->lut.handle = disp->mast.base.vram.handle; |
2163 | asyh->lut.offset = head->base.lut.nvbo->bo.offset; | |
6bbab3b6 BS |
2164 | asyh->set.base = armh->base.cpp != asyh->base.cpp; |
2165 | asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp; | |
ad633619 BS |
2166 | } else { |
2167 | asyh->core.visible = false; | |
ea8ee390 | 2168 | asyh->curs.visible = false; |
6bbab3b6 BS |
2169 | asyh->base.cpp = 0; |
2170 | asyh->ovly.cpp = 0; | |
ad633619 BS |
2171 | } |
2172 | ||
2173 | if (!drm_atomic_crtc_needs_modeset(&asyh->state)) { | |
2174 | if (asyh->core.visible) { | |
2175 | if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core))) | |
2176 | asyh->set.core = true; | |
2177 | } else | |
2178 | if (armh->core.visible) { | |
2179 | asyh->clr.core = true; | |
2180 | } | |
ea8ee390 BS |
2181 | |
2182 | if (asyh->curs.visible) { | |
2183 | if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs))) | |
2184 | asyh->set.curs = true; | |
2185 | } else | |
2186 | if (armh->curs.visible) { | |
2187 | asyh->clr.curs = true; | |
2188 | } | |
ad633619 BS |
2189 | } else { |
2190 | asyh->clr.core = armh->core.visible; | |
ea8ee390 | 2191 | asyh->clr.curs = armh->curs.visible; |
ad633619 | 2192 | asyh->set.core = asyh->core.visible; |
ea8ee390 | 2193 | asyh->set.curs = asyh->curs.visible; |
3dbd036b BS |
2194 | } |
2195 | ||
839ca903 BS |
2196 | if (asyh->clr.mask || asyh->set.mask) |
2197 | nv50_atom(asyh->state.state)->lock_core = true; | |
3dbd036b BS |
2198 | return 0; |
2199 | } | |
2200 | ||
438d99e3 | 2201 | static void |
9bfdee9a | 2202 | nv50_head_lut_load(struct drm_crtc *crtc) |
438d99e3 | 2203 | { |
e225f446 | 2204 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
438d99e3 BS |
2205 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
2206 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
804ea3ec | 2207 | u16 *r, *g, *b; |
438d99e3 BS |
2208 | int i; |
2209 | ||
804ea3ec PR |
2210 | r = crtc->gamma_store; |
2211 | g = r + crtc->gamma_size; | |
2212 | b = g + crtc->gamma_size; | |
de8268c5 | 2213 | |
804ea3ec | 2214 | for (i = 0; i < 256; i++) { |
648d4dfd | 2215 | if (disp->disp->oclass < GF110_DISP) { |
804ea3ec PR |
2216 | writew((*r++ >> 2) + 0x0000, lut + (i * 0x08) + 0); |
2217 | writew((*g++ >> 2) + 0x0000, lut + (i * 0x08) + 2); | |
2218 | writew((*b++ >> 2) + 0x0000, lut + (i * 0x08) + 4); | |
de8268c5 | 2219 | } else { |
804ea3ec PR |
2220 | /* 0x6000 interferes with the 14-bit color??? */ |
2221 | writew((*r++ >> 2) + 0x6000, lut + (i * 0x20) + 0); | |
2222 | writew((*g++ >> 2) + 0x6000, lut + (i * 0x20) + 2); | |
2223 | writew((*b++ >> 2) + 0x6000, lut + (i * 0x20) + 4); | |
de8268c5 | 2224 | } |
438d99e3 BS |
2225 | } |
2226 | } | |
2227 | ||
9bfdee9a BS |
2228 | static const struct drm_crtc_helper_funcs |
2229 | nv50_head_help = { | |
839ca903 | 2230 | .atomic_check = nv50_head_atomic_check, |
438d99e3 BS |
2231 | }; |
2232 | ||
9bfdee9a BS |
2233 | static int |
2234 | nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
6d124ff8 DV |
2235 | uint32_t size, |
2236 | struct drm_modeset_acquire_ctx *ctx) | |
9bfdee9a | 2237 | { |
9bfdee9a BS |
2238 | nv50_head_lut_load(crtc); |
2239 | return 0; | |
2240 | } | |
2241 | ||
839ca903 BS |
2242 | static void |
2243 | nv50_head_atomic_destroy_state(struct drm_crtc *crtc, | |
2244 | struct drm_crtc_state *state) | |
2245 | { | |
2246 | struct nv50_head_atom *asyh = nv50_head_atom(state); | |
2247 | __drm_atomic_helper_crtc_destroy_state(&asyh->state); | |
2248 | kfree(asyh); | |
2249 | } | |
2250 | ||
2251 | static struct drm_crtc_state * | |
2252 | nv50_head_atomic_duplicate_state(struct drm_crtc *crtc) | |
2253 | { | |
2254 | struct nv50_head_atom *armh = nv50_head_atom(crtc->state); | |
2255 | struct nv50_head_atom *asyh; | |
2256 | if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL))) | |
2257 | return NULL; | |
2258 | __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state); | |
2259 | asyh->view = armh->view; | |
2260 | asyh->mode = armh->mode; | |
2261 | asyh->lut = armh->lut; | |
2262 | asyh->core = armh->core; | |
2263 | asyh->curs = armh->curs; | |
2264 | asyh->base = armh->base; | |
2265 | asyh->ovly = armh->ovly; | |
2266 | asyh->dither = armh->dither; | |
2267 | asyh->procamp = armh->procamp; | |
2268 | asyh->clr.mask = 0; | |
2269 | asyh->set.mask = 0; | |
2270 | return &asyh->state; | |
2271 | } | |
2272 | ||
2273 | static void | |
2274 | __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, | |
2275 | struct drm_crtc_state *state) | |
2276 | { | |
2277 | if (crtc->state) | |
2278 | crtc->funcs->atomic_destroy_state(crtc, crtc->state); | |
2279 | crtc->state = state; | |
2280 | crtc->state->crtc = crtc; | |
2281 | } | |
2282 | ||
2283 | static void | |
2284 | nv50_head_reset(struct drm_crtc *crtc) | |
2285 | { | |
2286 | struct nv50_head_atom *asyh; | |
2287 | ||
2288 | if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL)))) | |
2289 | return; | |
2290 | ||
2291 | __drm_atomic_helper_crtc_reset(crtc, &asyh->state); | |
2292 | } | |
2293 | ||
9bfdee9a BS |
2294 | static void |
2295 | nv50_head_destroy(struct drm_crtc *crtc) | |
2296 | { | |
2297 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
2298 | struct nv50_disp *disp = nv50_disp(crtc->dev); | |
2299 | struct nv50_head *head = nv50_head(crtc); | |
2300 | ||
2301 | nv50_dmac_destroy(&head->ovly.base, disp->disp); | |
2302 | nv50_pioc_destroy(&head->oimm.base); | |
2303 | ||
2304 | nouveau_bo_unmap(nv_crtc->lut.nvbo); | |
2305 | if (nv_crtc->lut.nvbo) | |
2306 | nouveau_bo_unpin(nv_crtc->lut.nvbo); | |
2307 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); | |
2308 | ||
2309 | drm_crtc_cleanup(crtc); | |
2310 | kfree(crtc); | |
2311 | } | |
2312 | ||
2313 | static const struct drm_crtc_funcs | |
2314 | nv50_head_func = { | |
839ca903 | 2315 | .reset = nv50_head_reset, |
9bfdee9a BS |
2316 | .gamma_set = nv50_head_gamma_set, |
2317 | .destroy = nv50_head_destroy, | |
839ca903 | 2318 | .set_config = drm_atomic_helper_set_config, |
612fb5d9 | 2319 | .page_flip = drm_atomic_helper_page_flip, |
839ca903 BS |
2320 | .atomic_duplicate_state = nv50_head_atomic_duplicate_state, |
2321 | .atomic_destroy_state = nv50_head_atomic_destroy_state, | |
438d99e3 BS |
2322 | }; |
2323 | ||
2324 | static int | |
9bfdee9a | 2325 | nv50_head_create(struct drm_device *dev, int index) |
438d99e3 | 2326 | { |
a01ca78c | 2327 | struct nouveau_drm *drm = nouveau_drm(dev); |
1167c6bc | 2328 | struct nvif_device *device = &drm->client.device; |
e225f446 BS |
2329 | struct nv50_disp *disp = nv50_disp(dev); |
2330 | struct nv50_head *head; | |
973f10c2 | 2331 | struct nv50_base *base; |
22e927d2 | 2332 | struct nv50_curs *curs; |
438d99e3 | 2333 | struct drm_crtc *crtc; |
804ea3ec | 2334 | int ret; |
438d99e3 | 2335 | |
dd0e3d53 BS |
2336 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
2337 | if (!head) | |
438d99e3 BS |
2338 | return -ENOMEM; |
2339 | ||
dd0e3d53 | 2340 | head->base.index = index; |
973f10c2 | 2341 | ret = nv50_base_new(drm, head, &base); |
22e927d2 BS |
2342 | if (ret == 0) |
2343 | ret = nv50_curs_new(drm, head, &curs); | |
973f10c2 BS |
2344 | if (ret) { |
2345 | kfree(head); | |
2346 | return ret; | |
2347 | } | |
2348 | ||
dd0e3d53 | 2349 | crtc = &head->base.base; |
839ca903 | 2350 | drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane, |
9bfdee9a | 2351 | &curs->wndw.plane, &nv50_head_func, |
839ca903 | 2352 | "head-%d", head->base.index); |
9bfdee9a | 2353 | drm_crtc_helper_add(crtc, &nv50_head_help); |
438d99e3 BS |
2354 | drm_mode_crtc_set_gamma_size(crtc, 256); |
2355 | ||
bab7cc18 | 2356 | ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM, |
bb6178b0 | 2357 | 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); |
b5a794b0 | 2358 | if (!ret) { |
547ad072 | 2359 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 2360 | if (!ret) { |
b5a794b0 | 2361 | ret = nouveau_bo_map(head->base.lut.nvbo); |
04c8c210 MS |
2362 | if (ret) |
2363 | nouveau_bo_unpin(head->base.lut.nvbo); | |
2364 | } | |
b5a794b0 BS |
2365 | if (ret) |
2366 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); | |
2367 | } | |
2368 | ||
438d99e3 BS |
2369 | if (ret) |
2370 | goto out; | |
2371 | ||
b5a794b0 | 2372 | /* allocate overlay resources */ |
a01ca78c | 2373 | ret = nv50_oimm_create(device, disp->disp, index, &head->oimm); |
438d99e3 BS |
2374 | if (ret) |
2375 | goto out; | |
2376 | ||
a01ca78c BS |
2377 | ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset, |
2378 | &head->ovly); | |
b5a794b0 BS |
2379 | if (ret) |
2380 | goto out; | |
438d99e3 BS |
2381 | |
2382 | out: | |
2383 | if (ret) | |
9bfdee9a | 2384 | nv50_head_destroy(crtc); |
438d99e3 BS |
2385 | return ret; |
2386 | } | |
2387 | ||
a91d3221 | 2388 | /****************************************************************************** |
d92c8adf | 2389 | * Output path helpers |
a91d3221 | 2390 | *****************************************************************************/ |
6c22ea37 BS |
2391 | static void |
2392 | nv50_outp_release(struct nouveau_encoder *nv_encoder) | |
2393 | { | |
2394 | struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); | |
2395 | struct { | |
2396 | struct nv50_disp_mthd_v1 base; | |
2397 | } args = { | |
2398 | .base.version = 1, | |
2399 | .base.method = NV50_DISP_MTHD_V1_RELEASE, | |
2400 | .base.hasht = nv_encoder->dcb->hasht, | |
2401 | .base.hashm = nv_encoder->dcb->hashm, | |
2402 | }; | |
2403 | ||
2404 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
2405 | nv_encoder->or = -1; | |
2406 | nv_encoder->link = 0; | |
2407 | } | |
2408 | ||
2409 | static int | |
2410 | nv50_outp_acquire(struct nouveau_encoder *nv_encoder) | |
2411 | { | |
2412 | struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); | |
2413 | struct nv50_disp *disp = nv50_disp(drm->dev); | |
2414 | struct { | |
2415 | struct nv50_disp_mthd_v1 base; | |
2416 | struct nv50_disp_acquire_v0 info; | |
2417 | } args = { | |
2418 | .base.version = 1, | |
2419 | .base.method = NV50_DISP_MTHD_V1_ACQUIRE, | |
2420 | .base.hasht = nv_encoder->dcb->hasht, | |
2421 | .base.hashm = nv_encoder->dcb->hashm, | |
2422 | }; | |
2423 | int ret; | |
2424 | ||
2425 | ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
2426 | if (ret) { | |
2427 | NV_ERROR(drm, "error acquiring output path: %d\n", ret); | |
2428 | return ret; | |
2429 | } | |
2430 | ||
2431 | nv_encoder->or = args.info.or; | |
2432 | nv_encoder->link = args.info.link; | |
2433 | return 0; | |
2434 | } | |
2435 | ||
d92c8adf BS |
2436 | static int |
2437 | nv50_outp_atomic_check_view(struct drm_encoder *encoder, | |
2438 | struct drm_crtc_state *crtc_state, | |
2439 | struct drm_connector_state *conn_state, | |
2440 | struct drm_display_mode *native_mode) | |
2441 | { | |
2442 | struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; | |
2443 | struct drm_display_mode *mode = &crtc_state->mode; | |
2444 | struct drm_connector *connector = conn_state->connector; | |
2445 | struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); | |
2446 | struct nouveau_drm *drm = nouveau_drm(encoder->dev); | |
2447 | ||
2448 | NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); | |
2449 | asyc->scaler.full = false; | |
2450 | if (!native_mode) | |
2451 | return 0; | |
2452 | ||
2453 | if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { | |
2454 | switch (connector->connector_type) { | |
2455 | case DRM_MODE_CONNECTOR_LVDS: | |
2456 | case DRM_MODE_CONNECTOR_eDP: | |
2457 | /* Force use of scaler for non-EDID modes. */ | |
2458 | if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) | |
2459 | break; | |
2460 | mode = native_mode; | |
2461 | asyc->scaler.full = true; | |
2462 | break; | |
2463 | default: | |
2464 | break; | |
2465 | } | |
2466 | } else { | |
2467 | mode = native_mode; | |
2468 | } | |
2469 | ||
2470 | if (!drm_mode_equal(adjusted_mode, mode)) { | |
2471 | drm_mode_copy(adjusted_mode, mode); | |
2472 | crtc_state->mode_changed = true; | |
2473 | } | |
2474 | ||
2475 | return 0; | |
2476 | } | |
2477 | ||
839ca903 BS |
2478 | static int |
2479 | nv50_outp_atomic_check(struct drm_encoder *encoder, | |
2480 | struct drm_crtc_state *crtc_state, | |
2481 | struct drm_connector_state *conn_state) | |
a91d3221 | 2482 | { |
839ca903 BS |
2483 | struct nouveau_connector *nv_connector = |
2484 | nouveau_connector(conn_state->connector); | |
2485 | return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, | |
2486 | nv_connector->native_mode); | |
a91d3221 BS |
2487 | } |
2488 | ||
26f6d88b BS |
2489 | /****************************************************************************** |
2490 | * DAC | |
2491 | *****************************************************************************/ | |
8eaa9669 | 2492 | static void |
839ca903 | 2493 | nv50_dac_disable(struct drm_encoder *encoder) |
8eaa9669 | 2494 | { |
f20c665c BS |
2495 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2496 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2497 | const int or = nv_encoder->or; | |
2498 | u32 *push; | |
2499 | ||
2500 | if (nv_encoder->crtc) { | |
f20c665c BS |
2501 | push = evo_wait(mast, 4); |
2502 | if (push) { | |
2503 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { | |
2504 | evo_mthd(push, 0x0400 + (or * 0x080), 1); | |
2505 | evo_data(push, 0x00000000); | |
2506 | } else { | |
2507 | evo_mthd(push, 0x0180 + (or * 0x020), 1); | |
2508 | evo_data(push, 0x00000000); | |
2509 | } | |
2510 | evo_kick(push, mast); | |
2511 | } | |
2512 | } | |
2513 | ||
2514 | nv_encoder->crtc = NULL; | |
6c22ea37 | 2515 | nv50_outp_release(nv_encoder); |
8eaa9669 BS |
2516 | } |
2517 | ||
2518 | static void | |
839ca903 | 2519 | nv50_dac_enable(struct drm_encoder *encoder) |
8eaa9669 | 2520 | { |
e225f446 | 2521 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
8eaa9669 BS |
2522 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2523 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
839ca903 | 2524 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
97b19b5c | 2525 | u32 *push; |
8eaa9669 | 2526 | |
6c22ea37 BS |
2527 | nv50_outp_acquire(nv_encoder); |
2528 | ||
97b19b5c | 2529 | push = evo_wait(mast, 8); |
8eaa9669 | 2530 | if (push) { |
648d4dfd | 2531 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
2532 | u32 syncs = 0x00000000; |
2533 | ||
2534 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2535 | syncs |= 0x00000001; | |
2536 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2537 | syncs |= 0x00000002; | |
2538 | ||
2539 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); | |
2540 | evo_data(push, 1 << nv_crtc->index); | |
2541 | evo_data(push, syncs); | |
2542 | } else { | |
2543 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
2544 | u32 syncs = 0x00000001; | |
2545 | ||
2546 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2547 | syncs |= 0x00000008; | |
2548 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2549 | syncs |= 0x00000010; | |
2550 | ||
2551 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2552 | magic |= 0x00000001; | |
2553 | ||
2554 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
2555 | evo_data(push, syncs); | |
2556 | evo_data(push, magic); | |
2557 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); | |
2558 | evo_data(push, 1 << nv_crtc->index); | |
2559 | } | |
2560 | ||
2561 | evo_kick(push, mast); | |
8eaa9669 BS |
2562 | } |
2563 | ||
2564 | nv_encoder->crtc = encoder->crtc; | |
2565 | } | |
2566 | ||
b6d8e7ec | 2567 | static enum drm_connector_status |
e225f446 | 2568 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
b6d8e7ec | 2569 | { |
c4abd317 | 2570 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 2571 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
c4abd317 BS |
2572 | struct { |
2573 | struct nv50_disp_mthd_v1 base; | |
2574 | struct nv50_disp_dac_load_v0 load; | |
2575 | } args = { | |
2576 | .base.version = 1, | |
2577 | .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, | |
2578 | .base.hasht = nv_encoder->dcb->hasht, | |
2579 | .base.hashm = nv_encoder->dcb->hashm, | |
2580 | }; | |
2581 | int ret; | |
2582 | ||
2583 | args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; | |
2584 | if (args.load.data == 0) | |
2585 | args.load.data = 340; | |
b681993f | 2586 | |
c4abd317 BS |
2587 | ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
2588 | if (ret || !args.load.load) | |
35b21d39 | 2589 | return connector_status_disconnected; |
b681993f | 2590 | |
35b21d39 | 2591 | return connector_status_connected; |
b6d8e7ec BS |
2592 | } |
2593 | ||
f20c665c BS |
2594 | static const struct drm_encoder_helper_funcs |
2595 | nv50_dac_help = { | |
839ca903 BS |
2596 | .atomic_check = nv50_outp_atomic_check, |
2597 | .enable = nv50_dac_enable, | |
2598 | .disable = nv50_dac_disable, | |
e225f446 | 2599 | .detect = nv50_dac_detect |
8eaa9669 BS |
2600 | }; |
2601 | ||
f20c665c BS |
2602 | static void |
2603 | nv50_dac_destroy(struct drm_encoder *encoder) | |
2604 | { | |
2605 | drm_encoder_cleanup(encoder); | |
2606 | kfree(encoder); | |
2607 | } | |
2608 | ||
2609 | static const struct drm_encoder_funcs | |
2610 | nv50_dac_func = { | |
e225f446 | 2611 | .destroy = nv50_dac_destroy, |
8eaa9669 BS |
2612 | }; |
2613 | ||
2614 | static int | |
e225f446 | 2615 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
8eaa9669 | 2616 | { |
5ed50209 | 2617 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1167c6bc | 2618 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); |
2aa5eac5 | 2619 | struct nvkm_i2c_bus *bus; |
8eaa9669 BS |
2620 | struct nouveau_encoder *nv_encoder; |
2621 | struct drm_encoder *encoder; | |
5ed50209 | 2622 | int type = DRM_MODE_ENCODER_DAC; |
8eaa9669 BS |
2623 | |
2624 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2625 | if (!nv_encoder) | |
2626 | return -ENOMEM; | |
2627 | nv_encoder->dcb = dcbe; | |
2aa5eac5 BS |
2628 | |
2629 | bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); | |
2630 | if (bus) | |
2631 | nv_encoder->i2c = &bus->i2c; | |
8eaa9669 BS |
2632 | |
2633 | encoder = to_drm_encoder(nv_encoder); | |
2634 | encoder->possible_crtcs = dcbe->heads; | |
2635 | encoder->possible_clones = 0; | |
5a223dac BS |
2636 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, |
2637 | "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); | |
f20c665c | 2638 | drm_encoder_helper_add(encoder, &nv50_dac_help); |
8eaa9669 BS |
2639 | |
2640 | drm_mode_connector_attach_encoder(connector, encoder); | |
2641 | return 0; | |
2642 | } | |
26f6d88b | 2643 | |
78951d22 BS |
2644 | /****************************************************************************** |
2645 | * Audio | |
2646 | *****************************************************************************/ | |
2647 | static void | |
f20c665c BS |
2648 | nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
2649 | { | |
2650 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2651 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
2652 | struct { | |
2653 | struct nv50_disp_mthd_v1 base; | |
2654 | struct nv50_disp_sor_hda_eld_v0 eld; | |
2655 | } args = { | |
2656 | .base.version = 1, | |
2657 | .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
2658 | .base.hasht = nv_encoder->dcb->hasht, | |
2659 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
2660 | (0x0100 << nv_crtc->index), | |
2661 | }; | |
2662 | ||
2663 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
2664 | } | |
2665 | ||
2666 | static void | |
2667 | nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
78951d22 BS |
2668 | { |
2669 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
cc2a9071 | 2670 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
78951d22 | 2671 | struct nouveau_connector *nv_connector; |
e225f446 | 2672 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
d889c524 BS |
2673 | struct __packed { |
2674 | struct { | |
2675 | struct nv50_disp_mthd_v1 mthd; | |
2676 | struct nv50_disp_sor_hda_eld_v0 eld; | |
2677 | } base; | |
120b0c39 BS |
2678 | u8 data[sizeof(nv_connector->base.eld)]; |
2679 | } args = { | |
d889c524 BS |
2680 | .base.mthd.version = 1, |
2681 | .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
2682 | .base.mthd.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
2683 | .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
2684 | (0x0100 << nv_crtc->index), | |
120b0c39 | 2685 | }; |
78951d22 BS |
2686 | |
2687 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2688 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
2689 | return; | |
2690 | ||
78951d22 | 2691 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
120b0c39 | 2692 | memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); |
78951d22 | 2693 | |
938fd8aa JN |
2694 | nvif_mthd(disp->disp, 0, &args, |
2695 | sizeof(args.base) + drm_eld_size(args.data)); | |
78951d22 BS |
2696 | } |
2697 | ||
f20c665c BS |
2698 | /****************************************************************************** |
2699 | * HDMI | |
2700 | *****************************************************************************/ | |
78951d22 | 2701 | static void |
f20c665c | 2702 | nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 BS |
2703 | { |
2704 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 2705 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
120b0c39 BS |
2706 | struct { |
2707 | struct nv50_disp_mthd_v1 base; | |
f20c665c | 2708 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; |
120b0c39 BS |
2709 | } args = { |
2710 | .base.version = 1, | |
f20c665c BS |
2711 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, |
2712 | .base.hasht = nv_encoder->dcb->hasht, | |
2713 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
2714 | (0x0100 << nv_crtc->index), | |
120b0c39 | 2715 | }; |
78951d22 | 2716 | |
120b0c39 | 2717 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
2718 | } |
2719 | ||
78951d22 | 2720 | static void |
f20c665c | 2721 | nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 | 2722 | { |
64d9cc04 BS |
2723 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2724 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
e225f446 | 2725 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
2726 | struct { |
2727 | struct nv50_disp_mthd_v1 base; | |
2728 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
34fd3e5d | 2729 | u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ |
e00f2235 BS |
2730 | } args = { |
2731 | .base.version = 1, | |
2732 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
2733 | .base.hasht = nv_encoder->dcb->hasht, | |
2734 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
2735 | (0x0100 << nv_crtc->index), | |
2736 | .pwr.state = 1, | |
2737 | .pwr.rekey = 56, /* binary driver, and tegra, constant */ | |
2738 | }; | |
2739 | struct nouveau_connector *nv_connector; | |
64d9cc04 | 2740 | u32 max_ac_packet; |
34fd3e5d AB |
2741 | union hdmi_infoframe avi_frame; |
2742 | union hdmi_infoframe vendor_frame; | |
2743 | int ret; | |
2744 | int size; | |
64d9cc04 BS |
2745 | |
2746 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2747 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
2748 | return; | |
2749 | ||
0c1f528c SS |
2750 | ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode, |
2751 | false); | |
34fd3e5d AB |
2752 | if (!ret) { |
2753 | /* We have an AVI InfoFrame, populate it to the display */ | |
2754 | args.pwr.avi_infoframe_length | |
2755 | = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); | |
2756 | } | |
2757 | ||
2758 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, mode); | |
2759 | if (!ret) { | |
2760 | /* We have a Vendor InfoFrame, populate it to the display */ | |
2761 | args.pwr.vendor_infoframe_length | |
2762 | = hdmi_infoframe_pack(&vendor_frame, | |
2763 | args.infoframes | |
2764 | + args.pwr.avi_infoframe_length, | |
2765 | 17); | |
2766 | } | |
2767 | ||
64d9cc04 | 2768 | max_ac_packet = mode->htotal - mode->hdisplay; |
e00f2235 | 2769 | max_ac_packet -= args.pwr.rekey; |
64d9cc04 | 2770 | max_ac_packet -= 18; /* constant from tegra */ |
e00f2235 | 2771 | args.pwr.max_ac_packet = max_ac_packet / 32; |
091e40cd | 2772 | |
34fd3e5d AB |
2773 | size = sizeof(args.base) |
2774 | + sizeof(args.pwr) | |
2775 | + args.pwr.avi_infoframe_length | |
2776 | + args.pwr.vendor_infoframe_length; | |
2777 | nvif_mthd(disp->disp, 0, &args, size); | |
f20c665c | 2778 | nv50_audio_enable(encoder, mode); |
78951d22 BS |
2779 | } |
2780 | ||
52aa30f2 BS |
2781 | /****************************************************************************** |
2782 | * MST | |
2783 | *****************************************************************************/ | |
f479c0ba BS |
2784 | #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) |
2785 | #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) | |
2786 | #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) | |
2787 | ||
52aa30f2 BS |
2788 | struct nv50_mstm { |
2789 | struct nouveau_encoder *outp; | |
2790 | ||
2791 | struct drm_dp_mst_topology_mgr mgr; | |
f479c0ba BS |
2792 | struct nv50_msto *msto[4]; |
2793 | ||
2794 | bool modified; | |
6c22ea37 BS |
2795 | bool disabled; |
2796 | int links; | |
f479c0ba BS |
2797 | }; |
2798 | ||
2799 | struct nv50_mstc { | |
2800 | struct nv50_mstm *mstm; | |
2801 | struct drm_dp_mst_port *port; | |
2802 | struct drm_connector connector; | |
2803 | ||
2804 | struct drm_display_mode *native; | |
2805 | struct edid *edid; | |
2806 | ||
2807 | int pbn; | |
52aa30f2 BS |
2808 | }; |
2809 | ||
f479c0ba BS |
2810 | struct nv50_msto { |
2811 | struct drm_encoder encoder; | |
2812 | ||
2813 | struct nv50_head *head; | |
2814 | struct nv50_mstc *mstc; | |
2815 | bool disabled; | |
2816 | }; | |
2817 | ||
2818 | static struct drm_dp_payload * | |
2819 | nv50_msto_payload(struct nv50_msto *msto) | |
2820 | { | |
2821 | struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); | |
2822 | struct nv50_mstc *mstc = msto->mstc; | |
2823 | struct nv50_mstm *mstm = mstc->mstm; | |
2824 | int vcpi = mstc->port->vcpi.vcpi, i; | |
2825 | ||
2826 | NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); | |
2827 | for (i = 0; i < mstm->mgr.max_payloads; i++) { | |
2828 | struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; | |
2829 | NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", | |
2830 | mstm->outp->base.base.name, i, payload->vcpi, | |
2831 | payload->start_slot, payload->num_slots); | |
2832 | } | |
2833 | ||
2834 | for (i = 0; i < mstm->mgr.max_payloads; i++) { | |
2835 | struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; | |
2836 | if (payload->vcpi == vcpi) | |
2837 | return payload; | |
2838 | } | |
2839 | ||
2840 | return NULL; | |
2841 | } | |
2842 | ||
2843 | static void | |
2844 | nv50_msto_cleanup(struct nv50_msto *msto) | |
2845 | { | |
2846 | struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); | |
2847 | struct nv50_mstc *mstc = msto->mstc; | |
2848 | struct nv50_mstm *mstm = mstc->mstm; | |
2849 | ||
2850 | NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); | |
2851 | if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto)) | |
2852 | drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); | |
2853 | if (msto->disabled) { | |
2854 | msto->mstc = NULL; | |
2855 | msto->head = NULL; | |
2856 | msto->disabled = false; | |
2857 | } | |
2858 | } | |
2859 | ||
2860 | static void | |
2861 | nv50_msto_prepare(struct nv50_msto *msto) | |
2862 | { | |
2863 | struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); | |
2864 | struct nv50_mstc *mstc = msto->mstc; | |
2865 | struct nv50_mstm *mstm = mstc->mstm; | |
2866 | struct { | |
2867 | struct nv50_disp_mthd_v1 base; | |
2868 | struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; | |
2869 | } args = { | |
2870 | .base.version = 1, | |
2871 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, | |
2872 | .base.hasht = mstm->outp->dcb->hasht, | |
2873 | .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | | |
2874 | (0x0100 << msto->head->base.index), | |
2875 | }; | |
2876 | ||
2877 | NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); | |
2878 | if (mstc->port && mstc->port->vcpi.vcpi > 0) { | |
2879 | struct drm_dp_payload *payload = nv50_msto_payload(msto); | |
2880 | if (payload) { | |
2881 | args.vcpi.start_slot = payload->start_slot; | |
2882 | args.vcpi.num_slots = payload->num_slots; | |
2883 | args.vcpi.pbn = mstc->port->vcpi.pbn; | |
2884 | args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; | |
2885 | } | |
2886 | } | |
2887 | ||
2888 | NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", | |
2889 | msto->encoder.name, msto->head->base.base.name, | |
2890 | args.vcpi.start_slot, args.vcpi.num_slots, | |
2891 | args.vcpi.pbn, args.vcpi.aligned_pbn); | |
2892 | nvif_mthd(&drm->display->disp, 0, &args, sizeof(args)); | |
2893 | } | |
2894 | ||
2895 | static int | |
2896 | nv50_msto_atomic_check(struct drm_encoder *encoder, | |
2897 | struct drm_crtc_state *crtc_state, | |
2898 | struct drm_connector_state *conn_state) | |
2899 | { | |
2900 | struct nv50_mstc *mstc = nv50_mstc(conn_state->connector); | |
2901 | struct nv50_mstm *mstm = mstc->mstm; | |
2902 | int bpp = conn_state->connector->display_info.bpc * 3; | |
2903 | int slots; | |
2904 | ||
2905 | mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp); | |
2906 | ||
2907 | slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); | |
2908 | if (slots < 0) | |
2909 | return slots; | |
2910 | ||
2911 | return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, | |
2912 | mstc->native); | |
2913 | } | |
2914 | ||
2915 | static void | |
2916 | nv50_msto_enable(struct drm_encoder *encoder) | |
2917 | { | |
2918 | struct nv50_head *head = nv50_head(encoder->crtc); | |
2919 | struct nv50_msto *msto = nv50_msto(encoder); | |
2920 | struct nv50_mstc *mstc = NULL; | |
2921 | struct nv50_mstm *mstm = NULL; | |
2922 | struct drm_connector *connector; | |
875dd626 | 2923 | struct drm_connector_list_iter conn_iter; |
f479c0ba BS |
2924 | u8 proto, depth; |
2925 | int slots; | |
2926 | bool r; | |
2927 | ||
875dd626 GP |
2928 | drm_connector_list_iter_begin(encoder->dev, &conn_iter); |
2929 | drm_for_each_connector_iter(connector, &conn_iter) { | |
f479c0ba BS |
2930 | if (connector->state->best_encoder == &msto->encoder) { |
2931 | mstc = nv50_mstc(connector); | |
2932 | mstm = mstc->mstm; | |
2933 | break; | |
2934 | } | |
2935 | } | |
875dd626 | 2936 | drm_connector_list_iter_end(&conn_iter); |
f479c0ba BS |
2937 | |
2938 | if (WARN_ON(!mstc)) | |
2939 | return; | |
2940 | ||
1e797f55 PD |
2941 | slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); |
2942 | r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots); | |
f479c0ba BS |
2943 | WARN_ON(!r); |
2944 | ||
6c22ea37 BS |
2945 | if (!mstm->links++) |
2946 | nv50_outp_acquire(mstm->outp); | |
2947 | ||
2948 | if (mstm->outp->link & 1) | |
f479c0ba BS |
2949 | proto = 0x8; |
2950 | else | |
2951 | proto = 0x9; | |
2952 | ||
2953 | switch (mstc->connector.display_info.bpc) { | |
2954 | case 6: depth = 0x2; break; | |
2955 | case 8: depth = 0x5; break; | |
2956 | case 10: | |
2957 | default: depth = 0x6; break; | |
2958 | } | |
2959 | ||
2960 | mstm->outp->update(mstm->outp, head->base.index, | |
2961 | &head->base.base.state->adjusted_mode, proto, depth); | |
2962 | ||
2963 | msto->head = head; | |
2964 | msto->mstc = mstc; | |
2965 | mstm->modified = true; | |
2966 | } | |
2967 | ||
2968 | static void | |
2969 | nv50_msto_disable(struct drm_encoder *encoder) | |
2970 | { | |
2971 | struct nv50_msto *msto = nv50_msto(encoder); | |
2972 | struct nv50_mstc *mstc = msto->mstc; | |
2973 | struct nv50_mstm *mstm = mstc->mstm; | |
2974 | ||
2975 | if (mstc->port) | |
2976 | drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); | |
2977 | ||
2978 | mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); | |
2979 | mstm->modified = true; | |
6c22ea37 BS |
2980 | if (!--mstm->links) |
2981 | mstm->disabled = true; | |
f479c0ba BS |
2982 | msto->disabled = true; |
2983 | } | |
2984 | ||
2985 | static const struct drm_encoder_helper_funcs | |
2986 | nv50_msto_help = { | |
2987 | .disable = nv50_msto_disable, | |
2988 | .enable = nv50_msto_enable, | |
2989 | .atomic_check = nv50_msto_atomic_check, | |
2990 | }; | |
2991 | ||
2992 | static void | |
2993 | nv50_msto_destroy(struct drm_encoder *encoder) | |
2994 | { | |
2995 | struct nv50_msto *msto = nv50_msto(encoder); | |
2996 | drm_encoder_cleanup(&msto->encoder); | |
2997 | kfree(msto); | |
2998 | } | |
2999 | ||
3000 | static const struct drm_encoder_funcs | |
3001 | nv50_msto = { | |
3002 | .destroy = nv50_msto_destroy, | |
3003 | }; | |
3004 | ||
3005 | static int | |
3006 | nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, | |
3007 | struct nv50_msto **pmsto) | |
3008 | { | |
3009 | struct nv50_msto *msto; | |
3010 | int ret; | |
3011 | ||
3012 | if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) | |
3013 | return -ENOMEM; | |
3014 | ||
3015 | ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, | |
3016 | DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); | |
3017 | if (ret) { | |
3018 | kfree(*pmsto); | |
3019 | *pmsto = NULL; | |
3020 | return ret; | |
3021 | } | |
3022 | ||
3023 | drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); | |
3024 | msto->encoder.possible_crtcs = heads; | |
3025 | return 0; | |
3026 | } | |
3027 | ||
3028 | static struct drm_encoder * | |
3029 | nv50_mstc_atomic_best_encoder(struct drm_connector *connector, | |
3030 | struct drm_connector_state *connector_state) | |
3031 | { | |
3032 | struct nv50_head *head = nv50_head(connector_state->crtc); | |
3033 | struct nv50_mstc *mstc = nv50_mstc(connector); | |
3034 | if (mstc->port) { | |
3035 | struct nv50_mstm *mstm = mstc->mstm; | |
3036 | return &mstm->msto[head->base.index]->encoder; | |
3037 | } | |
3038 | return NULL; | |
3039 | } | |
3040 | ||
3041 | static struct drm_encoder * | |
3042 | nv50_mstc_best_encoder(struct drm_connector *connector) | |
3043 | { | |
3044 | struct nv50_mstc *mstc = nv50_mstc(connector); | |
3045 | if (mstc->port) { | |
3046 | struct nv50_mstm *mstm = mstc->mstm; | |
3047 | return &mstm->msto[0]->encoder; | |
3048 | } | |
3049 | return NULL; | |
3050 | } | |
3051 | ||
3052 | static enum drm_mode_status | |
3053 | nv50_mstc_mode_valid(struct drm_connector *connector, | |
3054 | struct drm_display_mode *mode) | |
3055 | { | |
3056 | return MODE_OK; | |
3057 | } | |
3058 | ||
3059 | static int | |
3060 | nv50_mstc_get_modes(struct drm_connector *connector) | |
3061 | { | |
3062 | struct nv50_mstc *mstc = nv50_mstc(connector); | |
3063 | int ret = 0; | |
3064 | ||
3065 | mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); | |
3066 | drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid); | |
3067 | if (mstc->edid) { | |
3068 | ret = drm_add_edid_modes(&mstc->connector, mstc->edid); | |
3069 | drm_edid_to_eld(&mstc->connector, mstc->edid); | |
3070 | } | |
3071 | ||
3072 | if (!mstc->connector.display_info.bpc) | |
3073 | mstc->connector.display_info.bpc = 8; | |
3074 | ||
3075 | if (mstc->native) | |
3076 | drm_mode_destroy(mstc->connector.dev, mstc->native); | |
3077 | mstc->native = nouveau_conn_native_mode(&mstc->connector); | |
3078 | return ret; | |
3079 | } | |
3080 | ||
3081 | static const struct drm_connector_helper_funcs | |
3082 | nv50_mstc_help = { | |
3083 | .get_modes = nv50_mstc_get_modes, | |
3084 | .mode_valid = nv50_mstc_mode_valid, | |
3085 | .best_encoder = nv50_mstc_best_encoder, | |
3086 | .atomic_best_encoder = nv50_mstc_atomic_best_encoder, | |
3087 | }; | |
3088 | ||
3089 | static enum drm_connector_status | |
3090 | nv50_mstc_detect(struct drm_connector *connector, bool force) | |
3091 | { | |
3092 | struct nv50_mstc *mstc = nv50_mstc(connector); | |
3093 | if (!mstc->port) | |
3094 | return connector_status_disconnected; | |
3095 | return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port); | |
3096 | } | |
3097 | ||
3098 | static void | |
3099 | nv50_mstc_destroy(struct drm_connector *connector) | |
3100 | { | |
3101 | struct nv50_mstc *mstc = nv50_mstc(connector); | |
3102 | drm_connector_cleanup(&mstc->connector); | |
3103 | kfree(mstc); | |
3104 | } | |
3105 | ||
3106 | static const struct drm_connector_funcs | |
3107 | nv50_mstc = { | |
f479c0ba BS |
3108 | .reset = nouveau_conn_reset, |
3109 | .detect = nv50_mstc_detect, | |
3110 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f479c0ba BS |
3111 | .destroy = nv50_mstc_destroy, |
3112 | .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, | |
3113 | .atomic_destroy_state = nouveau_conn_atomic_destroy_state, | |
3114 | .atomic_set_property = nouveau_conn_atomic_set_property, | |
3115 | .atomic_get_property = nouveau_conn_atomic_get_property, | |
3116 | }; | |
3117 | ||
3118 | static int | |
3119 | nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, | |
3120 | const char *path, struct nv50_mstc **pmstc) | |
3121 | { | |
3122 | struct drm_device *dev = mstm->outp->base.base.dev; | |
3123 | struct nv50_mstc *mstc; | |
3124 | int ret, i; | |
3125 | ||
3126 | if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) | |
3127 | return -ENOMEM; | |
3128 | mstc->mstm = mstm; | |
3129 | mstc->port = port; | |
3130 | ||
3131 | ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, | |
3132 | DRM_MODE_CONNECTOR_DisplayPort); | |
3133 | if (ret) { | |
3134 | kfree(*pmstc); | |
3135 | *pmstc = NULL; | |
3136 | return ret; | |
3137 | } | |
3138 | ||
3139 | drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); | |
3140 | ||
3141 | mstc->connector.funcs->reset(&mstc->connector); | |
3142 | nouveau_conn_attach_properties(&mstc->connector); | |
3143 | ||
27a451e8 | 3144 | for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) |
f479c0ba BS |
3145 | drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); |
3146 | ||
3147 | drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); | |
3148 | drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); | |
3149 | drm_mode_connector_set_path_property(&mstc->connector, path); | |
3150 | return 0; | |
3151 | } | |
3152 | ||
3153 | static void | |
3154 | nv50_mstm_cleanup(struct nv50_mstm *mstm) | |
3155 | { | |
3156 | struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); | |
3157 | struct drm_encoder *encoder; | |
3158 | int ret; | |
3159 | ||
3160 | NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); | |
3161 | ret = drm_dp_check_act_status(&mstm->mgr); | |
3162 | ||
3163 | ret = drm_dp_update_payload_part2(&mstm->mgr); | |
3164 | ||
3165 | drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { | |
3166 | if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { | |
3167 | struct nv50_msto *msto = nv50_msto(encoder); | |
3168 | struct nv50_mstc *mstc = msto->mstc; | |
3169 | if (mstc && mstc->mstm == mstm) | |
3170 | nv50_msto_cleanup(msto); | |
3171 | } | |
3172 | } | |
3173 | ||
3174 | mstm->modified = false; | |
3175 | } | |
3176 | ||
3177 | static void | |
3178 | nv50_mstm_prepare(struct nv50_mstm *mstm) | |
3179 | { | |
3180 | struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); | |
3181 | struct drm_encoder *encoder; | |
3182 | int ret; | |
3183 | ||
3184 | NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); | |
3185 | ret = drm_dp_update_payload_part1(&mstm->mgr); | |
3186 | ||
3187 | drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { | |
3188 | if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { | |
3189 | struct nv50_msto *msto = nv50_msto(encoder); | |
3190 | struct nv50_mstc *mstc = msto->mstc; | |
3191 | if (mstc && mstc->mstm == mstm) | |
3192 | nv50_msto_prepare(msto); | |
3193 | } | |
3194 | } | |
6c22ea37 BS |
3195 | |
3196 | if (mstm->disabled) { | |
3197 | if (!mstm->links) | |
3198 | nv50_outp_release(mstm->outp); | |
3199 | mstm->disabled = false; | |
3200 | } | |
f479c0ba BS |
3201 | } |
3202 | ||
3203 | static void | |
3204 | nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr) | |
3205 | { | |
3206 | struct nv50_mstm *mstm = nv50_mstm(mgr); | |
3207 | drm_kms_helper_hotplug_event(mstm->outp->base.base.dev); | |
3208 | } | |
3209 | ||
3210 | static void | |
3211 | nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, | |
3212 | struct drm_connector *connector) | |
3213 | { | |
3214 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
3215 | struct nv50_mstc *mstc = nv50_mstc(connector); | |
3216 | ||
3217 | drm_connector_unregister(&mstc->connector); | |
3218 | ||
3219 | drm_modeset_lock_all(drm->dev); | |
3220 | drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); | |
3221 | mstc->port = NULL; | |
3222 | drm_modeset_unlock_all(drm->dev); | |
3223 | ||
3224 | drm_connector_unreference(&mstc->connector); | |
3225 | } | |
3226 | ||
3227 | static void | |
3228 | nv50_mstm_register_connector(struct drm_connector *connector) | |
3229 | { | |
3230 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
3231 | ||
3232 | drm_modeset_lock_all(drm->dev); | |
3233 | drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); | |
3234 | drm_modeset_unlock_all(drm->dev); | |
3235 | ||
3236 | drm_connector_register(connector); | |
3237 | } | |
3238 | ||
3239 | static struct drm_connector * | |
3240 | nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, | |
3241 | struct drm_dp_mst_port *port, const char *path) | |
3242 | { | |
3243 | struct nv50_mstm *mstm = nv50_mstm(mgr); | |
3244 | struct nv50_mstc *mstc; | |
3245 | int ret; | |
3246 | ||
3247 | ret = nv50_mstc_new(mstm, port, path, &mstc); | |
3248 | if (ret) { | |
3249 | if (mstc) | |
3250 | mstc->connector.funcs->destroy(&mstc->connector); | |
3251 | return NULL; | |
3252 | } | |
3253 | ||
3254 | return &mstc->connector; | |
3255 | } | |
3256 | ||
3257 | static const struct drm_dp_mst_topology_cbs | |
3258 | nv50_mstm = { | |
3259 | .add_connector = nv50_mstm_add_connector, | |
3260 | .register_connector = nv50_mstm_register_connector, | |
3261 | .destroy_connector = nv50_mstm_destroy_connector, | |
3262 | .hotplug = nv50_mstm_hotplug, | |
3263 | }; | |
3264 | ||
3265 | void | |
3266 | nv50_mstm_service(struct nv50_mstm *mstm) | |
3267 | { | |
227f66d2 | 3268 | struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; |
f479c0ba BS |
3269 | bool handled = true; |
3270 | int ret; | |
3271 | u8 esi[8] = {}; | |
3272 | ||
227f66d2 BS |
3273 | if (!aux) |
3274 | return; | |
3275 | ||
f479c0ba BS |
3276 | while (handled) { |
3277 | ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); | |
3278 | if (ret != 8) { | |
3279 | drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); | |
3280 | return; | |
3281 | } | |
3282 | ||
3283 | drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); | |
3284 | if (!handled) | |
3285 | break; | |
3286 | ||
3287 | drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); | |
3288 | } | |
3289 | } | |
3290 | ||
3291 | void | |
3292 | nv50_mstm_remove(struct nv50_mstm *mstm) | |
3293 | { | |
3294 | if (mstm) | |
3295 | drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); | |
3296 | } | |
3297 | ||
52aa30f2 BS |
3298 | static int |
3299 | nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) | |
3300 | { | |
3301 | struct nouveau_encoder *outp = mstm->outp; | |
3302 | struct { | |
3303 | struct nv50_disp_mthd_v1 base; | |
3304 | struct nv50_disp_sor_dp_mst_link_v0 mst; | |
3305 | } args = { | |
3306 | .base.version = 1, | |
3307 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, | |
3308 | .base.hasht = outp->dcb->hasht, | |
3309 | .base.hashm = outp->dcb->hashm, | |
3310 | .mst.state = state, | |
3311 | }; | |
3312 | struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); | |
3313 | struct nvif_object *disp = &drm->display->disp; | |
3314 | int ret; | |
3315 | ||
3316 | if (dpcd >= 0x12) { | |
3317 | ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd); | |
3318 | if (ret < 0) | |
3319 | return ret; | |
3320 | ||
3321 | dpcd &= ~DP_MST_EN; | |
3322 | if (state) | |
3323 | dpcd |= DP_MST_EN; | |
3324 | ||
3325 | ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd); | |
3326 | if (ret < 0) | |
3327 | return ret; | |
3328 | } | |
3329 | ||
3330 | return nvif_mthd(disp, 0, &args, sizeof(args)); | |
3331 | } | |
3332 | ||
3333 | int | |
3334 | nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) | |
3335 | { | |
3336 | int ret, state = 0; | |
3337 | ||
3338 | if (!mstm) | |
3339 | return 0; | |
3340 | ||
3ca03cac | 3341 | if (dpcd[0] >= 0x12) { |
52aa30f2 BS |
3342 | ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]); |
3343 | if (ret < 0) | |
3344 | return ret; | |
3345 | ||
3ca03cac BS |
3346 | if (!(dpcd[1] & DP_MST_CAP)) |
3347 | dpcd[0] = 0x11; | |
3348 | else | |
3349 | state = allow; | |
52aa30f2 BS |
3350 | } |
3351 | ||
3352 | ret = nv50_mstm_enable(mstm, dpcd[0], state); | |
3353 | if (ret) | |
3354 | return ret; | |
3355 | ||
3356 | ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state); | |
3357 | if (ret) | |
3358 | return nv50_mstm_enable(mstm, dpcd[0], 0); | |
3359 | ||
3360 | return mstm->mgr.mst_state; | |
3361 | } | |
3362 | ||
f479c0ba BS |
3363 | static void |
3364 | nv50_mstm_fini(struct nv50_mstm *mstm) | |
3365 | { | |
3366 | if (mstm && mstm->mgr.mst_state) | |
3367 | drm_dp_mst_topology_mgr_suspend(&mstm->mgr); | |
3368 | } | |
3369 | ||
3370 | static void | |
3371 | nv50_mstm_init(struct nv50_mstm *mstm) | |
3372 | { | |
3373 | if (mstm && mstm->mgr.mst_state) | |
3374 | drm_dp_mst_topology_mgr_resume(&mstm->mgr); | |
3375 | } | |
3376 | ||
52aa30f2 BS |
3377 | static void |
3378 | nv50_mstm_del(struct nv50_mstm **pmstm) | |
3379 | { | |
3380 | struct nv50_mstm *mstm = *pmstm; | |
3381 | if (mstm) { | |
3382 | kfree(*pmstm); | |
3383 | *pmstm = NULL; | |
3384 | } | |
3385 | } | |
3386 | ||
3387 | static int | |
3388 | nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, | |
3389 | int conn_base_id, struct nv50_mstm **pmstm) | |
3390 | { | |
3391 | const int max_payloads = hweight8(outp->dcb->heads); | |
3392 | struct drm_device *dev = outp->base.base.dev; | |
3393 | struct nv50_mstm *mstm; | |
f479c0ba BS |
3394 | int ret, i; |
3395 | u8 dpcd; | |
3396 | ||
3397 | /* This is a workaround for some monitors not functioning | |
3398 | * correctly in MST mode on initial module load. I think | |
3399 | * some bad interaction with the VBIOS may be responsible. | |
3400 | * | |
3401 | * A good ol' off and on again seems to work here ;) | |
3402 | */ | |
3403 | ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); | |
3404 | if (ret >= 0 && dpcd >= 0x12) | |
3405 | drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); | |
52aa30f2 BS |
3406 | |
3407 | if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) | |
3408 | return -ENOMEM; | |
3409 | mstm->outp = outp; | |
f479c0ba | 3410 | mstm->mgr.cbs = &nv50_mstm; |
52aa30f2 | 3411 | |
7b0a89a6 | 3412 | ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, |
52aa30f2 BS |
3413 | max_payloads, conn_base_id); |
3414 | if (ret) | |
3415 | return ret; | |
3416 | ||
f479c0ba BS |
3417 | for (i = 0; i < max_payloads; i++) { |
3418 | ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, | |
3419 | i, &mstm->msto[i]); | |
3420 | if (ret) | |
3421 | return ret; | |
3422 | } | |
3423 | ||
52aa30f2 BS |
3424 | return 0; |
3425 | } | |
3426 | ||
26f6d88b BS |
3427 | /****************************************************************************** |
3428 | * SOR | |
3429 | *****************************************************************************/ | |
4cbb0f8d | 3430 | static void |
d665c7e9 BS |
3431 | nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, |
3432 | struct drm_display_mode *mode, u8 proto, u8 depth) | |
4cbb0f8d | 3433 | { |
d665c7e9 BS |
3434 | struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base; |
3435 | u32 *push; | |
3436 | ||
3437 | if (!mode) { | |
3438 | nv_encoder->ctrl &= ~BIT(head); | |
3439 | if (!(nv_encoder->ctrl & 0x0000000f)) | |
3440 | nv_encoder->ctrl = 0; | |
3441 | } else { | |
3442 | nv_encoder->ctrl |= proto << 8; | |
3443 | nv_encoder->ctrl |= BIT(head); | |
3444 | } | |
3445 | ||
3446 | if ((push = evo_wait(core, 6))) { | |
3447 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
3448 | if (mode) { | |
3449 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
3450 | nv_encoder->ctrl |= 0x00001000; | |
3451 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
3452 | nv_encoder->ctrl |= 0x00002000; | |
3453 | nv_encoder->ctrl |= depth << 16; | |
3454 | } | |
e84a35a8 | 3455 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); |
e84a35a8 | 3456 | } else { |
d665c7e9 BS |
3457 | if (mode) { |
3458 | u32 magic = 0x31ec6000 | (head << 25); | |
3459 | u32 syncs = 0x00000001; | |
3460 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
3461 | syncs |= 0x00000008; | |
3462 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
3463 | syncs |= 0x00000010; | |
3464 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
3465 | magic |= 0x00000001; | |
3466 | ||
3467 | evo_mthd(push, 0x0404 + (head * 0x300), 2); | |
3468 | evo_data(push, syncs | (depth << 6)); | |
3469 | evo_data(push, magic); | |
3470 | } | |
e84a35a8 | 3471 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); |
4cbb0f8d | 3472 | } |
d665c7e9 BS |
3473 | evo_data(push, nv_encoder->ctrl); |
3474 | evo_kick(push, core); | |
4cbb0f8d | 3475 | } |
e84a35a8 BS |
3476 | } |
3477 | ||
3478 | static void | |
839ca903 | 3479 | nv50_sor_disable(struct drm_encoder *encoder) |
e84a35a8 BS |
3480 | { |
3481 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
3482 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
419e8dc0 | 3483 | |
419e8dc0 | 3484 | nv_encoder->crtc = NULL; |
e84a35a8 BS |
3485 | |
3486 | if (nv_crtc) { | |
839ca903 BS |
3487 | struct nvkm_i2c_aux *aux = nv_encoder->aux; |
3488 | u8 pwr; | |
3489 | ||
3490 | if (aux) { | |
3491 | int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); | |
3492 | if (ret == 0) { | |
3493 | pwr &= ~DP_SET_POWER_MASK; | |
3494 | pwr |= DP_SET_POWER_D3; | |
3495 | nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); | |
3496 | } | |
3497 | } | |
3498 | ||
d665c7e9 | 3499 | nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); |
f20c665c BS |
3500 | nv50_audio_disable(encoder, nv_crtc); |
3501 | nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); | |
6c22ea37 | 3502 | nv50_outp_release(nv_encoder); |
e84a35a8 | 3503 | } |
4cbb0f8d BS |
3504 | } |
3505 | ||
83fc083c | 3506 | static void |
839ca903 | 3507 | nv50_sor_enable(struct drm_encoder *encoder) |
83fc083c | 3508 | { |
a3761fa2 BS |
3509 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
3510 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
839ca903 | 3511 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
a3761fa2 BS |
3512 | struct { |
3513 | struct nv50_disp_mthd_v1 base; | |
3514 | struct nv50_disp_sor_lvds_script_v0 lvds; | |
3515 | } lvds = { | |
3516 | .base.version = 1, | |
3517 | .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, | |
3518 | .base.hasht = nv_encoder->dcb->hasht, | |
3519 | .base.hashm = nv_encoder->dcb->hashm, | |
3520 | }; | |
e225f446 | 3521 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
78951d22 | 3522 | struct drm_device *dev = encoder->dev; |
77145f1c | 3523 | struct nouveau_drm *drm = nouveau_drm(dev); |
3b6d83d1 | 3524 | struct nouveau_connector *nv_connector; |
77145f1c | 3525 | struct nvbios *bios = &drm->vbios; |
419e8dc0 BS |
3526 | u8 proto = 0xf; |
3527 | u8 depth = 0x0; | |
83fc083c | 3528 | |
3b6d83d1 | 3529 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
e84a35a8 | 3530 | nv_encoder->crtc = encoder->crtc; |
6c22ea37 | 3531 | nv50_outp_acquire(nv_encoder); |
e84a35a8 | 3532 | |
3b6d83d1 | 3533 | switch (nv_encoder->dcb->type) { |
cb75d97e | 3534 | case DCB_OUTPUT_TMDS: |
6c22ea37 | 3535 | if (nv_encoder->link & 1) { |
16ef53a9 HM |
3536 | proto = 0x1; |
3537 | /* Only enable dual-link if: | |
3538 | * - Need to (i.e. rate > 165MHz) | |
3539 | * - DCB says we can | |
3540 | * - Not an HDMI monitor, since there's no dual-link | |
3541 | * on HDMI. | |
3542 | */ | |
3543 | if (mode->clock >= 165000 && | |
3544 | nv_encoder->dcb->duallink_possible && | |
3545 | !drm_detect_hdmi_monitor(nv_connector->edid)) | |
3546 | proto |= 0x4; | |
3b6d83d1 | 3547 | } else { |
419e8dc0 | 3548 | proto = 0x2; |
3b6d83d1 BS |
3549 | } |
3550 | ||
f20c665c | 3551 | nv50_hdmi_enable(&nv_encoder->base.base, mode); |
3b6d83d1 | 3552 | break; |
cb75d97e | 3553 | case DCB_OUTPUT_LVDS: |
419e8dc0 BS |
3554 | proto = 0x0; |
3555 | ||
3b6d83d1 BS |
3556 | if (bios->fp_no_ddc) { |
3557 | if (bios->fp.dual_link) | |
a3761fa2 | 3558 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 3559 | if (bios->fp.if_is_24bit) |
a3761fa2 | 3560 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 3561 | } else { |
befb51e9 | 3562 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 | 3563 | if (((u8 *)nv_connector->edid)[121] == 2) |
a3761fa2 | 3564 | lvds.lvds.script |= 0x0100; |
3b6d83d1 BS |
3565 | } else |
3566 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
a3761fa2 | 3567 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 3568 | } |
83fc083c | 3569 | |
a3761fa2 | 3570 | if (lvds.lvds.script & 0x0100) { |
3b6d83d1 | 3571 | if (bios->fp.strapless_is_24bit & 2) |
a3761fa2 | 3572 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
3573 | } else { |
3574 | if (bios->fp.strapless_is_24bit & 1) | |
a3761fa2 | 3575 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
3576 | } |
3577 | ||
3578 | if (nv_connector->base.display_info.bpc == 8) | |
a3761fa2 | 3579 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 3580 | } |
4a230fa6 | 3581 | |
a3761fa2 | 3582 | nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); |
3b6d83d1 | 3583 | break; |
cb75d97e | 3584 | case DCB_OUTPUT_DP: |
f20c665c | 3585 | if (nv_connector->base.display_info.bpc == 6) |
419e8dc0 | 3586 | depth = 0x2; |
f20c665c BS |
3587 | else |
3588 | if (nv_connector->base.display_info.bpc == 8) | |
419e8dc0 | 3589 | depth = 0x5; |
f20c665c | 3590 | else |
bf2c886a | 3591 | depth = 0x6; |
6e83fda2 | 3592 | |
6c22ea37 | 3593 | if (nv_encoder->link & 1) |
419e8dc0 | 3594 | proto = 0x8; |
6e83fda2 | 3595 | else |
419e8dc0 | 3596 | proto = 0x9; |
f20c665c BS |
3597 | |
3598 | nv50_audio_enable(encoder, mode); | |
6e83fda2 | 3599 | break; |
3b6d83d1 | 3600 | default: |
af7db03e | 3601 | BUG(); |
3b6d83d1 BS |
3602 | break; |
3603 | } | |
ff8ff503 | 3604 | |
d665c7e9 | 3605 | nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth); |
83fc083c BS |
3606 | } |
3607 | ||
f20c665c BS |
3608 | static const struct drm_encoder_helper_funcs |
3609 | nv50_sor_help = { | |
839ca903 BS |
3610 | .atomic_check = nv50_outp_atomic_check, |
3611 | .enable = nv50_sor_enable, | |
3612 | .disable = nv50_sor_disable, | |
f20c665c BS |
3613 | }; |
3614 | ||
83fc083c | 3615 | static void |
e225f446 | 3616 | nv50_sor_destroy(struct drm_encoder *encoder) |
83fc083c | 3617 | { |
52aa30f2 BS |
3618 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
3619 | nv50_mstm_del(&nv_encoder->dp.mstm); | |
83fc083c BS |
3620 | drm_encoder_cleanup(encoder); |
3621 | kfree(encoder); | |
3622 | } | |
3623 | ||
f20c665c BS |
3624 | static const struct drm_encoder_funcs |
3625 | nv50_sor_func = { | |
e225f446 | 3626 | .destroy = nv50_sor_destroy, |
83fc083c BS |
3627 | }; |
3628 | ||
3629 | static int | |
e225f446 | 3630 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
83fc083c | 3631 | { |
52aa30f2 | 3632 | struct nouveau_connector *nv_connector = nouveau_connector(connector); |
5ed50209 | 3633 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1167c6bc | 3634 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); |
83fc083c BS |
3635 | struct nouveau_encoder *nv_encoder; |
3636 | struct drm_encoder *encoder; | |
52aa30f2 | 3637 | int type, ret; |
5ed50209 BS |
3638 | |
3639 | switch (dcbe->type) { | |
3640 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; | |
3641 | case DCB_OUTPUT_TMDS: | |
3642 | case DCB_OUTPUT_DP: | |
3643 | default: | |
3644 | type = DRM_MODE_ENCODER_TMDS; | |
3645 | break; | |
3646 | } | |
83fc083c BS |
3647 | |
3648 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
3649 | if (!nv_encoder) | |
3650 | return -ENOMEM; | |
3651 | nv_encoder->dcb = dcbe; | |
d665c7e9 | 3652 | nv_encoder->update = nv50_sor_update; |
83fc083c | 3653 | |
52aa30f2 BS |
3654 | encoder = to_drm_encoder(nv_encoder); |
3655 | encoder->possible_crtcs = dcbe->heads; | |
3656 | encoder->possible_clones = 0; | |
5a223dac BS |
3657 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, |
3658 | "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); | |
f20c665c | 3659 | drm_encoder_helper_add(encoder, &nv50_sor_help); |
52aa30f2 BS |
3660 | |
3661 | drm_mode_connector_attach_encoder(connector, encoder); | |
3662 | ||
2aa5eac5 | 3663 | if (dcbe->type == DCB_OUTPUT_DP) { |
13a86519 | 3664 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
2aa5eac5 BS |
3665 | struct nvkm_i2c_aux *aux = |
3666 | nvkm_i2c_aux_find(i2c, dcbe->i2c_index); | |
3667 | if (aux) { | |
13a86519 BS |
3668 | if (disp->disp->oclass < GF110_DISP) { |
3669 | /* HW has no support for address-only | |
3670 | * transactions, so we're required to | |
3671 | * use custom I2C-over-AUX code. | |
3672 | */ | |
3673 | nv_encoder->i2c = &aux->i2c; | |
3674 | } else { | |
3675 | nv_encoder->i2c = &nv_connector->aux.ddc; | |
3676 | } | |
2aa5eac5 BS |
3677 | nv_encoder->aux = aux; |
3678 | } | |
52aa30f2 BS |
3679 | |
3680 | /*TODO: Use DP Info Table to check for support. */ | |
13a86519 | 3681 | if (disp->disp->oclass >= GF110_DISP) { |
52aa30f2 BS |
3682 | ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, |
3683 | nv_connector->base.base.id, | |
3684 | &nv_encoder->dp.mstm); | |
3685 | if (ret) | |
3686 | return ret; | |
3687 | } | |
2aa5eac5 BS |
3688 | } else { |
3689 | struct nvkm_i2c_bus *bus = | |
3690 | nvkm_i2c_bus_find(i2c, dcbe->i2c_index); | |
3691 | if (bus) | |
3692 | nv_encoder->i2c = &bus->i2c; | |
3693 | } | |
3694 | ||
83fc083c BS |
3695 | return 0; |
3696 | } | |
26f6d88b | 3697 | |
eb6313ad BS |
3698 | /****************************************************************************** |
3699 | * PIOR | |
3700 | *****************************************************************************/ | |
839ca903 BS |
3701 | static int |
3702 | nv50_pior_atomic_check(struct drm_encoder *encoder, | |
3703 | struct drm_crtc_state *crtc_state, | |
3704 | struct drm_connector_state *conn_state) | |
eb6313ad | 3705 | { |
839ca903 BS |
3706 | int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); |
3707 | if (ret) | |
3708 | return ret; | |
3709 | crtc_state->adjusted_mode.clock *= 2; | |
3710 | return 0; | |
eb6313ad BS |
3711 | } |
3712 | ||
3713 | static void | |
839ca903 | 3714 | nv50_pior_disable(struct drm_encoder *encoder) |
eb6313ad | 3715 | { |
f20c665c BS |
3716 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
3717 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
3718 | const int or = nv_encoder->or; | |
3719 | u32 *push; | |
3720 | ||
3721 | if (nv_encoder->crtc) { | |
f20c665c BS |
3722 | push = evo_wait(mast, 4); |
3723 | if (push) { | |
3724 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { | |
3725 | evo_mthd(push, 0x0700 + (or * 0x040), 1); | |
3726 | evo_data(push, 0x00000000); | |
3727 | } | |
3728 | evo_kick(push, mast); | |
3729 | } | |
3730 | } | |
3731 | ||
3732 | nv_encoder->crtc = NULL; | |
6c22ea37 | 3733 | nv50_outp_release(nv_encoder); |
eb6313ad BS |
3734 | } |
3735 | ||
3736 | static void | |
839ca903 | 3737 | nv50_pior_enable(struct drm_encoder *encoder) |
eb6313ad BS |
3738 | { |
3739 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
3740 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
3741 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
3742 | struct nouveau_connector *nv_connector; | |
839ca903 | 3743 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
eb6313ad BS |
3744 | u8 owner = 1 << nv_crtc->index; |
3745 | u8 proto, depth; | |
3746 | u32 *push; | |
3747 | ||
6c22ea37 BS |
3748 | nv50_outp_acquire(nv_encoder); |
3749 | ||
eb6313ad BS |
3750 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
3751 | switch (nv_connector->base.display_info.bpc) { | |
3752 | case 10: depth = 0x6; break; | |
3753 | case 8: depth = 0x5; break; | |
3754 | case 6: depth = 0x2; break; | |
3755 | default: depth = 0x0; break; | |
3756 | } | |
3757 | ||
3758 | switch (nv_encoder->dcb->type) { | |
3759 | case DCB_OUTPUT_TMDS: | |
3760 | case DCB_OUTPUT_DP: | |
3761 | proto = 0x0; | |
3762 | break; | |
3763 | default: | |
af7db03e | 3764 | BUG(); |
eb6313ad BS |
3765 | break; |
3766 | } | |
3767 | ||
eb6313ad BS |
3768 | push = evo_wait(mast, 8); |
3769 | if (push) { | |
648d4dfd | 3770 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
3771 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
3772 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
3773 | ctrl |= 0x00001000; | |
3774 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
3775 | ctrl |= 0x00002000; | |
3776 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); | |
3777 | evo_data(push, ctrl); | |
3778 | } | |
3779 | ||
3780 | evo_kick(push, mast); | |
3781 | } | |
3782 | ||
3783 | nv_encoder->crtc = encoder->crtc; | |
3784 | } | |
3785 | ||
f20c665c BS |
3786 | static const struct drm_encoder_helper_funcs |
3787 | nv50_pior_help = { | |
839ca903 BS |
3788 | .atomic_check = nv50_pior_atomic_check, |
3789 | .enable = nv50_pior_enable, | |
3790 | .disable = nv50_pior_disable, | |
eb6313ad BS |
3791 | }; |
3792 | ||
f20c665c BS |
3793 | static void |
3794 | nv50_pior_destroy(struct drm_encoder *encoder) | |
3795 | { | |
3796 | drm_encoder_cleanup(encoder); | |
3797 | kfree(encoder); | |
3798 | } | |
3799 | ||
3800 | static const struct drm_encoder_funcs | |
3801 | nv50_pior_func = { | |
eb6313ad BS |
3802 | .destroy = nv50_pior_destroy, |
3803 | }; | |
3804 | ||
3805 | static int | |
3806 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) | |
3807 | { | |
df8dc97c | 3808 | struct nouveau_connector *nv_connector = nouveau_connector(connector); |
eb6313ad | 3809 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1167c6bc | 3810 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); |
2aa5eac5 BS |
3811 | struct nvkm_i2c_bus *bus = NULL; |
3812 | struct nvkm_i2c_aux *aux = NULL; | |
3813 | struct i2c_adapter *ddc; | |
eb6313ad BS |
3814 | struct nouveau_encoder *nv_encoder; |
3815 | struct drm_encoder *encoder; | |
3816 | int type; | |
3817 | ||
3818 | switch (dcbe->type) { | |
3819 | case DCB_OUTPUT_TMDS: | |
2aa5eac5 BS |
3820 | bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); |
3821 | ddc = bus ? &bus->i2c : NULL; | |
eb6313ad BS |
3822 | type = DRM_MODE_ENCODER_TMDS; |
3823 | break; | |
3824 | case DCB_OUTPUT_DP: | |
2aa5eac5 | 3825 | aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); |
df8dc97c | 3826 | ddc = aux ? &nv_connector->aux.ddc : NULL; |
eb6313ad BS |
3827 | type = DRM_MODE_ENCODER_TMDS; |
3828 | break; | |
3829 | default: | |
3830 | return -ENODEV; | |
3831 | } | |
3832 | ||
3833 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
3834 | if (!nv_encoder) | |
3835 | return -ENOMEM; | |
3836 | nv_encoder->dcb = dcbe; | |
eb6313ad | 3837 | nv_encoder->i2c = ddc; |
2aa5eac5 | 3838 | nv_encoder->aux = aux; |
eb6313ad BS |
3839 | |
3840 | encoder = to_drm_encoder(nv_encoder); | |
3841 | encoder->possible_crtcs = dcbe->heads; | |
3842 | encoder->possible_clones = 0; | |
5a223dac BS |
3843 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, |
3844 | "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); | |
f20c665c | 3845 | drm_encoder_helper_add(encoder, &nv50_pior_help); |
eb6313ad BS |
3846 | |
3847 | drm_mode_connector_attach_encoder(connector, encoder); | |
3848 | return 0; | |
3849 | } | |
3850 | ||
839ca903 BS |
3851 | /****************************************************************************** |
3852 | * Atomic | |
3853 | *****************************************************************************/ | |
3854 | ||
3855 | static void | |
3856 | nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock) | |
3857 | { | |
3858 | struct nv50_disp *disp = nv50_disp(drm->dev); | |
3859 | struct nv50_dmac *core = &disp->mast.base; | |
f479c0ba BS |
3860 | struct nv50_mstm *mstm; |
3861 | struct drm_encoder *encoder; | |
839ca903 BS |
3862 | u32 *push; |
3863 | ||
3864 | NV_ATOMIC(drm, "commit core %08x\n", interlock); | |
3865 | ||
f479c0ba BS |
3866 | drm_for_each_encoder(encoder, drm->dev) { |
3867 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { | |
3868 | mstm = nouveau_encoder(encoder)->dp.mstm; | |
3869 | if (mstm && mstm->modified) | |
3870 | nv50_mstm_prepare(mstm); | |
3871 | } | |
3872 | } | |
3873 | ||
839ca903 BS |
3874 | if ((push = evo_wait(core, 5))) { |
3875 | evo_mthd(push, 0x0084, 1); | |
3876 | evo_data(push, 0x80000000); | |
3877 | evo_mthd(push, 0x0080, 2); | |
3878 | evo_data(push, interlock); | |
3879 | evo_data(push, 0x00000000); | |
3880 | nouveau_bo_wr32(disp->sync, 0, 0x00000000); | |
3881 | evo_kick(push, core); | |
1167c6bc | 3882 | if (nvif_msec(&drm->client.device, 2000ULL, |
839ca903 BS |
3883 | if (nouveau_bo_rd32(disp->sync, 0)) |
3884 | break; | |
3885 | usleep_range(1, 2); | |
3886 | ) < 0) | |
3887 | NV_ERROR(drm, "EVO timeout\n"); | |
3888 | } | |
f479c0ba BS |
3889 | |
3890 | drm_for_each_encoder(encoder, drm->dev) { | |
3891 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { | |
3892 | mstm = nouveau_encoder(encoder)->dp.mstm; | |
3893 | if (mstm && mstm->modified) | |
3894 | nv50_mstm_cleanup(mstm); | |
3895 | } | |
3896 | } | |
839ca903 BS |
3897 | } |
3898 | ||
3899 | static void | |
3900 | nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) | |
3901 | { | |
3902 | struct drm_device *dev = state->dev; | |
efa47935 | 3903 | struct drm_crtc_state *new_crtc_state, *old_crtc_state; |
839ca903 | 3904 | struct drm_crtc *crtc; |
3c847d6c | 3905 | struct drm_plane_state *new_plane_state; |
839ca903 BS |
3906 | struct drm_plane *plane; |
3907 | struct nouveau_drm *drm = nouveau_drm(dev); | |
3908 | struct nv50_disp *disp = nv50_disp(dev); | |
3909 | struct nv50_atom *atom = nv50_atom(state); | |
3910 | struct nv50_outp_atom *outp, *outt; | |
3911 | u32 interlock_core = 0; | |
3912 | u32 interlock_chan = 0; | |
3913 | int i; | |
3914 | ||
3915 | NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); | |
3916 | drm_atomic_helper_wait_for_fences(dev, state, false); | |
3917 | drm_atomic_helper_wait_for_dependencies(state); | |
3918 | drm_atomic_helper_update_legacy_modeset_state(dev, state); | |
3919 | ||
3920 | if (atom->lock_core) | |
3921 | mutex_lock(&disp->mutex); | |
3922 | ||
3923 | /* Disable head(s). */ | |
efa47935 | 3924 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
3c847d6c | 3925 | struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); |
839ca903 BS |
3926 | struct nv50_head *head = nv50_head(crtc); |
3927 | ||
3928 | NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, | |
3929 | asyh->clr.mask, asyh->set.mask); | |
efa47935 | 3930 | if (old_crtc_state->active && !new_crtc_state->active) |
4a5431af | 3931 | drm_crtc_vblank_off(crtc); |
839ca903 BS |
3932 | |
3933 | if (asyh->clr.mask) { | |
3934 | nv50_head_flush_clr(head, asyh, atom->flush_disable); | |
3935 | interlock_core |= 1; | |
3936 | } | |
3937 | } | |
3938 | ||
3939 | /* Disable plane(s). */ | |
3c847d6c ML |
3940 | for_each_new_plane_in_state(state, plane, new_plane_state, i) { |
3941 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); | |
839ca903 BS |
3942 | struct nv50_wndw *wndw = nv50_wndw(plane); |
3943 | ||
3944 | NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, | |
3945 | asyw->clr.mask, asyw->set.mask); | |
3946 | if (!asyw->clr.mask) | |
3947 | continue; | |
3948 | ||
3949 | interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core, | |
3950 | atom->flush_disable, | |
3951 | asyw); | |
3952 | } | |
3953 | ||
3954 | /* Disable output path(s). */ | |
3955 | list_for_each_entry(outp, &atom->outp, head) { | |
3956 | const struct drm_encoder_helper_funcs *help; | |
3957 | struct drm_encoder *encoder; | |
3958 | ||
3959 | encoder = outp->encoder; | |
3960 | help = encoder->helper_private; | |
3961 | ||
3962 | NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, | |
3963 | outp->clr.mask, outp->set.mask); | |
3964 | ||
3965 | if (outp->clr.mask) { | |
3966 | help->disable(encoder); | |
3967 | interlock_core |= 1; | |
3968 | if (outp->flush_disable) { | |
3969 | nv50_disp_atomic_commit_core(drm, interlock_chan); | |
3970 | interlock_core = 0; | |
3971 | interlock_chan = 0; | |
3972 | } | |
3973 | } | |
3974 | } | |
3975 | ||
3976 | /* Flush disable. */ | |
3977 | if (interlock_core) { | |
3978 | if (atom->flush_disable) { | |
3979 | nv50_disp_atomic_commit_core(drm, interlock_chan); | |
3980 | interlock_core = 0; | |
3981 | interlock_chan = 0; | |
3982 | } | |
3983 | } | |
3984 | ||
3985 | /* Update output path(s). */ | |
3986 | list_for_each_entry_safe(outp, outt, &atom->outp, head) { | |
3987 | const struct drm_encoder_helper_funcs *help; | |
3988 | struct drm_encoder *encoder; | |
3989 | ||
3990 | encoder = outp->encoder; | |
3991 | help = encoder->helper_private; | |
3992 | ||
3993 | NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, | |
3994 | outp->set.mask, outp->clr.mask); | |
3995 | ||
3996 | if (outp->set.mask) { | |
3997 | help->enable(encoder); | |
3998 | interlock_core = 1; | |
3999 | } | |
4000 | ||
4001 | list_del(&outp->head); | |
4002 | kfree(outp); | |
4003 | } | |
4004 | ||
4005 | /* Update head(s). */ | |
efa47935 | 4006 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
3c847d6c | 4007 | struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); |
839ca903 BS |
4008 | struct nv50_head *head = nv50_head(crtc); |
4009 | ||
4010 | NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, | |
4011 | asyh->set.mask, asyh->clr.mask); | |
4012 | ||
4013 | if (asyh->set.mask) { | |
4014 | nv50_head_flush_set(head, asyh); | |
4015 | interlock_core = 1; | |
4016 | } | |
839ca903 | 4017 | |
efa47935 ML |
4018 | if (new_crtc_state->active) { |
4019 | if (!old_crtc_state->active) | |
4a5431af | 4020 | drm_crtc_vblank_on(crtc); |
efa47935 | 4021 | if (new_crtc_state->event) |
4a5431af BS |
4022 | drm_crtc_vblank_get(crtc); |
4023 | } | |
2b507893 BS |
4024 | } |
4025 | ||
839ca903 | 4026 | /* Update plane(s). */ |
3c847d6c ML |
4027 | for_each_new_plane_in_state(state, plane, new_plane_state, i) { |
4028 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); | |
839ca903 BS |
4029 | struct nv50_wndw *wndw = nv50_wndw(plane); |
4030 | ||
4031 | NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, | |
4032 | asyw->set.mask, asyw->clr.mask); | |
4033 | if ( !asyw->set.mask && | |
4034 | (!asyw->clr.mask || atom->flush_disable)) | |
4035 | continue; | |
4036 | ||
4037 | interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw); | |
4038 | } | |
4039 | ||
4040 | /* Flush update. */ | |
4041 | if (interlock_core) { | |
4042 | if (!interlock_chan && atom->state.legacy_cursor_update) { | |
4043 | u32 *push = evo_wait(&disp->mast, 2); | |
4044 | if (push) { | |
4045 | evo_mthd(push, 0x0080, 1); | |
4046 | evo_data(push, 0x00000000); | |
4047 | evo_kick(push, &disp->mast); | |
4048 | } | |
4049 | } else { | |
4050 | nv50_disp_atomic_commit_core(drm, interlock_chan); | |
4051 | } | |
4052 | } | |
4053 | ||
4054 | if (atom->lock_core) | |
4055 | mutex_unlock(&disp->mutex); | |
4056 | ||
4057 | /* Wait for HW to signal completion. */ | |
3c847d6c ML |
4058 | for_each_new_plane_in_state(state, plane, new_plane_state, i) { |
4059 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); | |
839ca903 BS |
4060 | struct nv50_wndw *wndw = nv50_wndw(plane); |
4061 | int ret = nv50_wndw_wait_armed(wndw, asyw); | |
4062 | if (ret) | |
4063 | NV_ERROR(drm, "%s: timeout\n", plane->name); | |
4064 | } | |
4065 | ||
3c847d6c ML |
4066 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
4067 | if (new_crtc_state->event) { | |
839ca903 | 4068 | unsigned long flags; |
bd9f6605 | 4069 | /* Get correct count/ts if racing with vblank irq */ |
efa47935 | 4070 | if (new_crtc_state->active) |
0c697faf | 4071 | drm_crtc_accurate_vblank_count(crtc); |
839ca903 | 4072 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
3c847d6c | 4073 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
839ca903 | 4074 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
efa47935 | 4075 | |
3c847d6c | 4076 | new_crtc_state->event = NULL; |
efa47935 | 4077 | if (new_crtc_state->active) |
4a5431af | 4078 | drm_crtc_vblank_put(crtc); |
839ca903 BS |
4079 | } |
4080 | } | |
4081 | ||
4082 | drm_atomic_helper_commit_hw_done(state); | |
4083 | drm_atomic_helper_cleanup_planes(dev, state); | |
4084 | drm_atomic_helper_commit_cleanup_done(state); | |
4085 | drm_atomic_state_put(state); | |
4086 | } | |
4087 | ||
4088 | static void | |
4089 | nv50_disp_atomic_commit_work(struct work_struct *work) | |
4090 | { | |
4091 | struct drm_atomic_state *state = | |
4092 | container_of(work, typeof(*state), commit_work); | |
4093 | nv50_disp_atomic_commit_tail(state); | |
4094 | } | |
4095 | ||
4096 | static int | |
4097 | nv50_disp_atomic_commit(struct drm_device *dev, | |
4098 | struct drm_atomic_state *state, bool nonblock) | |
4099 | { | |
4100 | struct nouveau_drm *drm = nouveau_drm(dev); | |
4101 | struct nv50_disp *disp = nv50_disp(dev); | |
d324c5bc | 4102 | struct drm_plane_state *new_plane_state; |
839ca903 BS |
4103 | struct drm_plane *plane; |
4104 | struct drm_crtc *crtc; | |
4105 | bool active = false; | |
4106 | int ret, i; | |
4107 | ||
4108 | ret = pm_runtime_get_sync(dev->dev); | |
4109 | if (ret < 0 && ret != -EACCES) | |
4110 | return ret; | |
4111 | ||
4112 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
4113 | if (ret) | |
4114 | goto done; | |
4115 | ||
4116 | INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); | |
4117 | ||
4118 | ret = drm_atomic_helper_prepare_planes(dev, state); | |
4119 | if (ret) | |
4120 | goto done; | |
4121 | ||
4122 | if (!nonblock) { | |
4123 | ret = drm_atomic_helper_wait_for_fences(dev, state, true); | |
4124 | if (ret) | |
813a7e16 | 4125 | goto err_cleanup; |
839ca903 BS |
4126 | } |
4127 | ||
8572636e ML |
4128 | ret = drm_atomic_helper_swap_state(state, true); |
4129 | if (ret) | |
4130 | goto err_cleanup; | |
4131 | ||
d324c5bc BS |
4132 | for_each_new_plane_in_state(state, plane, new_plane_state, i) { |
4133 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); | |
839ca903 | 4134 | struct nv50_wndw *wndw = nv50_wndw(plane); |
3c847d6c | 4135 | |
839ca903 BS |
4136 | if (asyw->set.image) { |
4137 | asyw->ntfy.handle = wndw->dmac->sync.handle; | |
4138 | asyw->ntfy.offset = wndw->ntfy; | |
4139 | asyw->ntfy.awaken = false; | |
4140 | asyw->set.ntfy = true; | |
4141 | nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000); | |
4142 | wndw->ntfy ^= 0x10; | |
4143 | } | |
4144 | } | |
4145 | ||
839ca903 BS |
4146 | drm_atomic_state_get(state); |
4147 | ||
4148 | if (nonblock) | |
4149 | queue_work(system_unbound_wq, &state->commit_work); | |
4150 | else | |
4151 | nv50_disp_atomic_commit_tail(state); | |
4152 | ||
4153 | drm_for_each_crtc(crtc, dev) { | |
4154 | if (crtc->state->enable) { | |
4155 | if (!drm->have_disp_power_ref) { | |
4156 | drm->have_disp_power_ref = true; | |
813a7e16 | 4157 | return 0; |
839ca903 BS |
4158 | } |
4159 | active = true; | |
4160 | break; | |
4161 | } | |
4162 | } | |
4163 | ||
4164 | if (!active && drm->have_disp_power_ref) { | |
4165 | pm_runtime_put_autosuspend(dev->dev); | |
4166 | drm->have_disp_power_ref = false; | |
4167 | } | |
4168 | ||
813a7e16 ML |
4169 | err_cleanup: |
4170 | if (ret) | |
4171 | drm_atomic_helper_cleanup_planes(dev, state); | |
839ca903 BS |
4172 | done: |
4173 | pm_runtime_put_autosuspend(dev->dev); | |
4174 | return ret; | |
4175 | } | |
4176 | ||
4177 | static struct nv50_outp_atom * | |
4178 | nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) | |
4179 | { | |
4180 | struct nv50_outp_atom *outp; | |
4181 | ||
4182 | list_for_each_entry(outp, &atom->outp, head) { | |
4183 | if (outp->encoder == encoder) | |
4184 | return outp; | |
4185 | } | |
4186 | ||
4187 | outp = kzalloc(sizeof(*outp), GFP_KERNEL); | |
4188 | if (!outp) | |
4189 | return ERR_PTR(-ENOMEM); | |
4190 | ||
4191 | list_add(&outp->head, &atom->outp); | |
4192 | outp->encoder = encoder; | |
4193 | return outp; | |
4194 | } | |
4195 | ||
4196 | static int | |
4197 | nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, | |
3c847d6c | 4198 | struct drm_connector_state *old_connector_state) |
839ca903 | 4199 | { |
3c847d6c ML |
4200 | struct drm_encoder *encoder = old_connector_state->best_encoder; |
4201 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; | |
839ca903 BS |
4202 | struct drm_crtc *crtc; |
4203 | struct nv50_outp_atom *outp; | |
4204 | ||
3c847d6c | 4205 | if (!(crtc = old_connector_state->crtc)) |
839ca903 BS |
4206 | return 0; |
4207 | ||
3c847d6c ML |
4208 | old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); |
4209 | new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); | |
4210 | if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
839ca903 BS |
4211 | outp = nv50_disp_outp_atomic_add(atom, encoder); |
4212 | if (IS_ERR(outp)) | |
4213 | return PTR_ERR(outp); | |
4214 | ||
4215 | if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { | |
4216 | outp->flush_disable = true; | |
4217 | atom->flush_disable = true; | |
4218 | } | |
4219 | outp->clr.ctrl = true; | |
4220 | atom->lock_core = true; | |
4221 | } | |
4222 | ||
4223 | return 0; | |
4224 | } | |
4225 | ||
4226 | static int | |
4227 | nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, | |
4228 | struct drm_connector_state *connector_state) | |
4229 | { | |
4230 | struct drm_encoder *encoder = connector_state->best_encoder; | |
3c847d6c | 4231 | struct drm_crtc_state *new_crtc_state; |
839ca903 BS |
4232 | struct drm_crtc *crtc; |
4233 | struct nv50_outp_atom *outp; | |
4234 | ||
4235 | if (!(crtc = connector_state->crtc)) | |
4236 | return 0; | |
4237 | ||
3c847d6c ML |
4238 | new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); |
4239 | if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
839ca903 BS |
4240 | outp = nv50_disp_outp_atomic_add(atom, encoder); |
4241 | if (IS_ERR(outp)) | |
4242 | return PTR_ERR(outp); | |
4243 | ||
4244 | outp->set.ctrl = true; | |
4245 | atom->lock_core = true; | |
4246 | } | |
4247 | ||
4248 | return 0; | |
4249 | } | |
4250 | ||
4251 | static int | |
4252 | nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) | |
4253 | { | |
4254 | struct nv50_atom *atom = nv50_atom(state); | |
3c847d6c | 4255 | struct drm_connector_state *old_connector_state, *new_connector_state; |
839ca903 BS |
4256 | struct drm_connector *connector; |
4257 | int ret, i; | |
4258 | ||
4259 | ret = drm_atomic_helper_check(dev, state); | |
4260 | if (ret) | |
4261 | return ret; | |
4262 | ||
3c847d6c ML |
4263 | for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { |
4264 | ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); | |
839ca903 BS |
4265 | if (ret) |
4266 | return ret; | |
4267 | ||
3c847d6c | 4268 | ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); |
839ca903 BS |
4269 | if (ret) |
4270 | return ret; | |
4271 | } | |
4272 | ||
4273 | return 0; | |
4274 | } | |
4275 | ||
4276 | static void | |
4277 | nv50_disp_atomic_state_clear(struct drm_atomic_state *state) | |
4278 | { | |
4279 | struct nv50_atom *atom = nv50_atom(state); | |
4280 | struct nv50_outp_atom *outp, *outt; | |
4281 | ||
4282 | list_for_each_entry_safe(outp, outt, &atom->outp, head) { | |
4283 | list_del(&outp->head); | |
4284 | kfree(outp); | |
4285 | } | |
4286 | ||
4287 | drm_atomic_state_default_clear(state); | |
4288 | } | |
4289 | ||
4290 | static void | |
4291 | nv50_disp_atomic_state_free(struct drm_atomic_state *state) | |
4292 | { | |
4293 | struct nv50_atom *atom = nv50_atom(state); | |
4294 | drm_atomic_state_default_release(&atom->state); | |
4295 | kfree(atom); | |
4296 | } | |
4297 | ||
4298 | static struct drm_atomic_state * | |
4299 | nv50_disp_atomic_state_alloc(struct drm_device *dev) | |
4300 | { | |
4301 | struct nv50_atom *atom; | |
4302 | if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || | |
4303 | drm_atomic_state_init(dev, &atom->state) < 0) { | |
4304 | kfree(atom); | |
4305 | return NULL; | |
4306 | } | |
4307 | INIT_LIST_HEAD(&atom->outp); | |
4308 | return &atom->state; | |
4309 | } | |
4310 | ||
4311 | static const struct drm_mode_config_funcs | |
4312 | nv50_disp_func = { | |
4313 | .fb_create = nouveau_user_framebuffer_create, | |
4314 | .output_poll_changed = nouveau_fbcon_output_poll_changed, | |
4315 | .atomic_check = nv50_disp_atomic_check, | |
4316 | .atomic_commit = nv50_disp_atomic_commit, | |
4317 | .atomic_state_alloc = nv50_disp_atomic_state_alloc, | |
4318 | .atomic_state_clear = nv50_disp_atomic_state_clear, | |
4319 | .atomic_state_free = nv50_disp_atomic_state_free, | |
4320 | }; | |
4321 | ||
26f6d88b BS |
4322 | /****************************************************************************** |
4323 | * Init | |
4324 | *****************************************************************************/ | |
ab0af559 | 4325 | |
2a44e499 | 4326 | void |
e225f446 | 4327 | nv50_display_fini(struct drm_device *dev) |
26f6d88b | 4328 | { |
f479c0ba BS |
4329 | struct nouveau_encoder *nv_encoder; |
4330 | struct drm_encoder *encoder; | |
973f10c2 BS |
4331 | struct drm_plane *plane; |
4332 | ||
4333 | drm_for_each_plane(plane, dev) { | |
4334 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
4335 | if (plane->funcs != &nv50_wndw) | |
4336 | continue; | |
4337 | nv50_wndw_fini(wndw); | |
4338 | } | |
f479c0ba BS |
4339 | |
4340 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
4341 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { | |
4342 | nv_encoder = nouveau_encoder(encoder); | |
4343 | nv50_mstm_fini(nv_encoder->dp.mstm); | |
4344 | } | |
4345 | } | |
26f6d88b BS |
4346 | } |
4347 | ||
4348 | int | |
e225f446 | 4349 | nv50_display_init(struct drm_device *dev) |
26f6d88b | 4350 | { |
354d3508 | 4351 | struct drm_encoder *encoder; |
973f10c2 | 4352 | struct drm_plane *plane; |
9f9bdaaf BS |
4353 | struct drm_crtc *crtc; |
4354 | u32 *push; | |
4355 | ||
4356 | push = evo_wait(nv50_mast(dev), 32); | |
4357 | if (!push) | |
4358 | return -EBUSY; | |
4359 | ||
9f9bdaaf | 4360 | evo_mthd(push, 0x0088, 1); |
f45f55c4 | 4361 | evo_data(push, nv50_mast(dev)->base.sync.handle); |
9f9bdaaf | 4362 | evo_kick(push, nv50_mast(dev)); |
973f10c2 | 4363 | |
354d3508 BS |
4364 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
4365 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { | |
9c5753bc BS |
4366 | struct nouveau_encoder *nv_encoder = |
4367 | nouveau_encoder(encoder); | |
f479c0ba | 4368 | nv50_mstm_init(nv_encoder->dp.mstm); |
354d3508 BS |
4369 | } |
4370 | } | |
4371 | ||
e1ef6b42 | 4372 | drm_for_each_crtc(crtc, dev) { |
9bfdee9a | 4373 | nv50_head_lut_load(crtc); |
e1ef6b42 BS |
4374 | } |
4375 | ||
973f10c2 BS |
4376 | drm_for_each_plane(plane, dev) { |
4377 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
4378 | if (plane->funcs != &nv50_wndw) | |
4379 | continue; | |
4380 | nv50_wndw_init(wndw); | |
4381 | } | |
4382 | ||
9f9bdaaf | 4383 | return 0; |
26f6d88b BS |
4384 | } |
4385 | ||
4386 | void | |
e225f446 | 4387 | nv50_display_destroy(struct drm_device *dev) |
26f6d88b | 4388 | { |
e225f446 | 4389 | struct nv50_disp *disp = nv50_disp(dev); |
bdb8c212 | 4390 | |
0ad72863 | 4391 | nv50_dmac_destroy(&disp->mast.base, disp->disp); |
26f6d88b | 4392 | |
816af2f2 | 4393 | nouveau_bo_unmap(disp->sync); |
04c8c210 MS |
4394 | if (disp->sync) |
4395 | nouveau_bo_unpin(disp->sync); | |
816af2f2 | 4396 | nouveau_bo_ref(NULL, &disp->sync); |
51beb428 | 4397 | |
77145f1c | 4398 | nouveau_display(dev)->priv = NULL; |
26f6d88b BS |
4399 | kfree(disp); |
4400 | } | |
4401 | ||
839ca903 BS |
4402 | MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); |
4403 | static int nouveau_atomic = 0; | |
4404 | module_param_named(atomic, nouveau_atomic, int, 0400); | |
4405 | ||
26f6d88b | 4406 | int |
e225f446 | 4407 | nv50_display_create(struct drm_device *dev) |
26f6d88b | 4408 | { |
1167c6bc | 4409 | struct nvif_device *device = &nouveau_drm(dev)->client.device; |
77145f1c | 4410 | struct nouveau_drm *drm = nouveau_drm(dev); |
77145f1c | 4411 | struct dcb_table *dcb = &drm->vbios.dcb; |
83fc083c | 4412 | struct drm_connector *connector, *tmp; |
e225f446 | 4413 | struct nv50_disp *disp; |
cb75d97e | 4414 | struct dcb_output *dcbe; |
7c5f6a87 | 4415 | int crtcs, ret, i; |
26f6d88b BS |
4416 | |
4417 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
4418 | if (!disp) | |
4419 | return -ENOMEM; | |
77145f1c | 4420 | |
839ca903 BS |
4421 | mutex_init(&disp->mutex); |
4422 | ||
77145f1c | 4423 | nouveau_display(dev)->priv = disp; |
e225f446 BS |
4424 | nouveau_display(dev)->dtor = nv50_display_destroy; |
4425 | nouveau_display(dev)->init = nv50_display_init; | |
4426 | nouveau_display(dev)->fini = nv50_display_fini; | |
0ad72863 | 4427 | disp->disp = &nouveau_display(dev)->disp; |
839ca903 BS |
4428 | dev->mode_config.funcs = &nv50_disp_func; |
4429 | if (nouveau_atomic) | |
4430 | dev->driver->driver_features |= DRIVER_ATOMIC; | |
26f6d88b | 4431 | |
b5a794b0 | 4432 | /* small shared memory area we use for notifiers and semaphores */ |
bab7cc18 | 4433 | ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
bb6178b0 | 4434 | 0, 0x0000, NULL, NULL, &disp->sync); |
b5a794b0 | 4435 | if (!ret) { |
547ad072 | 4436 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 4437 | if (!ret) { |
b5a794b0 | 4438 | ret = nouveau_bo_map(disp->sync); |
04c8c210 MS |
4439 | if (ret) |
4440 | nouveau_bo_unpin(disp->sync); | |
4441 | } | |
b5a794b0 BS |
4442 | if (ret) |
4443 | nouveau_bo_ref(NULL, &disp->sync); | |
4444 | } | |
4445 | ||
b5a794b0 BS |
4446 | if (ret) |
4447 | goto out; | |
4448 | ||
4449 | /* allocate master evo channel */ | |
a01ca78c | 4450 | ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset, |
410f3ec6 | 4451 | &disp->mast); |
b5a794b0 BS |
4452 | if (ret) |
4453 | goto out; | |
4454 | ||
438d99e3 | 4455 | /* create crtc objects to represent the hw heads */ |
648d4dfd | 4456 | if (disp->disp->oclass >= GF110_DISP) |
eba5e56d | 4457 | crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; |
63718a07 | 4458 | else |
eba5e56d | 4459 | crtcs = 0x3; |
63718a07 | 4460 | |
eba5e56d IM |
4461 | for (i = 0; i < fls(crtcs); i++) { |
4462 | if (!(crtcs & (1 << i))) | |
4463 | continue; | |
9bfdee9a | 4464 | ret = nv50_head_create(dev, i); |
438d99e3 BS |
4465 | if (ret) |
4466 | goto out; | |
4467 | } | |
4468 | ||
83fc083c BS |
4469 | /* create encoder/connector objects based on VBIOS DCB table */ |
4470 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
4471 | connector = nouveau_connector_create(dev, dcbe->connector); | |
4472 | if (IS_ERR(connector)) | |
4473 | continue; | |
4474 | ||
eb6313ad BS |
4475 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
4476 | switch (dcbe->type) { | |
4477 | case DCB_OUTPUT_TMDS: | |
4478 | case DCB_OUTPUT_LVDS: | |
4479 | case DCB_OUTPUT_DP: | |
4480 | ret = nv50_sor_create(connector, dcbe); | |
4481 | break; | |
4482 | case DCB_OUTPUT_ANALOG: | |
4483 | ret = nv50_dac_create(connector, dcbe); | |
4484 | break; | |
4485 | default: | |
4486 | ret = -ENODEV; | |
4487 | break; | |
4488 | } | |
4489 | } else { | |
4490 | ret = nv50_pior_create(connector, dcbe); | |
83fc083c BS |
4491 | } |
4492 | ||
eb6313ad BS |
4493 | if (ret) { |
4494 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", | |
4495 | dcbe->location, dcbe->type, | |
4496 | ffs(dcbe->or) - 1, ret); | |
94f54f53 | 4497 | ret = 0; |
83fc083c BS |
4498 | } |
4499 | } | |
4500 | ||
4501 | /* cull any connectors we created that don't have an encoder */ | |
4502 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
4503 | if (connector->encoder_ids[0]) | |
4504 | continue; | |
4505 | ||
77145f1c | 4506 | NV_WARN(drm, "%s has no encoders, removing\n", |
8c6c361a | 4507 | connector->name); |
83fc083c BS |
4508 | connector->funcs->destroy(connector); |
4509 | } | |
4510 | ||
26f6d88b BS |
4511 | out: |
4512 | if (ret) | |
e225f446 | 4513 | nv50_display_destroy(dev); |
26f6d88b BS |
4514 | return ret; |
4515 | } |