[linux-block.git] / drivers / gpu / drm / nouveau / nv40_graph.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_grctx.h"
#include "nouveau_ramht.h"

static int nv40_graph_register(struct drm_device *);
static void nv40_graph_isr(struct drm_device *);

struct nouveau_channel *
nv40_graph_channel(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t inst;
	int i;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return NULL;
	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->channels.ptr[i];

		if (chan && chan->ramin_grctx &&
		    chan->ramin_grctx->pinst == inst)
			return chan;
	}

	return NULL;
}

int
nv40_graph_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_grctx ctx = {};
	unsigned long flags;
	int ret;

	ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
	if (ret)
		return ret;

	/* Initialise default context values */
	ctx.dev = chan->dev;
	ctx.mode = NOUVEAU_GRCTX_VALS;
	ctx.data = chan->ramin_grctx;
	nv40_grctx_init(&ctx);

	nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);

	/* init grctx pointer in ramfc, and on PFIFO if channel is
	 * already active there
	 */
	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);
	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
		nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);
	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	return 0;
}

void
nv40_graph_destroy_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	pgraph->fifo_access(dev, false);

	/* Unload the context if it's the currently active one */
	if (pgraph->channel(dev) == chan)
		pgraph->unload_context(dev);

	pgraph->fifo_access(dev, true);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	/* Free the context resources */
	nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
}

static int
nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
{
	uint32_t old_cp, tv = 1000, tmp;
	int i;

	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
		      NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);

	nouveau_wait_for_idle(dev);

	for (i = 0; i < tv; i++) {
		if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
			break;
	}

	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);

	if (i == tv) {
		uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
		NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
		NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
			 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
			 ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
		NV_ERROR(dev, "0x40030C = 0x%08x\n",
			 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
		return -EBUSY;
	}

	return 0;
}

/* Restore the context for a specific channel into PGRAPH */
int
nv40_graph_load_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	uint32_t inst;
	int ret;

	if (!chan->ramin_grctx)
		return -EINVAL;
	inst = chan->ramin_grctx->pinst >> 4;

	ret = nv40_graph_transfer_context(dev, inst, 0);
	if (ret)
		return ret;

	/* 0x40032C, no idea of it's exact function.  Could simply be a
	 * record of the currently active PGRAPH context.  It's currently
	 * unknown as to what bit 24 does.  The nv ddx has it set, so we will
	 * set it here too.
	 */
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
		 (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
		  NV40_PGRAPH_CTXCTL_CUR_LOADED);
	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
	 * context.  If at any time this doesn't match 0x40032C, you will
	 * receive PGRAPH_INTR_CONTEXT_SWITCH
	 */
	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
	return 0;
}

int
nv40_graph_unload_context(struct drm_device *dev)
{
	uint32_t inst;
	int ret;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return 0;
	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;

	ret = nv40_graph_transfer_context(dev, inst, 1);

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
	return ret;
}

int
nv40_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
{
	struct drm_device *dev = chan->dev;
	struct nouveau_gpuobj *obj = NULL;
	int ret;

	ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	if (ret)
		return ret;
	obj->engine = 1;
	obj->class  = class;

	nv_wo32(obj, 0x00, class);
	nv_wo32(obj, 0x04, 0x00000000);
#ifdef __BIG_ENDIAN
	nv_wo32(obj, 0x08, 0x01000000);
#endif
	nv_wo32(obj, 0x0c, 0x00000000);
	nv_wo32(obj, 0x10, 0x00000000);

	ret = nouveau_ramht_insert(chan, handle, obj);
	nouveau_gpuobj_ref(NULL, &obj);
	return ret;
}

void
nv40_graph_set_tile_region(struct drm_device *dev, int i)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x41: /* guess */
	case 0x42:
	case 0x43:
	case 0x45: /* guess */
	case 0x4e:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	case 0x44:
	case 0x4a:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
		break;
	case 0x46:
	case 0x47:
	case 0x49:
	case 0x4b:
	case 0x4c:
	case 0x67:
	default:
		nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	}
}

/*
 * G70		0x47
 * G71		0x49
 * NV45		0x48
 * G72[M]	0x46
 * G73		0x4b
 * C51_G7X	0x4c
 * C51		0x4e
 */
int
nv40_graph_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv =
		(struct drm_nouveau_private *)dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_grctx ctx = {};
	uint32_t vramsz, *cp;
	int ret, i, j;

	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
			~NV_PMC_ENABLE_PGRAPH);
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
			 NV_PMC_ENABLE_PGRAPH);

	cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
	if (!cp)
		return -ENOMEM;

	ctx.dev = dev;
	ctx.mode = NOUVEAU_GRCTX_PROG;
	ctx.data = cp;
	ctx.ctxprog_max = 256;
	nv40_grctx_init(&ctx);
	dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	for (i = 0; i < ctx.ctxprog_len; i++)
		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);

	kfree(cp);

	ret = nv40_graph_register(dev);
	if (ret)
		return ret;

	/* No context present currently */
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

	nouveau_irq_register(dev, 12, nv40_graph_isr);
	nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);

	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	j = nv_rd32(dev, 0x1540) & 0xff;
	if (j) {
		for (i = 0; !(j & 1); j >>= 1, i++)
			;
		nv_wr32(dev, 0x405000, i);
	}

	if (dev_priv->chipset == 0x40) {
		nv_wr32(dev, 0x4009b0, 0x83280fff);
		nv_wr32(dev, 0x4009b4, 0x000000a0);
	} else {
		nv_wr32(dev, 0x400820, 0x83280eff);
		nv_wr32(dev, 0x400824, 0x000000a0);
	}

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x45:
		nv_wr32(dev, 0x4009b8, 0x0078e366);
		nv_wr32(dev, 0x4009bc, 0x0000014c);
		break;
	case 0x41:
	case 0x42: /* pciid also 0x00Cx */
	/* case 0x0120: XXX (pciid) */
		nv_wr32(dev, 0x400828, 0x007596ff);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x43:
		nv_wr32(dev, 0x400828, 0x0072cb77);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x44:
	case 0x46: /* G72 */
	case 0x4a:
	case 0x4c: /* G7x-based C51 */
	case 0x4e:
		nv_wr32(dev, 0x400860, 0);
		nv_wr32(dev, 0x400864, 0);
		break;
	case 0x47: /* G70 */
	case 0x49: /* G71 */
	case 0x4b: /* G73 */
		nv_wr32(dev, 0x400828, 0x07830610);
		nv_wr32(dev, 0x40082c, 0x0000016A);
		break;
	default:
		break;
	}

	nv_wr32(dev, 0x400b38, 0x2ffff800);
	nv_wr32(dev, 0x400b3c, 0x00006000);

	/* Tiling related stuff. */
	switch (dev_priv->chipset) {
	case 0x44:
	case 0x4a:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b500);
		break;
	case 0x46:
		nv_wr32(dev, 0x400bc4, 0x0000e024);
		nv_wr32(dev, 0x400bbc, 0xb7a7b520);
		break;
	case 0x4c:
	case 0x4e:
	case 0x67:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b540);
		break;
	default:
		break;
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->num_tiles; i++)
		nv40_graph_set_tile_region(dev, i);

	/* begin RAM config */
	vramsz = pci_resource_len(dev->pdev, 0) - 1;
	switch (dev_priv->chipset) {
	case 0x40:
		nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400820, 0);
		nv_wr32(dev, 0x400824, 0);
		nv_wr32(dev, 0x400864, vramsz);
		nv_wr32(dev, 0x400868, vramsz);
		break;
	default:
		switch (dev_priv->chipset) {
		case 0x41:
		case 0x42:
		case 0x43:
		case 0x45:
		case 0x4e:
		case 0x44:
		case 0x4a:
			nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		default:
			nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		}
		nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400840, 0);
		nv_wr32(dev, 0x400844, 0);
		nv_wr32(dev, 0x4008A0, vramsz);
		nv_wr32(dev, 0x4008A4, vramsz);
		break;
	}

	return 0;
}

void nv40_graph_takedown(struct drm_device *dev)
{
	nouveau_irq_unregister(dev, 12);
}

static int
nv40_graph_register(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (dev_priv->engine.graph.registered)
		return 0;

	NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */

	/* curie */
	if (nv44_graph_class(dev))
		NVOBJ_CLASS(dev, 0x4497, GR);
	else
		NVOBJ_CLASS(dev, 0x4097, GR);

	/* nvsw */
	NVOBJ_CLASS(dev, 0x506e, SW);
	NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);

	dev_priv->engine.graph.registered = true;
	return 0;
}

static int
nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_channel *chan;
	unsigned long flags;
	int i;

	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		chan = dev_priv->channels.ptr[i];
		if (!chan || !chan->ramin_grctx)
			continue;

		if (inst == chan->ramin_grctx->pinst)
			break;
	}
	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	return i;
}

static void
nv40_graph_isr(struct drm_device *dev)
{
	u32 stat;

	while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
		u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
		u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
		u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
		u32 chid = nv40_graph_isr_chid(dev, inst);
		u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
		u32 subc = (addr & 0x00070000) >> 16;
		u32 mthd = (addr & 0x00001ffc);
		u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
		u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
		u32 show = stat;

		if (stat & NV_PGRAPH_INTR_ERROR) {
			if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
				if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
					show &= ~NV_PGRAPH_INTR_ERROR;
			} else
			if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
				nv_mask(dev, 0x402000, 0, 0);
			}
		}

		nv_wr32(dev, NV03_PGRAPH_INTR, stat);
		nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);

		if (show && nouveau_ratelimit()) {
			NV_INFO(dev, "PGRAPH -");
			nouveau_bitfield_print(nv10_graph_intr, show);
			printk(" nsource:");
			nouveau_bitfield_print(nv04_graph_nsource, nsource);
			printk(" nstatus:");
			nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
			printk("\n");
			NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
				     "class 0x%04x mthd 0x%04x data 0x%08x\n",
				chid, inst, subc, class, mthd, data);
		}
	}
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
6ee73861 BS	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
054b93e4	30	#include "nouveau_grctx.h"
4ea52f89	31	#include "nouveau_ramht.h"
6ee73861	32
b8c157d3	33	static int nv40_graph_register(struct drm_device *);
274fec93	34	static void nv40_graph_isr(struct drm_device *);
b8c157d3	35
6ee73861 BS	36	struct nouveau_channel *
	37	nv40_graph_channel(struct drm_device *dev)
	38	{
	39	struct drm_nouveau_private *dev_priv = dev->dev_private;
	40	uint32_t inst;
	41	int i;
	42
	43	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	44	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
	45	return NULL;
	46	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
	47
	48	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
cff5c133	49	struct nouveau_channel *chan = dev_priv->channels.ptr[i];
6ee73861 BS	50
6ee73861 BS	51	if (chan && chan->ramin_grctx &&
a8eaebc6	52	chan->ramin_grctx->pinst == inst)
6ee73861 BS	53	return chan;
	54	}
	55
	56	return NULL;
	57	}
	58
	59	int
	60	nv40_graph_create_context(struct nouveau_channel *chan)
	61	{
	62	struct drm_device *dev = chan->dev;
	63	struct drm_nouveau_private *dev_priv = dev->dev_private;
054b93e4	64	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
ec91db26	65	struct nouveau_grctx ctx = {};
e457acae	66	unsigned long flags;
6ee73861 BS	67	int ret;
6ee73861 BS	68
a8eaebc6 BS	69	ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
a8eaebc6 BS	70	NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
6ee73861 BS	71	if (ret)
6ee73861 BS	72	return ret;
6ee73861 BS	73
6ee73861 BS	74	/* Initialise default context values */
ec91db26 BS	75	ctx.dev = chan->dev;
ec91db26 BS	76	ctx.mode = NOUVEAU_GRCTX_VALS;
a8eaebc6	77	ctx.data = chan->ramin_grctx;
ec91db26	78	nv40_grctx_init(&ctx);
6ee73861	79
5125bfd8	80	nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
e457acae BS	81
	82	/* init grctx pointer in ramfc, and on PFIFO if channel is
	83	* already active there
	84	*/
	85	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	86	nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);
	87	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
	88	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
	89	nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);
	90	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
	91	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
6ee73861 BS	92	return 0;
	93	}
	94
	95	void
	96	nv40_graph_destroy_context(struct nouveau_channel *chan)
	97	{
3945e475 FJ	98	struct drm_device *dev = chan->dev;
	99	struct drm_nouveau_private *dev_priv = dev->dev_private;
	100	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	101	unsigned long flags;
	102
	103	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	104	pgraph->fifo_access(dev, false);
	105
	106	/* Unload the context if it's the currently active one */
	107	if (pgraph->channel(dev) == chan)
	108	pgraph->unload_context(dev);
	109
	110	pgraph->fifo_access(dev, true);
	111	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	112
	113	/* Free the context resources */
a8eaebc6	114	nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
6ee73861 BS	115	}
	116
	117	static int
	118	nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
	119	{
	120	uint32_t old_cp, tv = 1000, tmp;
	121	int i;
	122
	123	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	124	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	125
	126	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	127	tmp \|= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
	128	NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	129	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
	130
	131	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	132	tmp \|= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	133	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
	134
	135	nouveau_wait_for_idle(dev);
	136
	137	for (i = 0; i < tv; i++) {
	138	if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
	139	break;
	140	}
	141
	142	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
	143
	144	if (i == tv) {
	145	uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
	146	NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
	147	NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
	148	ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
	149	ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
	150	NV_ERROR(dev, "0x40030C = 0x%08x\n",
	151	nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
	152	return -EBUSY;
	153	}
	154
	155	return 0;
	156	}
	157
	158	/* Restore the context for a specific channel into PGRAPH */
	159	int
	160	nv40_graph_load_context(struct nouveau_channel *chan)
	161	{
	162	struct drm_device *dev = chan->dev;
	163	uint32_t inst;
	164	int ret;
	165
	166	if (!chan->ramin_grctx)
	167	return -EINVAL;
a8eaebc6	168	inst = chan->ramin_grctx->pinst >> 4;
6ee73861 BS	169
	170	ret = nv40_graph_transfer_context(dev, inst, 0);
	171	if (ret)
	172	return ret;
	173
	174	/* 0x40032C, no idea of it's exact function. Could simply be a
	175	* record of the currently active PGRAPH context. It's currently
	176	* unknown as to what bit 24 does. The nv ddx has it set, so we will
	177	* set it here too.
	178	*/
	179	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	180	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
	181	(inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) \|
	182	NV40_PGRAPH_CTXCTL_CUR_LOADED);
	183	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
	184	* context. If at any time this doesn't match 0x40032C, you will
25985edc	185	* receive PGRAPH_INTR_CONTEXT_SWITCH
6ee73861 BS	186	*/
	187	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
	188	return 0;
	189	}
	190
	191	int
	192	nv40_graph_unload_context(struct drm_device *dev)
	193	{
	194	uint32_t inst;
	195	int ret;
	196
	197	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	198	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
	199	return 0;
	200	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
	201
	202	ret = nv40_graph_transfer_context(dev, inst, 1);
	203
	204	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
	205	return ret;
	206	}
	207
4ea52f89 BS	208	int
	209	nv40_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
	210	{
	211	struct drm_device *dev = chan->dev;
	212	struct nouveau_gpuobj *obj = NULL;
	213	int ret;
	214
	215	ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	216	if (ret)
	217	return ret;
	218	obj->engine = 1;
	219	obj->class = class;
	220
	221	nv_wo32(obj, 0x00, class);
	222	nv_wo32(obj, 0x04, 0x00000000);
	223	#ifdef __BIG_ENDIAN
	224	nv_wo32(obj, 0x08, 0x01000000);
	225	#endif
	226	nv_wo32(obj, 0x0c, 0x00000000);
	227	nv_wo32(obj, 0x10, 0x00000000);
	228
	229	ret = nouveau_ramht_insert(chan, handle, obj);
	230	nouveau_gpuobj_ref(NULL, &obj);
	231	return ret;
	232	}
	233
0d87c100	234	void
a5cf68b0	235	nv40_graph_set_tile_region(struct drm_device *dev, int i)
0d87c100 FJ	236	{
0d87c100 FJ	237	struct drm_nouveau_private *dev_priv = dev->dev_private;
a5cf68b0	238	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
0d87c100 FJ	239
0d87c100 FJ	240	switch (dev_priv->chipset) {
1dc32671 BS	241	case 0x40:
	242	case 0x41: /* guess */
	243	case 0x42:
	244	case 0x43:
	245	case 0x45: /* guess */
	246	case 0x4e:
	247	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
	248	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
	249	nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
	250	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	251	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	252	nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
	253	break;
0d87c100 FJ	254	case 0x44:
0d87c100 FJ	255	case 0x4a:
a5cf68b0 FJ	256	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
	257	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
	258	nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
0d87c100	259	break;
0d87c100 FJ	260	case 0x46:
	261	case 0x47:
	262	case 0x49:
	263	case 0x4b:
1dc32671 BS	264	case 0x4c:
	265	case 0x67:
	266	default:
a5cf68b0 FJ	267	nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
	268	nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
	269	nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
	270	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	271	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	272	nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
0d87c100	273	break;
0d87c100 FJ	274	}
	275	}
	276
6ee73861 BS	277	/*
	278	* G70 0x47
	279	* G71 0x49
	280	* NV45 0x48
	281	* G72[M] 0x46
	282	* G73 0x4b
	283	* C51_G7X 0x4c
	284	* C51 0x4e
	285	*/
	286	int
	287	nv40_graph_init(struct drm_device *dev)
	288	{
	289	struct drm_nouveau_private *dev_priv =
	290	(struct drm_nouveau_private *)dev->dev_private;
0d87c100	291	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
ec91db26 BS	292	struct nouveau_grctx ctx = {};
ec91db26 BS	293	uint32_t vramsz, *cp;
b8c157d3	294	int ret, i, j;
6ee73861 BS	295
	296	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
	297	~NV_PMC_ENABLE_PGRAPH);
	298	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	299	NV_PMC_ENABLE_PGRAPH);
	300
ec91db26 BS	301	cp = kmalloc(sizeof(cp) 256, GFP_KERNEL);
	302	if (!cp)
	303	return -ENOMEM;
054b93e4	304
ec91db26 BS	305	ctx.dev = dev;
	306	ctx.mode = NOUVEAU_GRCTX_PROG;
	307	ctx.data = cp;
	308	ctx.ctxprog_max = 256;
	309	nv40_grctx_init(&ctx);
	310	dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
054b93e4	311
ec91db26 BS	312	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	313	for (i = 0; i < ctx.ctxprog_len; i++)
	314	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
f49d273d	315
ec91db26	316	kfree(cp);
6ee73861	317
b8c157d3 BS	318	ret = nv40_graph_register(dev);
	319	if (ret)
	320	return ret;
	321
6ee73861 BS	322	/* No context present currently */
	323	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
	324
274fec93	325	nouveau_irq_register(dev, 12, nv40_graph_isr);
6ee73861 BS	326	nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
	327	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
	328
	329	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	330	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	331	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	332	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	333	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	334	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
	335
	336	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	337	nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
	338
	339	j = nv_rd32(dev, 0x1540) & 0xff;
	340	if (j) {
	341	for (i = 0; !(j & 1); j >>= 1, i++)
	342	;
	343	nv_wr32(dev, 0x405000, i);
	344	}
	345
	346	if (dev_priv->chipset == 0x40) {
	347	nv_wr32(dev, 0x4009b0, 0x83280fff);
	348	nv_wr32(dev, 0x4009b4, 0x000000a0);
	349	} else {
	350	nv_wr32(dev, 0x400820, 0x83280eff);
	351	nv_wr32(dev, 0x400824, 0x000000a0);
	352	}
	353
	354	switch (dev_priv->chipset) {
	355	case 0x40:
	356	case 0x45:
	357	nv_wr32(dev, 0x4009b8, 0x0078e366);
	358	nv_wr32(dev, 0x4009bc, 0x0000014c);
	359	break;
	360	case 0x41:
	361	case 0x42: /* pciid also 0x00Cx */
	362	/* case 0x0120: XXX (pciid) */
	363	nv_wr32(dev, 0x400828, 0x007596ff);
	364	nv_wr32(dev, 0x40082c, 0x00000108);
	365	break;
	366	case 0x43:
	367	nv_wr32(dev, 0x400828, 0x0072cb77);
	368	nv_wr32(dev, 0x40082c, 0x00000108);
	369	break;
	370	case 0x44:
	371	case 0x46: /* G72 */
	372	case 0x4a:
	373	case 0x4c: /* G7x-based C51 */
	374	case 0x4e:
	375	nv_wr32(dev, 0x400860, 0);
	376	nv_wr32(dev, 0x400864, 0);
	377	break;
	378	case 0x47: /* G70 */
	379	case 0x49: /* G71 */
	380	case 0x4b: /* G73 */
	381	nv_wr32(dev, 0x400828, 0x07830610);
	382	nv_wr32(dev, 0x40082c, 0x0000016A);
	383	break;
	384	default:
	385	break;
	386	}
	387
	388	nv_wr32(dev, 0x400b38, 0x2ffff800);
	389	nv_wr32(dev, 0x400b3c, 0x00006000);
390
2295e17a FJ	391	/* Tiling related stuff. */
	392	switch (dev_priv->chipset) {
	393	case 0x44:
	394	case 0x4a:
	395	nv_wr32(dev, 0x400bc4, 0x1003d888);
	396	nv_wr32(dev, 0x400bbc, 0xb7a7b500);
	397	break;
	398	case 0x46:
	399	nv_wr32(dev, 0x400bc4, 0x0000e024);
	400	nv_wr32(dev, 0x400bbc, 0xb7a7b520);
	401	break;
	402	case 0x4c:
	403	case 0x4e:
	404	case 0x67:
	405	nv_wr32(dev, 0x400bc4, 0x1003d888);
	406	nv_wr32(dev, 0x400bbc, 0xb7a7b540);
	407	break;
	408	default:
	409	break;
	410	}
	411
0d87c100 FJ	412	/* Turn all the tiling regions off. */
0d87c100 FJ	413	for (i = 0; i < pfb->num_tiles; i++)
a5cf68b0	414	nv40_graph_set_tile_region(dev, i);
6ee73861 BS	415
6ee73861 BS	416	/* begin RAM config */
01d73a69	417	vramsz = pci_resource_len(dev->pdev, 0) - 1;
6ee73861 BS	418	switch (dev_priv->chipset) {
	419	case 0x40:
	420	nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
	421	nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
	422	nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
	423	nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
	424	nv_wr32(dev, 0x400820, 0);
	425	nv_wr32(dev, 0x400824, 0);
	426	nv_wr32(dev, 0x400864, vramsz);
	427	nv_wr32(dev, 0x400868, vramsz);
	428	break;
	429	default:
	430	switch (dev_priv->chipset) {
1dc32671 BS	431	case 0x41:
	432	case 0x42:
	433	case 0x43:
	434	case 0x45:
	435	case 0x4e:
	436	case 0x44:
	437	case 0x4a:
6ee73861 BS	438	nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
	439	nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
	440	break;
1dc32671 BS	441	default:
	442	nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
	443	nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
	444	break;
6ee73861 BS	445	}
	446	nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
	447	nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
	448	nv_wr32(dev, 0x400840, 0);
	449	nv_wr32(dev, 0x400844, 0);
	450	nv_wr32(dev, 0x4008A0, vramsz);
	451	nv_wr32(dev, 0x4008A4, vramsz);
	452	break;
	453	}
	454
	455	return 0;
	456	}
	457
	458	void nv40_graph_takedown(struct drm_device *dev)
	459	{
274fec93	460	nouveau_irq_unregister(dev, 12);
6ee73861 BS	461	}
6ee73861 BS	462
b8c157d3 BS	463	static int
	464	nv40_graph_register(struct drm_device *dev)
	465	{
	466	struct drm_nouveau_private *dev_priv = dev->dev_private;
	467
	468	if (dev_priv->engine.graph.registered)
	469	return 0;
6ee73861	470
b8c157d3 BS	471	NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
	472	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	473	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	474	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	475	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	476	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	477	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	478	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	479	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	480	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	481	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	482	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	483	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	484	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	485	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	486	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
	487
	488	/* curie */
c693931d	489	if (nv44_graph_class(dev))
b8c157d3 BS	490	NVOBJ_CLASS(dev, 0x4497, GR);
	491	else
	492	NVOBJ_CLASS(dev, 0x4097, GR);
	493
332b242f FJ	494	/* nvsw */
	495	NVOBJ_CLASS(dev, 0x506e, SW);
	496	NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
	497
b8c157d3 BS	498	dev_priv->engine.graph.registered = true;
	499	return 0;
	500	}
274fec93 BS	501
	502	static int
	503	nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
	504	{
	505	struct drm_nouveau_private *dev_priv = dev->dev_private;
	506	struct nouveau_channel *chan;
	507	unsigned long flags;
	508	int i;
	509
	510	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	511	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
	512	chan = dev_priv->channels.ptr[i];
	513	if (!chan \|\| !chan->ramin_grctx)
	514	continue;
	515
	516	if (inst == chan->ramin_grctx->pinst)
	517	break;
	518	}
	519	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	520	return i;
	521	}
	522
	523	static void
	524	nv40_graph_isr(struct drm_device *dev)
	525	{
	526	u32 stat;
	527
	528	while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
	529	u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
	530	u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
	531	u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
	532	u32 chid = nv40_graph_isr_chid(dev, inst);
	533	u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
	534	u32 subc = (addr & 0x00070000) >> 16;
	535	u32 mthd = (addr & 0x00001ffc);
	536	u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
	537	u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
	538	u32 show = stat;
	539
	540	if (stat & NV_PGRAPH_INTR_ERROR) {
	541	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
	542	if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
	543	show &= ~NV_PGRAPH_INTR_ERROR;
	544	} else
	545	if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
	546	nv_mask(dev, 0x402000, 0, 0);
	547	}
	548	}
	549
	550	nv_wr32(dev, NV03_PGRAPH_INTR, stat);
	551	nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
	552
	553	if (show && nouveau_ratelimit()) {
	554	NV_INFO(dev, "PGRAPH -");
	555	nouveau_bitfield_print(nv10_graph_intr, show);
	556	printk(" nsource:");
	557	nouveau_bitfield_print(nv04_graph_nsource, nsource);
	558	printk(" nstatus:");
	559	nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
	560	printk("\n");
	561	NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
	562	"class 0x%04x mthd 0x%04x data 0x%08x\n",
	563	chid, inst, subc, class, mthd, data);
	564	}
565	}
566	}