[linux-block.git] / drivers / gpu / drm / nouveau / nv40_fifo.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"

#define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV40_RAMFC__SIZE))
#define NV40_RAMFC__SIZE 128

int
nv40_fifo_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t fc = NV40_RAMFC(chan->id);
	unsigned long flags;
	int ret;

	ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,
				      NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
				      NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
	if (ret)
		return ret;

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);

	nv_wi32(dev, fc +  0, chan->pushbuf_base);
	nv_wi32(dev, fc +  4, chan->pushbuf_base);
	nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
	nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
			      NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
			      NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
			      NV_PFIFO_CACHE1_BIG_ENDIAN |
#endif
			      0x30000000 /* no idea.. */);
	nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4);
	nv_wi32(dev, fc + 60, 0x0001FFFF);

	/* enable the fifo dma operation */
	nv_wr32(dev, NV04_PFIFO_MODE,
		nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));

	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	return 0;
}

void
nv40_fifo_destroy_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;

	nv_wr32(dev, NV04_PFIFO_MODE,
		nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));

	nouveau_gpuobj_ref(NULL, &chan->ramfc);
}

static void
nv40_fifo_do_load_context(struct drm_device *dev, int chid)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t fc = NV40_RAMFC(chid), tmp, tmp2;

	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
	nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, nv_ri32(dev, fc + 12));
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, nv_ri32(dev, fc + 16));
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 20));

	/* No idea what 0x2058 is.. */
	tmp   = nv_ri32(dev, fc + 24);
	tmp2  = nv_rd32(dev, 0x2058) & 0xFFF;
	tmp2 |= (tmp & 0x30000000);
	nv_wr32(dev, 0x2058, tmp2);
	tmp  &= ~0x30000000;
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, tmp);

	nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 28));
	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 32));
	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 36));
	tmp = nv_ri32(dev, fc + 40);
	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 44));
	nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 48));
	nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 52));
	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, nv_ri32(dev, fc + 56));

	/* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
	tmp  = nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
	tmp |= nv_ri32(dev, fc + 60) & 0x1FFFF;
	nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, tmp);

	nv_wr32(dev, 0x32e4, nv_ri32(dev, fc + 64));
	/* NVIDIA does this next line twice... */
	nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68));
	nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76));
	nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80));

	nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
}

int
nv40_fifo_load_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	uint32_t tmp;

	nv40_fifo_do_load_context(dev, chan->id);

	/* Set channel active, and in DMA mode */
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
		     NV40_PFIFO_CACHE1_PUSH1_DMA | chan->id);
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);

	/* Reset DMA_CTL_AT_INFO to INVALID */
	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);

	return 0;
}

int
nv40_fifo_unload_context(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	uint32_t fc, tmp;
	int chid;

	chid = pfifo->channel_id(dev);
	if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
		return 0;
	fc = NV40_RAMFC(chid);

	nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
	nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
	nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
	nv_wi32(dev, fc + 12, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE));
	nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT));
	nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
	tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH);
	tmp |= nv_rd32(dev, 0x2058) & 0x30000000;
	nv_wi32(dev, fc + 24, tmp);
	nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
	nv_wi32(dev, fc + 32, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
	nv_wi32(dev, fc + 36, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
	tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
	nv_wi32(dev, fc + 40, tmp);
	nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
	nv_wi32(dev, fc + 48, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
	/* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
	 * more involved depending on the value of 0x3228?
	 */
	nv_wi32(dev, fc + 52, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
	nv_wi32(dev, fc + 56, nv_rd32(dev, NV40_PFIFO_GRCTX_INSTANCE));
	nv_wi32(dev, fc + 60, nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & 0x1ffff);
	/* No idea what the below is for exactly, ripped from a mmio-trace */
	nv_wi32(dev, fc + 64, nv_rd32(dev, NV40_PFIFO_UNK32E4));
	/* NVIDIA do this next line twice.. bug? */
	nv_wi32(dev, fc + 68, nv_rd32(dev, 0x32e8));
	nv_wi32(dev, fc + 76, nv_rd32(dev, 0x2088));
	nv_wi32(dev, fc + 80, nv_rd32(dev, 0x3300));
#if 0 /* no real idea which is PUT/GET in UNK_48.. */
	tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_GET);
	tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16);
	nv_wi32(dev, fc + 72, tmp);
#endif

	nv40_fifo_do_load_context(dev, pfifo->channels - 1);
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
		     NV40_PFIFO_CACHE1_PUSH1_DMA | (pfifo->channels - 1));
	return 0;
}

static void
nv40_fifo_init_reset(struct drm_device *dev)
{
	int i;

	nv_wr32(dev, NV03_PMC_ENABLE,
		nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
	nv_wr32(dev, NV03_PMC_ENABLE,
		nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);

	nv_wr32(dev, 0x003224, 0x000f0078);
	nv_wr32(dev, 0x003210, 0x00000000);
	nv_wr32(dev, 0x003270, 0x00000000);
	nv_wr32(dev, 0x003240, 0x00000000);
	nv_wr32(dev, 0x003244, 0x00000000);
	nv_wr32(dev, 0x003258, 0x00000000);
	nv_wr32(dev, 0x002504, 0x00000000);
	for (i = 0; i < 16; i++)
		nv_wr32(dev, 0x002510 + (i * 4), 0x00000000);
	nv_wr32(dev, 0x00250c, 0x0000ffff);
	nv_wr32(dev, 0x002048, 0x00000000);
	nv_wr32(dev, 0x003228, 0x00000000);
	nv_wr32(dev, 0x0032e8, 0x00000000);
	nv_wr32(dev, 0x002410, 0x00000000);
	nv_wr32(dev, 0x002420, 0x00000000);
	nv_wr32(dev, 0x002058, 0x00000001);
	nv_wr32(dev, 0x00221c, 0x00000000);
	/* something with 0x2084, read/modify/write, no change */
	nv_wr32(dev, 0x002040, 0x000000ff);
	nv_wr32(dev, 0x002500, 0x00000000);
	nv_wr32(dev, 0x003200, 0x00000000);

	nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
}

static void
nv40_fifo_init_ramxx(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
				       ((dev_priv->ramht_bits - 9) << 16) |
				       (dev_priv->ramht_offset >> 8));
	nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);

	switch (dev_priv->chipset) {
	case 0x47:
	case 0x49:
	case 0x4b:
		nv_wr32(dev, 0x2230, 1);
		break;
	default:
		break;
	}

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x41:
	case 0x42:
	case 0x43:
	case 0x45:
	case 0x47:
	case 0x48:
	case 0x49:
	case 0x4b:
		nv_wr32(dev, NV40_PFIFO_RAMFC, 0x30002);
		break;
	default:
		nv_wr32(dev, 0x2230, 0);
		nv_wr32(dev, NV40_PFIFO_RAMFC,
			((dev_priv->vram_size - 512 * 1024 +
			  dev_priv->ramfc_offset) >> 16) | (3 << 16));
		break;
	}
}

static void
nv40_fifo_init_intr(struct drm_device *dev)
{
	nv_wr32(dev, 0x002100, 0xffffffff);
	nv_wr32(dev, 0x002140, 0xffffffff);
}

int
nv40_fifo_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	int i;

	nv40_fifo_init_reset(dev);
	nv40_fifo_init_ramxx(dev);

	nv40_fifo_do_load_context(dev, pfifo->channels - 1);
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);

	nv40_fifo_init_intr(dev);
	pfifo->enable(dev);
	pfifo->reassign(dev, true);

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		if (dev_priv->fifos[i]) {
			uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
			nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
		}
	}

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#include "drmP.h"
	28	#include "nouveau_drv.h"
	29	#include "nouveau_drm.h"
	30
	31	#define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV40_RAMFC__SIZE))
	32	#define NV40_RAMFC__SIZE 128
	33
	34	int
	35	nv40_fifo_create_context(struct nouveau_channel *chan)
	36	{
	37	struct drm_device *dev = chan->dev;
	38	struct drm_nouveau_private *dev_priv = dev->dev_private;
	39	uint32_t fc = NV40_RAMFC(chan->id);
ff9e5279	40	unsigned long flags;
6ee73861 BS	41	int ret;
	42
	43	ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,
	44	NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC \|
a8eaebc6	45	NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
6ee73861 BS	46	if (ret)
	47	return ret;
	48
ff9e5279 MM	49	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
ff9e5279 MM	50
6ee73861 BS	51	nv_wi32(dev, fc + 0, chan->pushbuf_base);
6ee73861 BS	52	nv_wi32(dev, fc + 4, chan->pushbuf_base);
a8eaebc6	53	nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
6ee73861 BS	54	nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES \|
	55	NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES \|
	56	NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 \|
	57	#ifdef __BIG_ENDIAN
	58	NV_PFIFO_CACHE1_BIG_ENDIAN \|
	59	#endif
	60	0x30000000 /* no idea.. */);
a8eaebc6	61	nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4);
6ee73861	62	nv_wi32(dev, fc + 60, 0x0001FFFF);
6ee73861 BS	63
	64	/* enable the fifo dma operation */
	65	nv_wr32(dev, NV04_PFIFO_MODE,
	66	nv_rd32(dev, NV04_PFIFO_MODE) \| (1 << chan->id));
ff9e5279 MM	67
ff9e5279 MM	68	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
6ee73861 BS	69	return 0;
	70	}
	71
	72	void
	73	nv40_fifo_destroy_context(struct nouveau_channel *chan)
	74	{
	75	struct drm_device *dev = chan->dev;
	76
	77	nv_wr32(dev, NV04_PFIFO_MODE,
	78	nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
	79
a8eaebc6	80	nouveau_gpuobj_ref(NULL, &chan->ramfc);
6ee73861 BS	81	}
	82
	83	static void
	84	nv40_fifo_do_load_context(struct drm_device *dev, int chid)
	85	{
	86	struct drm_nouveau_private *dev_priv = dev->dev_private;
	87	uint32_t fc = NV40_RAMFC(chid), tmp, tmp2;
	88
6ee73861 BS	89	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
	90	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
	91	nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
	92	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, nv_ri32(dev, fc + 12));
	93	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, nv_ri32(dev, fc + 16));
	94	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 20));
	95
	96	/* No idea what 0x2058 is.. */
	97	tmp = nv_ri32(dev, fc + 24);
	98	tmp2 = nv_rd32(dev, 0x2058) & 0xFFF;
	99	tmp2 \|= (tmp & 0x30000000);
	100	nv_wr32(dev, 0x2058, tmp2);
	101	tmp &= ~0x30000000;
	102	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, tmp);
	103
	104	nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 28));
	105	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 32));
	106	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 36));
	107	tmp = nv_ri32(dev, fc + 40);
	108	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
	109	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 44));
	110	nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 48));
	111	nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 52));
	112	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, nv_ri32(dev, fc + 56));
	113
	114	/* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
	115	tmp = nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
	116	tmp \|= nv_ri32(dev, fc + 60) & 0x1FFFF;
	117	nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, tmp);
	118
	119	nv_wr32(dev, 0x32e4, nv_ri32(dev, fc + 64));
	120	/* NVIDIA does this next line twice... */
	121	nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68));
	122	nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76));
	123	nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80));
	124
6ee73861 BS	125	nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
	126	nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
	127	}
	128
	129	int
	130	nv40_fifo_load_context(struct nouveau_channel *chan)
	131	{
	132	struct drm_device *dev = chan->dev;
	133	uint32_t tmp;
	134
	135	nv40_fifo_do_load_context(dev, chan->id);
	136
	137	/* Set channel active, and in DMA mode */
	138	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
	139	NV40_PFIFO_CACHE1_PUSH1_DMA \| chan->id);
	140	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
	141
	142	/* Reset DMA_CTL_AT_INFO to INVALID */
	143	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
	144	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
	145
	146	return 0;
	147	}
	148
	149	int
	150	nv40_fifo_unload_context(struct drm_device *dev)
	151	{
	152	struct drm_nouveau_private *dev_priv = dev->dev_private;
	153	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	154	uint32_t fc, tmp;
	155	int chid;
	156
	157	chid = pfifo->channel_id(dev);
	158	if (chid < 0 \|\| chid >= dev_priv->engine.fifo.channels)
	159	return 0;
	160	fc = NV40_RAMFC(chid);
	161
6ee73861 BS	162	nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
	163	nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
	164	nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
	165	nv_wi32(dev, fc + 12, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE));
	166	nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT));
	167	nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
	168	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH);
	169	tmp \|= nv_rd32(dev, 0x2058) & 0x30000000;
	170	nv_wi32(dev, fc + 24, tmp);
	171	nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
	172	nv_wi32(dev, fc + 32, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
	173	nv_wi32(dev, fc + 36, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
	174	tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
	175	nv_wi32(dev, fc + 40, tmp);
	176	nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
	177	nv_wi32(dev, fc + 48, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
	178	/* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
	179	* more involved depending on the value of 0x3228?
	180	*/
	181	nv_wi32(dev, fc + 52, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
	182	nv_wi32(dev, fc + 56, nv_rd32(dev, NV40_PFIFO_GRCTX_INSTANCE));
	183	nv_wi32(dev, fc + 60, nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & 0x1ffff);
	184	/* No idea what the below is for exactly, ripped from a mmio-trace */
	185	nv_wi32(dev, fc + 64, nv_rd32(dev, NV40_PFIFO_UNK32E4));
	186	/* NVIDIA do this next line twice.. bug? */
	187	nv_wi32(dev, fc + 68, nv_rd32(dev, 0x32e8));
	188	nv_wi32(dev, fc + 76, nv_rd32(dev, 0x2088));
	189	nv_wi32(dev, fc + 80, nv_rd32(dev, 0x3300));
	190	#if 0 /* no real idea which is PUT/GET in UNK_48.. */
	191	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_GET);
	192	tmp \|= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16);
	193	nv_wi32(dev, fc + 72, tmp);
	194	#endif
6ee73861 BS	195
	196	nv40_fifo_do_load_context(dev, pfifo->channels - 1);
	197	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
	198	NV40_PFIFO_CACHE1_PUSH1_DMA \| (pfifo->channels - 1));
	199	return 0;
	200	}
	201
	202	static void
	203	nv40_fifo_init_reset(struct drm_device *dev)
	204	{
	205	int i;
	206
	207	nv_wr32(dev, NV03_PMC_ENABLE,
	208	nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
	209	nv_wr32(dev, NV03_PMC_ENABLE,
	210	nv_rd32(dev, NV03_PMC_ENABLE) \| NV_PMC_ENABLE_PFIFO);
	211
	212	nv_wr32(dev, 0x003224, 0x000f0078);
	213	nv_wr32(dev, 0x003210, 0x00000000);
	214	nv_wr32(dev, 0x003270, 0x00000000);
	215	nv_wr32(dev, 0x003240, 0x00000000);
	216	nv_wr32(dev, 0x003244, 0x00000000);
	217	nv_wr32(dev, 0x003258, 0x00000000);
	218	nv_wr32(dev, 0x002504, 0x00000000);
	219	for (i = 0; i < 16; i++)
	220	nv_wr32(dev, 0x002510 + (i * 4), 0x00000000);
	221	nv_wr32(dev, 0x00250c, 0x0000ffff);
	222	nv_wr32(dev, 0x002048, 0x00000000);
	223	nv_wr32(dev, 0x003228, 0x00000000);
	224	nv_wr32(dev, 0x0032e8, 0x00000000);
	225	nv_wr32(dev, 0x002410, 0x00000000);
	226	nv_wr32(dev, 0x002420, 0x00000000);
	227	nv_wr32(dev, 0x002058, 0x00000001);
	228	nv_wr32(dev, 0x00221c, 0x00000000);
	229	/* something with 0x2084, read/modify/write, no change */
	230	nv_wr32(dev, 0x002040, 0x000000ff);
	231	nv_wr32(dev, 0x002500, 0x00000000);
	232	nv_wr32(dev, 0x003200, 0x00000000);
	233
	234	nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
	235	}
	236
	237	static void
	238	nv40_fifo_init_ramxx(struct drm_device *dev)
	239	{
	240	struct drm_nouveau_private *dev_priv = dev->dev_private;
	241
	242	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ \|
	243	((dev_priv->ramht_bits - 9) << 16) \|
	244	(dev_priv->ramht_offset >> 8));
	245	nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
	246
	247	switch (dev_priv->chipset) {
	248	case 0x47:
	249	case 0x49:
	250	case 0x4b:
	251	nv_wr32(dev, 0x2230, 1);
	252	break;
	253	default:
	254	break;
	255	}
	256
	257	switch (dev_priv->chipset) {
	258	case 0x40:
259	case 0x41:
260	case 0x42:
261	case 0x43:
262	case 0x45:
263	case 0x47:
264	case 0x48:
265	case 0x49:
266	case 0x4b:
267	nv_wr32(dev, NV40_PFIFO_RAMFC, 0x30002);
268	break;
269	default:
270	nv_wr32(dev, 0x2230, 0);
271	nv_wr32(dev, NV40_PFIFO_RAMFC,
a76fb4e8	272	((dev_priv->vram_size - 512 * 1024 +
6ee73861 BS	273	dev_priv->ramfc_offset) >> 16) \| (3 << 16));
	274	break;
	275	}
	276	}
	277
	278	static void
	279	nv40_fifo_init_intr(struct drm_device *dev)
	280	{
	281	nv_wr32(dev, 0x002100, 0xffffffff);
	282	nv_wr32(dev, 0x002140, 0xffffffff);
	283	}
	284
	285	int
	286	nv40_fifo_init(struct drm_device *dev)
	287	{
	288	struct drm_nouveau_private *dev_priv = dev->dev_private;
	289	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	290	int i;
	291
	292	nv40_fifo_init_reset(dev);
	293	nv40_fifo_init_ramxx(dev);
	294
	295	nv40_fifo_do_load_context(dev, pfifo->channels - 1);
	296	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
	297
	298	nv40_fifo_init_intr(dev);
	299	pfifo->enable(dev);
	300	pfifo->reassign(dev, true);
	301
	302	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
	303	if (dev_priv->fifos[i]) {
	304	uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
	305	nv_wr32(dev, NV04_PFIFO_MODE, mode \| (1 << i));
	306	}
	307	}
	308
	309	return 0;
	310	}