Commit | Line | Data |
---|---|---|
6ee73861 BS |
1 | #include "drmP.h" |
2 | #include "drm.h" | |
3 | #include "nouveau_drv.h" | |
4 | #include "nouveau_drm.h" | |
5 | ||
6 | int | |
7 | nv40_fb_init(struct drm_device *dev) | |
8 | { | |
9 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
10 | uint32_t fb_bar_size, tmp; | |
11 | int num_tiles; | |
12 | int i; | |
13 | ||
14 | /* This is strictly a NV4x register (don't know about NV5x). */ | |
15 | /* The blob sets these to all kinds of values, and they mess up our setup. */ | |
16 | /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */ | |
17 | /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */ | |
18 | /* Any idea what this is? */ | |
19 | nv_wr32(dev, NV40_PFB_UNK_800, 0x1); | |
20 | ||
21 | switch (dev_priv->chipset) { | |
22 | case 0x40: | |
23 | case 0x45: | |
24 | tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2); | |
25 | nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15)); | |
26 | num_tiles = NV10_PFB_TILE__SIZE; | |
27 | break; | |
28 | case 0x46: /* G72 */ | |
29 | case 0x47: /* G70 */ | |
30 | case 0x49: /* G71 */ | |
31 | case 0x4b: /* G73 */ | |
32 | case 0x4c: /* C51 (G7X version) */ | |
33 | num_tiles = NV40_PFB_TILE__SIZE_1; | |
34 | break; | |
35 | default: | |
36 | num_tiles = NV40_PFB_TILE__SIZE_0; | |
37 | break; | |
38 | } | |
39 | ||
40 | fb_bar_size = drm_get_resource_len(dev, 0) - 1; | |
41 | switch (dev_priv->chipset) { | |
42 | case 0x40: | |
43 | for (i = 0; i < num_tiles; i++) { | |
44 | nv_wr32(dev, NV10_PFB_TILE(i), 0); | |
45 | nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size); | |
46 | } | |
47 | break; | |
48 | default: | |
49 | for (i = 0; i < num_tiles; i++) { | |
50 | nv_wr32(dev, NV40_PFB_TILE(i), 0); | |
51 | nv_wr32(dev, NV40_PFB_TLIMIT(i), fb_bar_size); | |
52 | } | |
53 | break; | |
54 | } | |
55 | ||
56 | return 0; | |
57 | } | |
58 | ||
59 | void | |
60 | nv40_fb_takedown(struct drm_device *dev) | |
61 | { | |
62 | } |