Commit | Line | Data |
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6ee73861 | 1 | /* |
c420b2dc | 2 | * Copyright (C) 2012 Ben Skeggs. |
6ee73861 BS |
3 | * All Rights Reserved. |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
760285e7 | 27 | #include <drm/drmP.h> |
6ee73861 | 28 | #include "nouveau_drv.h" |
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29 | #include "nouveau_fifo.h" |
30 | #include "nouveau_util.h" | |
e05c5a31 | 31 | #include "nouveau_ramht.h" |
6ee73861 | 32 | |
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33 | static struct ramfc_desc { |
34 | unsigned bits:6; | |
35 | unsigned ctxs:5; | |
36 | unsigned ctxp:8; | |
37 | unsigned regs:5; | |
38 | unsigned regp; | |
39 | } nv10_ramfc[] = { | |
40 | { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, | |
41 | { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, | |
42 | { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, | |
43 | { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, | |
44 | { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, | |
45 | { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, | |
46 | { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, | |
47 | { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, | |
48 | { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, | |
49 | {} | |
50 | }; | |
51 | ||
52 | struct nv10_fifo_priv { | |
53 | struct nouveau_fifo_priv base; | |
54 | struct ramfc_desc *ramfc_desc; | |
55 | }; | |
56 | ||
57 | struct nv10_fifo_chan { | |
58 | struct nouveau_fifo_chan base; | |
59 | struct nouveau_gpuobj *ramfc; | |
60 | }; | |
61 | ||
62 | static int | |
63 | nv10_fifo_context_new(struct nouveau_channel *chan, int engine) | |
6ee73861 | 64 | { |
6ee73861 | 65 | struct drm_device *dev = chan->dev; |
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66 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
67 | struct nv10_fifo_priv *priv = nv_engine(dev, engine); | |
68 | struct nv10_fifo_chan *fctx; | |
69 | unsigned long flags; | |
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70 | int ret; |
71 | ||
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72 | fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL); |
73 | if (!fctx) | |
74 | return -ENOMEM; | |
6ee73861 | 75 | |
c420b2dc | 76 | /* map channel control registers */ |
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77 | chan->user = ioremap(pci_resource_start(dev->pdev, 0) + |
78 | NV03_USER(chan->id), PAGE_SIZE); | |
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79 | if (!chan->user) { |
80 | ret = -ENOMEM; | |
81 | goto error; | |
82 | } | |
d908175c | 83 | |
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84 | /* initialise default fifo context */ |
85 | ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst + | |
86 | chan->id * 32, ~0, 32, | |
87 | NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc); | |
88 | if (ret) | |
89 | goto error; | |
90 | ||
91 | nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base); | |
92 | nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base); | |
93 | nv_wo32(fctx->ramfc, 0x08, 0x00000000); | |
94 | nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4); | |
95 | nv_wo32(fctx->ramfc, 0x10, 0x00000000); | |
96 | nv_wo32(fctx->ramfc, 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | | |
97 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | | |
6ee73861 | 98 | #ifdef __BIG_ENDIAN |
c420b2dc | 99 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
6ee73861 | 100 | #endif |
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101 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); |
102 | nv_wo32(fctx->ramfc, 0x18, 0x00000000); | |
103 | nv_wo32(fctx->ramfc, 0x1c, 0x00000000); | |
6ee73861 | 104 | |
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105 | /* enable dma mode on the channel */ |
106 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); | |
107 | nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id)); | |
108 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); | |
6ee73861 | 109 | |
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110 | error: |
111 | if (ret) | |
112 | priv->base.base.context_del(chan, engine); | |
113 | return ret; | |
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114 | } |
115 | ||
116 | int | |
c420b2dc | 117 | nv10_fifo_create(struct drm_device *dev) |
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118 | { |
119 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
c420b2dc | 120 | struct nv10_fifo_priv *priv; |
6ee73861 | 121 | |
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122 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
123 | if (!priv) | |
124 | return -ENOMEM; | |
6ee73861 | 125 | |
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126 | priv->base.base.destroy = nv04_fifo_destroy; |
127 | priv->base.base.init = nv04_fifo_init; | |
128 | priv->base.base.fini = nv04_fifo_fini; | |
129 | priv->base.base.context_new = nv10_fifo_context_new; | |
130 | priv->base.base.context_del = nv04_fifo_context_del; | |
131 | priv->base.channels = 31; | |
132 | priv->ramfc_desc = nv10_ramfc; | |
133 | dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base; | |
6ee73861 | 134 | |
5178d40d | 135 | nouveau_irq_register(dev, 8, nv04_fifo_isr); |
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136 | return 0; |
137 | } |