[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nv10_fence.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs <bskeggs@redhat.com>
 */

#include <core/object.h>
#include <core/class.h>

#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nv10_fence.h"

int
nv10_fence_emit(struct nouveau_fence *fence)
{
	struct nouveau_channel *chan = fence->channel;
	int ret = RING_SPACE(chan, 2);
	if (ret == 0) {
		BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
		OUT_RING  (chan, fence->sequence);
		FIRE_RING (chan);
	}
	return ret;
}


static int
nv10_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	return -ENODEV;
}

int
nv17_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	struct nv10_fence_priv *priv = chan->drm->fence;
	u32 value;
	int ret;

	if (!mutex_trylock(&prev->cli->mutex))
		return -EBUSY;

	spin_lock(&priv->lock);
	value = priv->sequence;
	priv->sequence += 2;
	spin_unlock(&priv->lock);

	ret = RING_SPACE(prev, 5);
	if (!ret) {
		BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
		OUT_RING  (prev, NvSema);
		OUT_RING  (prev, 0);
		OUT_RING  (prev, value + 0);
		OUT_RING  (prev, value + 1);
		FIRE_RING (prev);
	}

	if (!ret && !(ret = RING_SPACE(chan, 5))) {
		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
		OUT_RING  (chan, NvSema);
		OUT_RING  (chan, 0);
		OUT_RING  (chan, value + 1);
		OUT_RING  (chan, value + 2);
		FIRE_RING (chan);
	}

	mutex_unlock(&prev->cli->mutex);
	return 0;
}

u32
nv10_fence_read(struct nouveau_channel *chan)
{
	return nv_ro32(chan->object, 0x0048);
}

void
nv10_fence_context_del(struct nouveau_channel *chan)
{
	struct nv10_fence_chan *fctx = chan->fence;
	nouveau_fence_context_del(&fctx->base);
	chan->fence = NULL;
	kfree(fctx);
}

static int
nv10_fence_context_new(struct nouveau_channel *chan)
{
	struct nv10_fence_priv *priv = chan->drm->fence;
	struct nv10_fence_chan *fctx;
	int ret = 0;

	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);

	if (priv->bo) {
		struct ttm_mem_reg *mem = &priv->bo->bo.mem;
		struct nouveau_object *object;
		u32 start = mem->start * PAGE_SIZE;
		u32 limit = mem->start + mem->size - 1;

		ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
					 NvSema, 0x0002,
					 &(struct nv_dma_class) {
						.flags = NV_DMA_TARGET_VRAM |
							 NV_DMA_ACCESS_RDWR,
						.start = start,
						.limit = limit,
					 }, sizeof(struct nv_dma_class),
					 &object);
	}

	if (ret)
		nv10_fence_context_del(chan);
	return ret;
}

void
nv10_fence_destroy(struct nouveau_drm *drm)
{
	struct nv10_fence_priv *priv = drm->fence;
	nouveau_bo_unmap(priv->bo);
	if (priv->bo)
		nouveau_bo_unpin(priv->bo);
	nouveau_bo_ref(NULL, &priv->bo);
	drm->fence = NULL;
	kfree(priv);
}

void nv17_fence_resume(struct nouveau_drm *drm)
{
	struct nv10_fence_priv *priv = drm->fence;

	nouveau_bo_wr32(priv->bo, 0, priv->sequence);
}

int
nv10_fence_create(struct nouveau_drm *drm)
{
	struct nv10_fence_priv *priv;
	int ret = 0;

	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base.dtor = nv10_fence_destroy;
	priv->base.context_new = nv10_fence_context_new;
	priv->base.context_del = nv10_fence_context_del;
	priv->base.emit = nv10_fence_emit;
	priv->base.read = nv10_fence_read;
	priv->base.sync = nv10_fence_sync;
	spin_lock_init(&priv->lock);

	if (nv_device(drm->device)->chipset >= 0x17) {
		ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
				     0, 0x0000, NULL, &priv->bo);
		if (!ret) {
			ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
			if (!ret) {
				ret = nouveau_bo_map(priv->bo);
				if (ret)
					nouveau_bo_unpin(priv->bo);
			}
			if (ret)
				nouveau_bo_ref(NULL, &priv->bo);
		}

		if (ret == 0) {
			nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
			priv->base.sync = nv17_fence_sync;
			priv->base.resume = nv17_fence_resume;
		}
	}

	if (ret)
		nv10_fence_destroy(drm);
	return ret;
}
Commit	Line	Data
5e120f6e BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs <bskeggs@redhat.com>
	23	*/
	24
ebb945a9 BS	25	#include <core/object.h>
	26	#include <core/class.h>
	27
	28	#include "nouveau_drm.h"
5e120f6e	29	#include "nouveau_dma.h"
a4cea27b	30	#include "nv10_fence.h"
5e120f6e	31
f589be88	32	int
5e120f6e BS	33	nv10_fence_emit(struct nouveau_fence *fence)
	34	{
	35	struct nouveau_channel *chan = fence->channel;
	36	int ret = RING_SPACE(chan, 2);
	37	if (ret == 0) {
	38	BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
	39	OUT_RING (chan, fence->sequence);
	40	FIRE_RING (chan);
	41	}
	42	return ret;
	43	}
	44
906c033e	45
5e120f6e	46	static int
906c033e BS	47	nv10_fence_sync(struct nouveau_fence *fence,
906c033e BS	48	struct nouveau_channel prev, struct nouveau_channel chan)
5e120f6e BS	49	{
	50	return -ENODEV;
	51	}
	52
f589be88	53	int
906c033e BS	54	nv17_fence_sync(struct nouveau_fence *fence,
906c033e BS	55	struct nouveau_channel prev, struct nouveau_channel chan)
5e120f6e	56	{
ebb945a9	57	struct nv10_fence_priv *priv = chan->drm->fence;
5e120f6e BS	58	u32 value;
	59	int ret;
	60
ebb945a9	61	if (!mutex_trylock(&prev->cli->mutex))
5e120f6e BS	62	return -EBUSY;
	63
	64	spin_lock(&priv->lock);
	65	value = priv->sequence;
	66	priv->sequence += 2;
	67	spin_unlock(&priv->lock);
	68
	69	ret = RING_SPACE(prev, 5);
	70	if (!ret) {
	71	BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
	72	OUT_RING (prev, NvSema);
	73	OUT_RING (prev, 0);
	74	OUT_RING (prev, value + 0);
	75	OUT_RING (prev, value + 1);
	76	FIRE_RING (prev);
	77	}
	78
	79	if (!ret && !(ret = RING_SPACE(chan, 5))) {
	80	BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
	81	OUT_RING (chan, NvSema);
	82	OUT_RING (chan, 0);
	83	OUT_RING (chan, value + 1);
	84	OUT_RING (chan, value + 2);
	85	FIRE_RING (chan);
	86	}
	87
ebb945a9	88	mutex_unlock(&prev->cli->mutex);
5e120f6e BS	89	return 0;
	90	}
	91
f589be88	92	u32
5e120f6e BS	93	nv10_fence_read(struct nouveau_channel *chan)
5e120f6e BS	94	{
ebb945a9	95	return nv_ro32(chan->object, 0x0048);
5e120f6e BS	96	}
5e120f6e BS	97
f589be88	98	void
e193b1d4	99	nv10_fence_context_del(struct nouveau_channel *chan)
5e120f6e	100	{
e193b1d4	101	struct nv10_fence_chan *fctx = chan->fence;
5e120f6e	102	nouveau_fence_context_del(&fctx->base);
e193b1d4	103	chan->fence = NULL;
5e120f6e BS	104	kfree(fctx);
	105	}
	106
	107	static int
e193b1d4	108	nv10_fence_context_new(struct nouveau_channel *chan)
5e120f6e	109	{
ebb945a9	110	struct nv10_fence_priv *priv = chan->drm->fence;
5e120f6e	111	struct nv10_fence_chan *fctx;
5e120f6e BS	112	int ret = 0;
5e120f6e BS	113
e193b1d4	114	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
5e120f6e BS	115	if (!fctx)
	116	return -ENOMEM;
	117
	118	nouveau_fence_context_new(&fctx->base);
	119
	120	if (priv->bo) {
	121	struct ttm_mem_reg *mem = &priv->bo->bo.mem;
ebb945a9 BS	122	struct nouveau_object *object;
	123	u32 start = mem->start * PAGE_SIZE;
	124	u32 limit = mem->start + mem->size - 1;
	125
	126	ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
	127	NvSema, 0x0002,
	128	&(struct nv_dma_class) {
	129	.flags = NV_DMA_TARGET_VRAM \|
	130	NV_DMA_ACCESS_RDWR,
	131	.start = start,
	132	.limit = limit,
	133	}, sizeof(struct nv_dma_class),
	134	&object);
5e120f6e BS	135	}
	136
	137	if (ret)
e193b1d4	138	nv10_fence_context_del(chan);
5e120f6e BS	139	return ret;
	140	}
	141
f589be88	142	void
ebb945a9	143	nv10_fence_destroy(struct nouveau_drm *drm)
5e120f6e	144	{
ebb945a9 BS	145	struct nv10_fence_priv *priv = drm->fence;
ebb945a9 BS	146	nouveau_bo_unmap(priv->bo);
04c8c210 MS	147	if (priv->bo)
04c8c210 MS	148	nouveau_bo_unpin(priv->bo);
5e120f6e	149	nouveau_bo_ref(NULL, &priv->bo);
ebb945a9	150	drm->fence = NULL;
5e120f6e BS	151	kfree(priv);
	152	}
	153
f20ebd03 MS	154	void nv17_fence_resume(struct nouveau_drm *drm)
	155	{
	156	struct nv10_fence_priv *priv = drm->fence;
	157
	158	nouveau_bo_wr32(priv->bo, 0, priv->sequence);
	159	}
	160
5e120f6e	161	int
ebb945a9	162	nv10_fence_create(struct nouveau_drm *drm)
5e120f6e	163	{
5e120f6e BS	164	struct nv10_fence_priv *priv;
	165	int ret = 0;
	166
ebb945a9	167	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
5e120f6e BS	168	if (!priv)
	169	return -ENOMEM;
	170
e193b1d4 BS	171	priv->base.dtor = nv10_fence_destroy;
	172	priv->base.context_new = nv10_fence_context_new;
	173	priv->base.context_del = nv10_fence_context_del;
5e120f6e BS	174	priv->base.emit = nv10_fence_emit;
	175	priv->base.read = nv10_fence_read;
	176	priv->base.sync = nv10_fence_sync;
5e120f6e BS	177	spin_lock_init(&priv->lock);
5e120f6e BS	178
ebb945a9 BS	179	if (nv_device(drm->device)->chipset >= 0x17) {
ebb945a9 BS	180	ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
5e120f6e BS	181	0, 0x0000, NULL, &priv->bo);
	182	if (!ret) {
	183	ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
04c8c210	184	if (!ret) {
5e120f6e	185	ret = nouveau_bo_map(priv->bo);
04c8c210 MS	186	if (ret)
	187	nouveau_bo_unpin(priv->bo);
	188	}
5e120f6e BS	189	if (ret)
	190	nouveau_bo_ref(NULL, &priv->bo);
	191	}
	192
	193	if (ret == 0) {
	194	nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
	195	priv->base.sync = nv17_fence_sync;
f20ebd03	196	priv->base.resume = nv17_fence_resume;
5e120f6e BS	197	}
	198	}
	199
	200	if (ret)
ebb945a9	201	nv10_fence_destroy(drm);
5e120f6e BS	202	return ret;
5e120f6e BS	203	}