Commit | Line | Data |
---|---|---|
760285e7 | 1 | #include <drm/drmP.h> |
6ee73861 BS |
2 | #include "nouveau_reg.h" |
3 | #include "nouveau_drv.h" | |
4 | #include "nouveau_crtc.h" | |
5 | #include "nouveau_hw.h" | |
6 | ||
7 | static void | |
8 | nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) | |
9 | { | |
10 | nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); | |
11 | } | |
12 | ||
13 | static void | |
14 | nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) | |
15 | { | |
16 | nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); | |
17 | } | |
18 | ||
19 | static void | |
20 | nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) | |
21 | { | |
b334f2b3 | 22 | nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; |
6ee73861 BS |
23 | NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, |
24 | NV_PRAMDAC_CU_START_POS, | |
25 | XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) | | |
26 | XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X)); | |
27 | } | |
28 | ||
29 | static void | |
30 | crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) | |
31 | { | |
32 | NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, | |
33 | crtcstate->CRTC[index]); | |
34 | } | |
35 | ||
36 | static void | |
37 | nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) | |
38 | { | |
39 | struct drm_device *dev = nv_crtc->base.dev; | |
40 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
41 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; | |
42 | struct drm_crtc *crtc = &nv_crtc->base; | |
43 | ||
44 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = | |
45 | MASK(NV_CIO_CRE_HCUR_ASI) | | |
46 | XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR); | |
47 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = | |
48 | XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR); | |
49 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) | |
50 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= | |
51 | MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); | |
52 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; | |
53 | ||
54 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); | |
55 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); | |
56 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); | |
57 | if (dev_priv->card_type == NV_40) | |
58 | nv_fix_nv40_hw_cursor(dev, nv_crtc->index); | |
59 | } | |
60 | ||
61 | int | |
62 | nv04_cursor_init(struct nouveau_crtc *crtc) | |
63 | { | |
64 | crtc->cursor.set_offset = nv04_cursor_set_offset; | |
65 | crtc->cursor.set_pos = nv04_cursor_set_pos; | |
66 | crtc->cursor.hide = nv04_cursor_hide; | |
67 | crtc->cursor.show = nv04_cursor_show; | |
68 | return 0; | |
69 | } | |
70 |