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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin | |
3 | * Copyright 2008 Stuart Bennett | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include <linux/swab.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/drm_crtc_helper.h> | |
6ee73861 | 30 | #include <linux/vgaarb.h> |
6a9ee8af | 31 | #include <linux/vga_switcheroo.h> |
6ee73861 BS |
32 | |
33 | #include "nouveau_drv.h" | |
760285e7 | 34 | #include <drm/nouveau_drm.h> |
38651674 | 35 | #include "nouveau_fbcon.h" |
a8eaebc6 | 36 | #include "nouveau_ramht.h" |
a0b25635 | 37 | #include "nouveau_gpio.h" |
330c5988 | 38 | #include "nouveau_pm.h" |
6ee73861 | 39 | #include "nv50_display.h" |
c420b2dc | 40 | #include "nouveau_fifo.h" |
5e120f6e | 41 | #include "nouveau_fence.h" |
20abd163 | 42 | #include "nouveau_software.h" |
6ee73861 | 43 | |
6ee73861 | 44 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
ee2e0131 | 45 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
6ee73861 BS |
46 | |
47 | static int nouveau_init_engine_ptrs(struct drm_device *dev) | |
48 | { | |
49 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
50 | struct nouveau_engine *engine = &dev_priv->engine; | |
51 | ||
52 | switch (dev_priv->chipset & 0xf0) { | |
53 | case 0x00: | |
54 | engine->instmem.init = nv04_instmem_init; | |
55 | engine->instmem.takedown = nv04_instmem_takedown; | |
56 | engine->instmem.suspend = nv04_instmem_suspend; | |
57 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
58 | engine->instmem.get = nv04_instmem_get; |
59 | engine->instmem.put = nv04_instmem_put; | |
60 | engine->instmem.map = nv04_instmem_map; | |
61 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 62 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
63 | engine->mc.init = nv04_mc_init; |
64 | engine->mc.takedown = nv04_mc_takedown; | |
65 | engine->timer.init = nv04_timer_init; | |
66 | engine->timer.read = nv04_timer_read; | |
67 | engine->timer.takedown = nv04_timer_takedown; | |
68 | engine->fb.init = nv04_fb_init; | |
69 | engine->fb.takedown = nv04_fb_takedown; | |
c88c2e06 FJ |
70 | engine->display.early_init = nv04_display_early_init; |
71 | engine->display.late_takedown = nv04_display_late_takedown; | |
72 | engine->display.create = nv04_display_create; | |
c88c2e06 | 73 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
74 | engine->display.init = nv04_display_init; |
75 | engine->display.fini = nv04_display_fini; | |
36f1317e BS |
76 | engine->pm.clocks_get = nv04_pm_clocks_get; |
77 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
78 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
7ad2d31c | 79 | engine->vram.init = nv04_fb_vram_init; |
24f246ac | 80 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 81 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
82 | break; |
83 | case 0x10: | |
84 | engine->instmem.init = nv04_instmem_init; | |
85 | engine->instmem.takedown = nv04_instmem_takedown; | |
86 | engine->instmem.suspend = nv04_instmem_suspend; | |
87 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
88 | engine->instmem.get = nv04_instmem_get; |
89 | engine->instmem.put = nv04_instmem_put; | |
90 | engine->instmem.map = nv04_instmem_map; | |
91 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 92 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
93 | engine->mc.init = nv04_mc_init; |
94 | engine->mc.takedown = nv04_mc_takedown; | |
95 | engine->timer.init = nv04_timer_init; | |
96 | engine->timer.read = nv04_timer_read; | |
97 | engine->timer.takedown = nv04_timer_takedown; | |
98 | engine->fb.init = nv10_fb_init; | |
99 | engine->fb.takedown = nv10_fb_takedown; | |
a5cf68b0 FJ |
100 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
101 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
102 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | |
c88c2e06 FJ |
103 | engine->display.early_init = nv04_display_early_init; |
104 | engine->display.late_takedown = nv04_display_late_takedown; | |
105 | engine->display.create = nv04_display_create; | |
c88c2e06 | 106 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
107 | engine->display.init = nv04_display_init; |
108 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
109 | engine->gpio.drive = nv10_gpio_drive; |
110 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
111 | engine->pm.clocks_get = nv04_pm_clocks_get; |
112 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
113 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
7ad2d31c BS |
114 | if (dev_priv->chipset == 0x1a || |
115 | dev_priv->chipset == 0x1f) | |
116 | engine->vram.init = nv1a_fb_vram_init; | |
117 | else | |
118 | engine->vram.init = nv10_fb_vram_init; | |
24f246ac | 119 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 120 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
121 | break; |
122 | case 0x20: | |
123 | engine->instmem.init = nv04_instmem_init; | |
124 | engine->instmem.takedown = nv04_instmem_takedown; | |
125 | engine->instmem.suspend = nv04_instmem_suspend; | |
126 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
127 | engine->instmem.get = nv04_instmem_get; |
128 | engine->instmem.put = nv04_instmem_put; | |
129 | engine->instmem.map = nv04_instmem_map; | |
130 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 131 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
132 | engine->mc.init = nv04_mc_init; |
133 | engine->mc.takedown = nv04_mc_takedown; | |
134 | engine->timer.init = nv04_timer_init; | |
135 | engine->timer.read = nv04_timer_read; | |
136 | engine->timer.takedown = nv04_timer_takedown; | |
d81c19e3 BS |
137 | engine->fb.init = nv20_fb_init; |
138 | engine->fb.takedown = nv20_fb_takedown; | |
139 | engine->fb.init_tile_region = nv20_fb_init_tile_region; | |
140 | engine->fb.set_tile_region = nv20_fb_set_tile_region; | |
141 | engine->fb.free_tile_region = nv20_fb_free_tile_region; | |
c88c2e06 FJ |
142 | engine->display.early_init = nv04_display_early_init; |
143 | engine->display.late_takedown = nv04_display_late_takedown; | |
144 | engine->display.create = nv04_display_create; | |
c88c2e06 | 145 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
146 | engine->display.init = nv04_display_init; |
147 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
148 | engine->gpio.drive = nv10_gpio_drive; |
149 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
150 | engine->pm.clocks_get = nv04_pm_clocks_get; |
151 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
152 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
d81c19e3 | 153 | engine->vram.init = nv20_fb_vram_init; |
24f246ac | 154 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 155 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
156 | break; |
157 | case 0x30: | |
158 | engine->instmem.init = nv04_instmem_init; | |
159 | engine->instmem.takedown = nv04_instmem_takedown; | |
160 | engine->instmem.suspend = nv04_instmem_suspend; | |
161 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
162 | engine->instmem.get = nv04_instmem_get; |
163 | engine->instmem.put = nv04_instmem_put; | |
164 | engine->instmem.map = nv04_instmem_map; | |
165 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 166 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
167 | engine->mc.init = nv04_mc_init; |
168 | engine->mc.takedown = nv04_mc_takedown; | |
169 | engine->timer.init = nv04_timer_init; | |
170 | engine->timer.read = nv04_timer_read; | |
171 | engine->timer.takedown = nv04_timer_takedown; | |
8bded189 FJ |
172 | engine->fb.init = nv30_fb_init; |
173 | engine->fb.takedown = nv30_fb_takedown; | |
a5cf68b0 FJ |
174 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
175 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
176 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
c88c2e06 FJ |
177 | engine->display.early_init = nv04_display_early_init; |
178 | engine->display.late_takedown = nv04_display_late_takedown; | |
179 | engine->display.create = nv04_display_create; | |
c88c2e06 | 180 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
181 | engine->display.init = nv04_display_init; |
182 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
183 | engine->gpio.drive = nv10_gpio_drive; |
184 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
185 | engine->pm.clocks_get = nv04_pm_clocks_get; |
186 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
187 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
442b626e BS |
188 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
189 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
d81c19e3 | 190 | engine->vram.init = nv20_fb_vram_init; |
24f246ac | 191 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 192 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
193 | break; |
194 | case 0x40: | |
195 | case 0x60: | |
196 | engine->instmem.init = nv04_instmem_init; | |
197 | engine->instmem.takedown = nv04_instmem_takedown; | |
198 | engine->instmem.suspend = nv04_instmem_suspend; | |
199 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
200 | engine->instmem.get = nv04_instmem_get; |
201 | engine->instmem.put = nv04_instmem_put; | |
202 | engine->instmem.map = nv04_instmem_map; | |
203 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 204 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
205 | engine->mc.init = nv40_mc_init; |
206 | engine->mc.takedown = nv40_mc_takedown; | |
207 | engine->timer.init = nv04_timer_init; | |
208 | engine->timer.read = nv04_timer_read; | |
209 | engine->timer.takedown = nv04_timer_takedown; | |
210 | engine->fb.init = nv40_fb_init; | |
211 | engine->fb.takedown = nv40_fb_takedown; | |
a5cf68b0 FJ |
212 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
213 | engine->fb.set_tile_region = nv40_fb_set_tile_region; | |
214 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
c88c2e06 FJ |
215 | engine->display.early_init = nv04_display_early_init; |
216 | engine->display.late_takedown = nv04_display_late_takedown; | |
217 | engine->display.create = nv04_display_create; | |
c88c2e06 | 218 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
219 | engine->display.init = nv04_display_init; |
220 | engine->display.fini = nv04_display_fini; | |
47e5d5cb BS |
221 | engine->gpio.init = nv10_gpio_init; |
222 | engine->gpio.fini = nv10_gpio_fini; | |
a0b25635 BS |
223 | engine->gpio.drive = nv10_gpio_drive; |
224 | engine->gpio.sense = nv10_gpio_sense; | |
47e5d5cb | 225 | engine->gpio.irq_enable = nv10_gpio_irq_enable; |
1262a206 BS |
226 | engine->pm.clocks_get = nv40_pm_clocks_get; |
227 | engine->pm.clocks_pre = nv40_pm_clocks_pre; | |
228 | engine->pm.clocks_set = nv40_pm_clocks_set; | |
442b626e BS |
229 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
230 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 | 231 | engine->pm.temp_get = nv40_temp_get; |
69346180 BS |
232 | engine->pm.pwm_get = nv40_pm_pwm_get; |
233 | engine->pm.pwm_set = nv40_pm_pwm_set; | |
ff92a6cd | 234 | engine->vram.init = nv40_fb_vram_init; |
24f246ac | 235 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 236 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
237 | break; |
238 | case 0x50: | |
239 | case 0x80: /* gotta love NVIDIA's consistency.. */ | |
240 | case 0x90: | |
d9f61c2d | 241 | case 0xa0: |
6ee73861 BS |
242 | engine->instmem.init = nv50_instmem_init; |
243 | engine->instmem.takedown = nv50_instmem_takedown; | |
244 | engine->instmem.suspend = nv50_instmem_suspend; | |
245 | engine->instmem.resume = nv50_instmem_resume; | |
e41115d0 BS |
246 | engine->instmem.get = nv50_instmem_get; |
247 | engine->instmem.put = nv50_instmem_put; | |
248 | engine->instmem.map = nv50_instmem_map; | |
249 | engine->instmem.unmap = nv50_instmem_unmap; | |
734ee835 BS |
250 | if (dev_priv->chipset == 0x50) |
251 | engine->instmem.flush = nv50_instmem_flush; | |
252 | else | |
253 | engine->instmem.flush = nv84_instmem_flush; | |
6ee73861 BS |
254 | engine->mc.init = nv50_mc_init; |
255 | engine->mc.takedown = nv50_mc_takedown; | |
256 | engine->timer.init = nv04_timer_init; | |
257 | engine->timer.read = nv04_timer_read; | |
258 | engine->timer.takedown = nv04_timer_takedown; | |
304424e1 MK |
259 | engine->fb.init = nv50_fb_init; |
260 | engine->fb.takedown = nv50_fb_takedown; | |
c88c2e06 FJ |
261 | engine->display.early_init = nv50_display_early_init; |
262 | engine->display.late_takedown = nv50_display_late_takedown; | |
263 | engine->display.create = nv50_display_create; | |
c88c2e06 | 264 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
265 | engine->display.init = nv50_display_init; |
266 | engine->display.fini = nv50_display_fini; | |
ee2e0131 | 267 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
268 | engine->gpio.fini = nv50_gpio_fini; |
269 | engine->gpio.drive = nv50_gpio_drive; | |
270 | engine->gpio.sense = nv50_gpio_sense; | |
ee2e0131 | 271 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
fade7ad5 | 272 | switch (dev_priv->chipset) { |
bd2e597d BS |
273 | case 0x84: |
274 | case 0x86: | |
275 | case 0x92: | |
276 | case 0x94: | |
277 | case 0x96: | |
278 | case 0x98: | |
279 | case 0xa0: | |
5f80198e BS |
280 | case 0xaa: |
281 | case 0xac: | |
bd2e597d | 282 | case 0x50: |
f3fbaf34 BS |
283 | engine->pm.clocks_get = nv50_pm_clocks_get; |
284 | engine->pm.clocks_pre = nv50_pm_clocks_pre; | |
285 | engine->pm.clocks_set = nv50_pm_clocks_set; | |
fade7ad5 | 286 | break; |
bd2e597d | 287 | default: |
ca94a71f BS |
288 | engine->pm.clocks_get = nva3_pm_clocks_get; |
289 | engine->pm.clocks_pre = nva3_pm_clocks_pre; | |
290 | engine->pm.clocks_set = nva3_pm_clocks_set; | |
bd2e597d | 291 | break; |
fade7ad5 | 292 | } |
02c30ca0 BS |
293 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
294 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 FJ |
295 | if (dev_priv->chipset >= 0x84) |
296 | engine->pm.temp_get = nv84_temp_get; | |
297 | else | |
298 | engine->pm.temp_get = nv40_temp_get; | |
5a4267ab BS |
299 | engine->pm.pwm_get = nv50_pm_pwm_get; |
300 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
60d2a88a | 301 | engine->vram.init = nv50_vram_init; |
24f246ac | 302 | engine->vram.takedown = nv50_vram_fini; |
60d2a88a BS |
303 | engine->vram.get = nv50_vram_new; |
304 | engine->vram.put = nv50_vram_del; | |
305 | engine->vram.flags_valid = nv50_vram_flags_valid; | |
6ee73861 | 306 | break; |
d9f61c2d | 307 | case 0xc0: |
4b223eef BS |
308 | engine->instmem.init = nvc0_instmem_init; |
309 | engine->instmem.takedown = nvc0_instmem_takedown; | |
310 | engine->instmem.suspend = nvc0_instmem_suspend; | |
311 | engine->instmem.resume = nvc0_instmem_resume; | |
8984e046 BS |
312 | engine->instmem.get = nv50_instmem_get; |
313 | engine->instmem.put = nv50_instmem_put; | |
314 | engine->instmem.map = nv50_instmem_map; | |
315 | engine->instmem.unmap = nv50_instmem_unmap; | |
316 | engine->instmem.flush = nv84_instmem_flush; | |
4b223eef BS |
317 | engine->mc.init = nv50_mc_init; |
318 | engine->mc.takedown = nv50_mc_takedown; | |
319 | engine->timer.init = nv04_timer_init; | |
320 | engine->timer.read = nv04_timer_read; | |
321 | engine->timer.takedown = nv04_timer_takedown; | |
322 | engine->fb.init = nvc0_fb_init; | |
323 | engine->fb.takedown = nvc0_fb_takedown; | |
4b223eef BS |
324 | engine->display.early_init = nv50_display_early_init; |
325 | engine->display.late_takedown = nv50_display_late_takedown; | |
326 | engine->display.create = nv50_display_create; | |
4b223eef | 327 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
328 | engine->display.init = nv50_display_init; |
329 | engine->display.fini = nv50_display_fini; | |
4b223eef | 330 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
331 | engine->gpio.fini = nv50_gpio_fini; |
332 | engine->gpio.drive = nv50_gpio_drive; | |
333 | engine->gpio.sense = nv50_gpio_sense; | |
4b223eef | 334 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
8984e046 | 335 | engine->vram.init = nvc0_vram_init; |
24f246ac | 336 | engine->vram.takedown = nv50_vram_fini; |
8984e046 BS |
337 | engine->vram.get = nvc0_vram_new; |
338 | engine->vram.put = nv50_vram_del; | |
339 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
74cfad18 | 340 | engine->pm.temp_get = nv84_temp_get; |
354d0781 | 341 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
342 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
343 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
3c71c233 | 344 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
da1dc4cf | 345 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
5a4267ab BS |
346 | engine->pm.pwm_get = nv50_pm_pwm_get; |
347 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
4b223eef | 348 | break; |
d9f61c2d BS |
349 | case 0xd0: |
350 | engine->instmem.init = nvc0_instmem_init; | |
351 | engine->instmem.takedown = nvc0_instmem_takedown; | |
352 | engine->instmem.suspend = nvc0_instmem_suspend; | |
353 | engine->instmem.resume = nvc0_instmem_resume; | |
354 | engine->instmem.get = nv50_instmem_get; | |
355 | engine->instmem.put = nv50_instmem_put; | |
356 | engine->instmem.map = nv50_instmem_map; | |
357 | engine->instmem.unmap = nv50_instmem_unmap; | |
358 | engine->instmem.flush = nv84_instmem_flush; | |
359 | engine->mc.init = nv50_mc_init; | |
360 | engine->mc.takedown = nv50_mc_takedown; | |
361 | engine->timer.init = nv04_timer_init; | |
362 | engine->timer.read = nv04_timer_read; | |
363 | engine->timer.takedown = nv04_timer_takedown; | |
364 | engine->fb.init = nvc0_fb_init; | |
365 | engine->fb.takedown = nvc0_fb_takedown; | |
d9f61c2d BS |
366 | engine->display.early_init = nouveau_stub_init; |
367 | engine->display.late_takedown = nouveau_stub_takedown; | |
26f6d88b | 368 | engine->display.create = nvd0_display_create; |
26f6d88b | 369 | engine->display.destroy = nvd0_display_destroy; |
2a44e499 BS |
370 | engine->display.init = nvd0_display_init; |
371 | engine->display.fini = nvd0_display_fini; | |
d7f8172c | 372 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
373 | engine->gpio.fini = nv50_gpio_fini; |
374 | engine->gpio.drive = nvd0_gpio_drive; | |
375 | engine->gpio.sense = nvd0_gpio_sense; | |
d7f8172c | 376 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
d9f61c2d BS |
377 | engine->vram.init = nvc0_vram_init; |
378 | engine->vram.takedown = nv50_vram_fini; | |
379 | engine->vram.get = nvc0_vram_new; | |
380 | engine->vram.put = nv50_vram_del; | |
381 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
61091837 | 382 | engine->pm.temp_get = nv84_temp_get; |
4784e4aa | 383 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
384 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
385 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
4784e4aa BS |
386 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
387 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
d9f61c2d | 388 | break; |
68455a43 BS |
389 | case 0xe0: |
390 | engine->instmem.init = nvc0_instmem_init; | |
391 | engine->instmem.takedown = nvc0_instmem_takedown; | |
392 | engine->instmem.suspend = nvc0_instmem_suspend; | |
393 | engine->instmem.resume = nvc0_instmem_resume; | |
394 | engine->instmem.get = nv50_instmem_get; | |
395 | engine->instmem.put = nv50_instmem_put; | |
396 | engine->instmem.map = nv50_instmem_map; | |
397 | engine->instmem.unmap = nv50_instmem_unmap; | |
398 | engine->instmem.flush = nv84_instmem_flush; | |
399 | engine->mc.init = nv50_mc_init; | |
400 | engine->mc.takedown = nv50_mc_takedown; | |
401 | engine->timer.init = nv04_timer_init; | |
402 | engine->timer.read = nv04_timer_read; | |
403 | engine->timer.takedown = nv04_timer_takedown; | |
404 | engine->fb.init = nvc0_fb_init; | |
405 | engine->fb.takedown = nvc0_fb_takedown; | |
68455a43 BS |
406 | engine->display.early_init = nouveau_stub_init; |
407 | engine->display.late_takedown = nouveau_stub_takedown; | |
408 | engine->display.create = nvd0_display_create; | |
409 | engine->display.destroy = nvd0_display_destroy; | |
410 | engine->display.init = nvd0_display_init; | |
411 | engine->display.fini = nvd0_display_fini; | |
412 | engine->gpio.init = nv50_gpio_init; | |
413 | engine->gpio.fini = nv50_gpio_fini; | |
414 | engine->gpio.drive = nvd0_gpio_drive; | |
415 | engine->gpio.sense = nvd0_gpio_sense; | |
416 | engine->gpio.irq_enable = nv50_gpio_irq_enable; | |
417 | engine->vram.init = nvc0_vram_init; | |
418 | engine->vram.takedown = nv50_vram_fini; | |
419 | engine->vram.get = nvc0_vram_new; | |
420 | engine->vram.put = nv50_vram_del; | |
421 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
422 | break; | |
6ee73861 BS |
423 | default: |
424 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); | |
425 | return 1; | |
426 | } | |
427 | ||
03bc9675 BS |
428 | /* headless mode */ |
429 | if (nouveau_modeset == 2) { | |
430 | engine->display.early_init = nouveau_stub_init; | |
431 | engine->display.late_takedown = nouveau_stub_takedown; | |
432 | engine->display.create = nouveau_stub_init; | |
433 | engine->display.init = nouveau_stub_init; | |
434 | engine->display.destroy = nouveau_stub_takedown; | |
435 | } | |
436 | ||
6ee73861 BS |
437 | return 0; |
438 | } | |
439 | ||
440 | static unsigned int | |
441 | nouveau_vga_set_decode(void *priv, bool state) | |
442 | { | |
9967b948 MK |
443 | struct drm_device *dev = priv; |
444 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
445 | ||
446 | if (dev_priv->chipset >= 0x40) | |
447 | nv_wr32(dev, 0x88054, state); | |
448 | else | |
449 | nv_wr32(dev, 0x1854, state); | |
450 | ||
6ee73861 BS |
451 | if (state) |
452 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
453 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
454 | else | |
455 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
456 | } | |
457 | ||
6a9ee8af DA |
458 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
459 | enum vga_switcheroo_state state) | |
460 | { | |
fbf81762 | 461 | struct drm_device *dev = pci_get_drvdata(pdev); |
6a9ee8af DA |
462 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
463 | if (state == VGA_SWITCHEROO_ON) { | |
464 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); | |
5bcf719b | 465 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 466 | nouveau_pci_resume(pdev); |
fbf81762 | 467 | drm_kms_helper_poll_enable(dev); |
5bcf719b | 468 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af DA |
469 | } else { |
470 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); | |
5bcf719b | 471 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
fbf81762 | 472 | drm_kms_helper_poll_disable(dev); |
d099230c | 473 | nouveau_switcheroo_optimus_dsm(); |
6a9ee8af | 474 | nouveau_pci_suspend(pdev, pmm); |
5bcf719b | 475 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
476 | } |
477 | } | |
478 | ||
8d608aa6 DA |
479 | static void nouveau_switcheroo_reprobe(struct pci_dev *pdev) |
480 | { | |
481 | struct drm_device *dev = pci_get_drvdata(pdev); | |
482 | nouveau_fbcon_output_poll_changed(dev); | |
483 | } | |
484 | ||
6a9ee8af DA |
485 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) |
486 | { | |
487 | struct drm_device *dev = pci_get_drvdata(pdev); | |
488 | bool can_switch; | |
489 | ||
490 | spin_lock(&dev->count_lock); | |
491 | can_switch = (dev->open_count == 0); | |
492 | spin_unlock(&dev->count_lock); | |
493 | return can_switch; | |
494 | } | |
495 | ||
48aca13f BS |
496 | static void |
497 | nouveau_card_channel_fini(struct drm_device *dev) | |
498 | { | |
499 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
500 | ||
501 | if (dev_priv->channel) | |
502 | nouveau_channel_put_unlocked(&dev_priv->channel); | |
503 | } | |
504 | ||
505 | static int | |
506 | nouveau_card_channel_init(struct drm_device *dev) | |
507 | { | |
508 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
509 | struct nouveau_channel *chan; | |
d1b167e1 | 510 | int ret; |
48aca13f BS |
511 | |
512 | ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT); | |
513 | dev_priv->channel = chan; | |
514 | if (ret) | |
515 | return ret; | |
48aca13f BS |
516 | mutex_unlock(&dev_priv->channel->mutex); |
517 | ||
d1b167e1 BS |
518 | nouveau_bo_move_init(chan); |
519 | return 0; | |
48aca13f BS |
520 | } |
521 | ||
26ec685f TI |
522 | static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = { |
523 | .set_gpu_state = nouveau_switcheroo_set_state, | |
524 | .reprobe = nouveau_switcheroo_reprobe, | |
525 | .can_switch = nouveau_switcheroo_can_switch, | |
526 | }; | |
527 | ||
6ee73861 BS |
528 | int |
529 | nouveau_card_init(struct drm_device *dev) | |
530 | { | |
531 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
532 | struct nouveau_engine *engine; | |
eea55c89 | 533 | int ret, e = 0; |
6ee73861 | 534 | |
6ee73861 | 535 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
26ec685f | 536 | vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops); |
6ee73861 BS |
537 | |
538 | /* Initialise internal driver API hooks */ | |
539 | ret = nouveau_init_engine_ptrs(dev); | |
540 | if (ret) | |
c5804be0 | 541 | goto out; |
6ee73861 | 542 | engine = &dev_priv->engine; |
cff5c133 | 543 | spin_lock_init(&dev_priv->channels.lock); |
a5cf68b0 | 544 | spin_lock_init(&dev_priv->tile.lock); |
ff9e5279 | 545 | spin_lock_init(&dev_priv->context_switch_lock); |
04eb34a4 | 546 | spin_lock_init(&dev_priv->vm_lock); |
6ee73861 | 547 | |
c88c2e06 FJ |
548 | /* Make the CRTCs and I2C buses accessible */ |
549 | ret = engine->display.early_init(dev); | |
550 | if (ret) | |
551 | goto out; | |
552 | ||
6ee73861 | 553 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
cd0b072f BS |
554 | ret = nouveau_bios_init(dev); |
555 | if (ret) | |
c88c2e06 | 556 | goto out_display_early; |
6ee73861 | 557 | |
4c5df493 BS |
558 | /* workaround an odd issue on nvc1 by disabling the device's |
559 | * nosnoop capability. hopefully won't cause issues until a | |
560 | * better fix is found - assuming there is one... | |
561 | */ | |
562 | if (dev_priv->chipset == 0xc1) { | |
563 | nv_mask(dev, 0x00088080, 0x00000800, 0x00000000); | |
564 | } | |
565 | ||
668b6c09 BS |
566 | /* PMC */ |
567 | ret = engine->mc.init(dev); | |
568 | if (ret) | |
569 | goto out_bios; | |
570 | ||
571 | /* PTIMER */ | |
572 | ret = engine->timer.init(dev); | |
573 | if (ret) | |
574 | goto out_mc; | |
575 | ||
576 | /* PFB */ | |
577 | ret = engine->fb.init(dev); | |
578 | if (ret) | |
579 | goto out_timer; | |
330c5988 | 580 | |
24f246ac | 581 | ret = engine->vram.init(dev); |
a76fb4e8 | 582 | if (ret) |
668b6c09 | 583 | goto out_fb; |
a76fb4e8 | 584 | |
668b6c09 BS |
585 | /* PGPIO */ |
586 | ret = nouveau_gpio_create(dev); | |
6ee73861 | 587 | if (ret) |
fbd2895e | 588 | goto out_vram; |
6ee73861 | 589 | |
668b6c09 BS |
590 | ret = nouveau_gpuobj_init(dev); |
591 | if (ret) | |
592 | goto out_gpio; | |
593 | ||
6ee73861 BS |
594 | ret = engine->instmem.init(dev); |
595 | if (ret) | |
fbd2895e | 596 | goto out_gpuobj; |
6ee73861 | 597 | |
24f246ac | 598 | ret = nouveau_mem_vram_init(dev); |
6ee73861 | 599 | if (ret) |
c5804be0 | 600 | goto out_instmem; |
6ee73861 | 601 | |
24f246ac BS |
602 | ret = nouveau_mem_gart_init(dev); |
603 | if (ret) | |
604 | goto out_ttmvram; | |
605 | ||
aba99a84 | 606 | if (!dev_priv->noaccel) { |
c420b2dc BS |
607 | switch (dev_priv->card_type) { |
608 | case NV_04: | |
609 | nv04_fifo_create(dev); | |
610 | break; | |
611 | case NV_10: | |
612 | case NV_20: | |
613 | case NV_30: | |
614 | if (dev_priv->chipset < 0x17) | |
615 | nv10_fifo_create(dev); | |
616 | else | |
617 | nv17_fifo_create(dev); | |
618 | break; | |
619 | case NV_40: | |
620 | nv40_fifo_create(dev); | |
621 | break; | |
622 | case NV_50: | |
623 | if (dev_priv->chipset == 0x50) | |
624 | nv50_fifo_create(dev); | |
625 | else | |
626 | nv84_fifo_create(dev); | |
627 | break; | |
628 | case NV_C0: | |
629 | case NV_D0: | |
630 | nvc0_fifo_create(dev); | |
631 | break; | |
632 | case NV_E0: | |
633 | nve0_fifo_create(dev); | |
634 | break; | |
635 | default: | |
636 | break; | |
637 | } | |
638 | ||
5e120f6e BS |
639 | switch (dev_priv->card_type) { |
640 | case NV_04: | |
641 | nv04_fence_create(dev); | |
642 | break; | |
643 | case NV_10: | |
644 | case NV_20: | |
645 | case NV_30: | |
646 | case NV_40: | |
647 | case NV_50: | |
648 | if (dev_priv->chipset < 0x84) | |
649 | nv10_fence_create(dev); | |
650 | else | |
651 | nv84_fence_create(dev); | |
652 | break; | |
653 | case NV_C0: | |
654 | case NV_D0: | |
655 | case NV_E0: | |
656 | nvc0_fence_create(dev); | |
657 | break; | |
658 | default: | |
659 | break; | |
660 | } | |
661 | ||
20abd163 BS |
662 | switch (dev_priv->card_type) { |
663 | case NV_04: | |
664 | case NV_10: | |
665 | case NV_20: | |
666 | case NV_30: | |
667 | case NV_40: | |
668 | nv04_software_create(dev); | |
669 | break; | |
670 | case NV_50: | |
671 | nv50_software_create(dev); | |
672 | break; | |
673 | case NV_C0: | |
674 | case NV_D0: | |
675 | case NV_E0: | |
676 | nvc0_software_create(dev); | |
677 | break; | |
678 | default: | |
679 | break; | |
680 | } | |
681 | ||
18b54c4d BS |
682 | switch (dev_priv->card_type) { |
683 | case NV_04: | |
684 | nv04_graph_create(dev); | |
685 | break; | |
686 | case NV_10: | |
687 | nv10_graph_create(dev); | |
688 | break; | |
689 | case NV_20: | |
690 | case NV_30: | |
691 | nv20_graph_create(dev); | |
692 | break; | |
693 | case NV_40: | |
694 | nv40_graph_create(dev); | |
695 | break; | |
696 | case NV_50: | |
697 | nv50_graph_create(dev); | |
698 | break; | |
699 | case NV_C0: | |
06784090 | 700 | case NV_D0: |
18b54c4d BS |
701 | nvc0_graph_create(dev); |
702 | break; | |
ab394543 BS |
703 | case NV_E0: |
704 | nve0_graph_create(dev); | |
705 | break; | |
18b54c4d BS |
706 | default: |
707 | break; | |
708 | } | |
6dfdd7a6 | 709 | |
7ff5441e | 710 | switch (dev_priv->chipset) { |
18b54c4d BS |
711 | case 0x84: |
712 | case 0x86: | |
713 | case 0x92: | |
714 | case 0x94: | |
715 | case 0x96: | |
716 | case 0xa0: | |
717 | nv84_crypt_create(dev); | |
7ff5441e | 718 | break; |
8f27c543 BS |
719 | case 0x98: |
720 | case 0xaa: | |
721 | case 0xac: | |
722 | nv98_crypt_create(dev); | |
723 | break; | |
7ff5441e | 724 | } |
7ff5441e | 725 | |
18b54c4d BS |
726 | switch (dev_priv->card_type) { |
727 | case NV_50: | |
728 | switch (dev_priv->chipset) { | |
729 | case 0xa3: | |
730 | case 0xa5: | |
731 | case 0xa8: | |
18b54c4d BS |
732 | nva3_copy_create(dev); |
733 | break; | |
734 | } | |
735 | break; | |
736 | case NV_C0: | |
14f0458a BS |
737 | if (!(nv_rd32(dev, 0x022500) & 0x00000200)) |
738 | nvc0_copy_create(dev, 1); | |
0c75f332 | 739 | case NV_D0: |
14f0458a BS |
740 | if (!(nv_rd32(dev, 0x022500) & 0x00000100)) |
741 | nvc0_copy_create(dev, 0); | |
18b54c4d BS |
742 | break; |
743 | default: | |
744 | break; | |
745 | } | |
746 | ||
8f27c543 BS |
747 | if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) { |
748 | nv84_bsp_create(dev); | |
749 | nv84_vp_create(dev); | |
750 | nv98_ppp_create(dev); | |
751 | } else | |
752 | if (dev_priv->chipset >= 0x84) { | |
753 | nv50_mpeg_create(dev); | |
754 | nv84_bsp_create(dev); | |
755 | nv84_vp_create(dev); | |
756 | } else | |
757 | if (dev_priv->chipset >= 0x50) { | |
758 | nv50_mpeg_create(dev); | |
759 | } else | |
52d07331 BS |
760 | if (dev_priv->card_type == NV_40 || |
761 | dev_priv->chipset == 0x31 || | |
762 | dev_priv->chipset == 0x34 || | |
8f27c543 | 763 | dev_priv->chipset == 0x36) { |
323dcac5 | 764 | nv31_mpeg_create(dev); |
8f27c543 | 765 | } |
a02ccc7f | 766 | |
6dfdd7a6 BS |
767 | for (e = 0; e < NVOBJ_ENGINE_NR; e++) { |
768 | if (dev_priv->eng[e]) { | |
769 | ret = dev_priv->eng[e]->init(dev, e); | |
770 | if (ret) | |
771 | goto out_engine; | |
772 | } | |
773 | } | |
a32ed69d | 774 | } |
6ee73861 | 775 | |
1575b364 BS |
776 | ret = nouveau_irq_init(dev); |
777 | if (ret) | |
c420b2dc | 778 | goto out_engine; |
1575b364 | 779 | |
27d5030a | 780 | ret = nouveau_display_create(dev); |
e88efe05 | 781 | if (ret) |
1575b364 | 782 | goto out_irq; |
6ee73861 | 783 | |
10b461e4 | 784 | nouveau_backlight_init(dev); |
7d3a766b | 785 | nouveau_pm_init(dev); |
10b461e4 | 786 | |
c61205b2 | 787 | if (dev_priv->eng[NVOBJ_ENGINE_GR]) { |
48aca13f | 788 | ret = nouveau_card_channel_init(dev); |
0c6c1c2f | 789 | if (ret) |
5e120f6e | 790 | goto out_pm; |
1575b364 BS |
791 | } |
792 | ||
793 | if (dev->mode_config.num_crtc) { | |
f62b27db | 794 | ret = nouveau_display_init(dev); |
1575b364 BS |
795 | if (ret) |
796 | goto out_chan; | |
797 | ||
798 | nouveau_fbcon_init(dev); | |
6ee73861 BS |
799 | } |
800 | ||
6ee73861 | 801 | return 0; |
c5804be0 | 802 | |
1575b364 | 803 | out_chan: |
48aca13f | 804 | nouveau_card_channel_fini(dev); |
7d3a766b BS |
805 | out_pm: |
806 | nouveau_pm_fini(dev); | |
10b461e4 | 807 | nouveau_backlight_exit(dev); |
27d5030a | 808 | nouveau_display_destroy(dev); |
c5804be0 | 809 | out_irq: |
35fa2f2a | 810 | nouveau_irq_fini(dev); |
6dfdd7a6 | 811 | out_engine: |
aba99a84 | 812 | if (!dev_priv->noaccel) { |
6dfdd7a6 | 813 | for (e = e - 1; e >= 0; e--) { |
2703c21a BS |
814 | if (!dev_priv->eng[e]) |
815 | continue; | |
6c320fef | 816 | dev_priv->eng[e]->fini(dev, e, false); |
2703c21a | 817 | dev_priv->eng[e]->destroy(dev,e ); |
6dfdd7a6 BS |
818 | } |
819 | } | |
fbd2895e | 820 | nouveau_mem_gart_fini(dev); |
24f246ac BS |
821 | out_ttmvram: |
822 | nouveau_mem_vram_fini(dev); | |
c5804be0 MK |
823 | out_instmem: |
824 | engine->instmem.takedown(dev); | |
fbd2895e BS |
825 | out_gpuobj: |
826 | nouveau_gpuobj_takedown(dev); | |
668b6c09 BS |
827 | out_gpio: |
828 | nouveau_gpio_destroy(dev); | |
fbd2895e | 829 | out_vram: |
24f246ac | 830 | engine->vram.takedown(dev); |
668b6c09 BS |
831 | out_fb: |
832 | engine->fb.takedown(dev); | |
833 | out_timer: | |
834 | engine->timer.takedown(dev); | |
835 | out_mc: | |
836 | engine->mc.takedown(dev); | |
c5804be0 MK |
837 | out_bios: |
838 | nouveau_bios_takedown(dev); | |
c88c2e06 FJ |
839 | out_display_early: |
840 | engine->display.late_takedown(dev); | |
c5804be0 | 841 | out: |
5c5ed6e2 | 842 | vga_switcheroo_unregister_client(dev->pdev); |
c5804be0 MK |
843 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
844 | return ret; | |
6ee73861 BS |
845 | } |
846 | ||
847 | static void nouveau_card_takedown(struct drm_device *dev) | |
848 | { | |
849 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
850 | struct nouveau_engine *engine = &dev_priv->engine; | |
6dfdd7a6 | 851 | int e; |
6ee73861 | 852 | |
1575b364 | 853 | if (dev->mode_config.num_crtc) { |
1575b364 | 854 | nouveau_fbcon_fini(dev); |
f62b27db | 855 | nouveau_display_fini(dev); |
1575b364 | 856 | } |
06b75e35 | 857 | |
48aca13f | 858 | nouveau_card_channel_fini(dev); |
7d3a766b | 859 | nouveau_pm_fini(dev); |
10b461e4 | 860 | nouveau_backlight_exit(dev); |
27d5030a | 861 | nouveau_display_destroy(dev); |
06b75e35 | 862 | |
aba99a84 | 863 | if (!dev_priv->noaccel) { |
6dfdd7a6 BS |
864 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { |
865 | if (dev_priv->eng[e]) { | |
6c320fef | 866 | dev_priv->eng[e]->fini(dev, e, false); |
6dfdd7a6 BS |
867 | dev_priv->eng[e]->destroy(dev,e ); |
868 | } | |
869 | } | |
b6d3d871 | 870 | } |
6ee73861 | 871 | |
97666109 JR |
872 | if (dev_priv->vga_ram) { |
873 | nouveau_bo_unpin(dev_priv->vga_ram); | |
874 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
875 | } | |
876 | ||
b6d3d871 BS |
877 | mutex_lock(&dev->struct_mutex); |
878 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); | |
879 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); | |
880 | mutex_unlock(&dev->struct_mutex); | |
fbd2895e | 881 | nouveau_mem_gart_fini(dev); |
24f246ac | 882 | nouveau_mem_vram_fini(dev); |
6ee73861 | 883 | |
b6d3d871 | 884 | engine->instmem.takedown(dev); |
fbd2895e | 885 | nouveau_gpuobj_takedown(dev); |
6ee73861 | 886 | |
668b6c09 BS |
887 | nouveau_gpio_destroy(dev); |
888 | engine->vram.takedown(dev); | |
889 | engine->fb.takedown(dev); | |
890 | engine->timer.takedown(dev); | |
891 | engine->mc.takedown(dev); | |
892 | ||
b6d3d871 | 893 | nouveau_bios_takedown(dev); |
668b6c09 BS |
894 | engine->display.late_takedown(dev); |
895 | ||
896 | nouveau_irq_fini(dev); | |
6ee73861 | 897 | |
5c5ed6e2 | 898 | vga_switcheroo_unregister_client(dev->pdev); |
b6d3d871 | 899 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
6ee73861 BS |
900 | } |
901 | ||
3f0a68d8 BS |
902 | int |
903 | nouveau_open(struct drm_device *dev, struct drm_file *file_priv) | |
904 | { | |
fe32b16e | 905 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
3f0a68d8 | 906 | struct nouveau_fpriv *fpriv; |
e41f26e7 | 907 | int ret; |
3f0a68d8 BS |
908 | |
909 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
910 | if (unlikely(!fpriv)) | |
911 | return -ENOMEM; | |
912 | ||
913 | spin_lock_init(&fpriv->lock); | |
e8a863c1 BS |
914 | INIT_LIST_HEAD(&fpriv->channels); |
915 | ||
e41f26e7 BS |
916 | if (dev_priv->card_type == NV_50) { |
917 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL, | |
918 | &fpriv->vm); | |
919 | if (ret) { | |
920 | kfree(fpriv); | |
921 | return ret; | |
922 | } | |
923 | } else | |
924 | if (dev_priv->card_type >= NV_C0) { | |
5de8037a BS |
925 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL, |
926 | &fpriv->vm); | |
927 | if (ret) { | |
928 | kfree(fpriv); | |
929 | return ret; | |
930 | } | |
e41f26e7 | 931 | } |
fe32b16e | 932 | |
3f0a68d8 BS |
933 | file_priv->driver_priv = fpriv; |
934 | return 0; | |
935 | } | |
936 | ||
6ee73861 BS |
937 | /* here a client dies, release the stuff that was allocated for its |
938 | * file_priv */ | |
939 | void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) | |
940 | { | |
941 | nouveau_channel_cleanup(dev, file_priv); | |
942 | } | |
943 | ||
3f0a68d8 BS |
944 | void |
945 | nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv) | |
946 | { | |
947 | struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv); | |
fe32b16e | 948 | nouveau_vm_ref(NULL, &fpriv->vm, NULL); |
3f0a68d8 BS |
949 | kfree(fpriv); |
950 | } | |
951 | ||
6ee73861 BS |
952 | /* first module load, setup the mmio/fb mapping */ |
953 | /* KMS: we need mmio at load time, not when the first drm client opens. */ | |
954 | int nouveau_firstopen(struct drm_device *dev) | |
955 | { | |
956 | return 0; | |
957 | } | |
958 | ||
959 | /* if we have an OF card, copy vbios to RAMIN */ | |
960 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) | |
961 | { | |
962 | #if defined(__powerpc__) | |
963 | int size, i; | |
964 | const uint32_t *bios; | |
965 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); | |
966 | if (!dn) { | |
967 | NV_INFO(dev, "Unable to get the OF node\n"); | |
968 | return; | |
969 | } | |
970 | ||
971 | bios = of_get_property(dn, "NVDA,BMP", &size); | |
972 | if (bios) { | |
973 | for (i = 0; i < size; i += 4) | |
974 | nv_wi32(dev, i, bios[i/4]); | |
975 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); | |
976 | } else { | |
977 | NV_INFO(dev, "Unable to get the OF bios\n"); | |
978 | } | |
979 | #endif | |
980 | } | |
981 | ||
06415c56 MS |
982 | static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev) |
983 | { | |
984 | struct pci_dev *pdev = dev->pdev; | |
985 | struct apertures_struct *aper = alloc_apertures(3); | |
986 | if (!aper) | |
987 | return NULL; | |
988 | ||
989 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
990 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
991 | aper->count = 1; | |
992 | ||
993 | if (pci_resource_len(pdev, 2)) { | |
994 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
995 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
996 | aper->count++; | |
997 | } | |
998 | ||
999 | if (pci_resource_len(pdev, 3)) { | |
1000 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
1001 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
1002 | aper->count++; | |
1003 | } | |
1004 | ||
1005 | return aper; | |
1006 | } | |
1007 | ||
1008 | static int nouveau_remove_conflicting_drivers(struct drm_device *dev) | |
1009 | { | |
1010 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
3b9676e7 | 1011 | bool primary = false; |
06415c56 MS |
1012 | dev_priv->apertures = nouveau_get_apertures(dev); |
1013 | if (!dev_priv->apertures) | |
1014 | return -ENOMEM; | |
1015 | ||
3b9676e7 MS |
1016 | #ifdef CONFIG_X86 |
1017 | primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1018 | #endif | |
f212949c | 1019 | |
3b9676e7 | 1020 | remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); |
06415c56 MS |
1021 | return 0; |
1022 | } | |
1023 | ||
6ee73861 BS |
1024 | int nouveau_load(struct drm_device *dev, unsigned long flags) |
1025 | { | |
1026 | struct drm_nouveau_private *dev_priv; | |
68455a43 | 1027 | unsigned long long offset, length; |
2f5394c3 | 1028 | uint32_t reg0 = ~0, strap; |
cd0b072f | 1029 | int ret; |
6ee73861 BS |
1030 | |
1031 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
a0d069ea DC |
1032 | if (!dev_priv) { |
1033 | ret = -ENOMEM; | |
1034 | goto err_out; | |
1035 | } | |
6ee73861 BS |
1036 | dev->dev_private = dev_priv; |
1037 | dev_priv->dev = dev; | |
1038 | ||
466e69b8 DA |
1039 | pci_set_master(dev->pdev); |
1040 | ||
6ee73861 | 1041 | dev_priv->flags = flags & NOUVEAU_FLAGS; |
6ee73861 BS |
1042 | |
1043 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", | |
1044 | dev->pci_vendor, dev->pci_device, dev->pdev->class); | |
1045 | ||
2f5394c3 BS |
1046 | /* first up, map the start of mmio and determine the chipset */ |
1047 | dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE); | |
1048 | if (dev_priv->mmio) { | |
1049 | #ifdef __BIG_ENDIAN | |
1050 | /* put the card into big-endian mode if it's not */ | |
1051 | if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001) | |
1052 | nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001); | |
1053 | DRM_MEMORYBARRIER(); | |
1054 | #endif | |
1055 | ||
1056 | /* determine chipset and derive architecture from it */ | |
1057 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); | |
1058 | if ((reg0 & 0x0f000000) > 0) { | |
1059 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; | |
1060 | switch (dev_priv->chipset & 0xf0) { | |
1061 | case 0x10: | |
1062 | case 0x20: | |
1063 | case 0x30: | |
1064 | dev_priv->card_type = dev_priv->chipset & 0xf0; | |
1065 | break; | |
1066 | case 0x40: | |
1067 | case 0x60: | |
1068 | dev_priv->card_type = NV_40; | |
1069 | break; | |
1070 | case 0x50: | |
1071 | case 0x80: | |
1072 | case 0x90: | |
1073 | case 0xa0: | |
1074 | dev_priv->card_type = NV_50; | |
1075 | break; | |
1076 | case 0xc0: | |
1077 | dev_priv->card_type = NV_C0; | |
1078 | break; | |
1079 | case 0xd0: | |
1080 | dev_priv->card_type = NV_D0; | |
1081 | break; | |
68455a43 BS |
1082 | case 0xe0: |
1083 | dev_priv->card_type = NV_E0; | |
1084 | break; | |
2f5394c3 BS |
1085 | default: |
1086 | break; | |
1087 | } | |
1088 | } else | |
1089 | if ((reg0 & 0xff00fff0) == 0x20004000) { | |
1090 | if (reg0 & 0x00f00000) | |
1091 | dev_priv->chipset = 0x05; | |
1092 | else | |
1093 | dev_priv->chipset = 0x04; | |
1094 | dev_priv->card_type = NV_04; | |
1095 | } | |
1096 | ||
1097 | iounmap(dev_priv->mmio); | |
1098 | } | |
1099 | ||
1100 | if (!dev_priv->card_type) { | |
1101 | NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0); | |
1102 | ret = -EINVAL; | |
1103 | goto err_priv; | |
1104 | } | |
1105 | ||
42eddbd7 | 1106 | NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n", |
2f5394c3 | 1107 | dev_priv->card_type, reg0); |
6ee73861 | 1108 | |
68455a43 BS |
1109 | /* map the mmio regs, limiting the amount to preserve vmap space */ |
1110 | offset = pci_resource_start(dev->pdev, 0); | |
1111 | length = pci_resource_len(dev->pdev, 0); | |
1112 | if (dev_priv->card_type < NV_E0) | |
1113 | length = min(length, (unsigned long long)0x00800000); | |
1114 | ||
1115 | dev_priv->mmio = ioremap(offset, length); | |
6ee73861 BS |
1116 | if (!dev_priv->mmio) { |
1117 | NV_ERROR(dev, "Unable to initialize the mmio mapping. " | |
1118 | "Please report your setup to " DRIVER_EMAIL "\n"); | |
a0d069ea | 1119 | ret = -EINVAL; |
d82f8e6c | 1120 | goto err_priv; |
6ee73861 | 1121 | } |
68455a43 | 1122 | NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset); |
6ee73861 | 1123 | |
f2cbe46f BS |
1124 | /* determine frequency of timing crystal */ |
1125 | strap = nv_rd32(dev, 0x101000); | |
1126 | if ( dev_priv->chipset < 0x17 || | |
1127 | (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25)) | |
1128 | strap &= 0x00000040; | |
1129 | else | |
1130 | strap &= 0x00400040; | |
1131 | ||
1132 | switch (strap) { | |
1133 | case 0x00000000: dev_priv->crystal = 13500; break; | |
1134 | case 0x00000040: dev_priv->crystal = 14318; break; | |
1135 | case 0x00400000: dev_priv->crystal = 27000; break; | |
1136 | case 0x00400040: dev_priv->crystal = 25000; break; | |
1137 | } | |
1138 | ||
1139 | NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal); | |
1140 | ||
aba99a84 BS |
1141 | /* Determine whether we'll attempt acceleration or not, some |
1142 | * cards are disabled by default here due to them being known | |
1143 | * non-functional, or never been tested due to lack of hw. | |
1144 | */ | |
1145 | dev_priv->noaccel = !!nouveau_noaccel; | |
1146 | if (nouveau_noaccel == -1) { | |
1147 | switch (dev_priv->chipset) { | |
06784090 | 1148 | case 0xd9: /* known broken */ |
ab394543 BS |
1149 | case 0xe4: /* needs binary driver firmware */ |
1150 | case 0xe7: /* needs binary driver firmware */ | |
ad830d23 BS |
1151 | NV_INFO(dev, "acceleration disabled by default, pass " |
1152 | "noaccel=0 to force enable\n"); | |
aba99a84 BS |
1153 | dev_priv->noaccel = true; |
1154 | break; | |
1155 | default: | |
1156 | dev_priv->noaccel = false; | |
1157 | break; | |
1158 | } | |
1159 | } | |
1160 | ||
cd0b072f BS |
1161 | ret = nouveau_remove_conflicting_drivers(dev); |
1162 | if (ret) | |
a0d069ea | 1163 | goto err_mmio; |
06415c56 | 1164 | |
25985edc | 1165 | /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */ |
6ee73861 BS |
1166 | if (dev_priv->card_type >= NV_40) { |
1167 | int ramin_bar = 2; | |
1168 | if (pci_resource_len(dev->pdev, ramin_bar) == 0) | |
1169 | ramin_bar = 3; | |
1170 | ||
1171 | dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar); | |
6d696305 BS |
1172 | dev_priv->ramin = |
1173 | ioremap(pci_resource_start(dev->pdev, ramin_bar), | |
6ee73861 BS |
1174 | dev_priv->ramin_size); |
1175 | if (!dev_priv->ramin) { | |
ff920bfb | 1176 | NV_ERROR(dev, "Failed to map PRAMIN BAR\n"); |
a0d069ea DC |
1177 | ret = -ENOMEM; |
1178 | goto err_mmio; | |
6ee73861 | 1179 | } |
6d696305 | 1180 | } else { |
6ee73861 | 1181 | dev_priv->ramin_size = 1 * 1024 * 1024; |
68455a43 | 1182 | dev_priv->ramin = ioremap(offset + NV_RAMIN, |
6d696305 | 1183 | dev_priv->ramin_size); |
6ee73861 BS |
1184 | if (!dev_priv->ramin) { |
1185 | NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); | |
a0d069ea DC |
1186 | ret = -ENOMEM; |
1187 | goto err_mmio; | |
6ee73861 BS |
1188 | } |
1189 | } | |
1190 | ||
1191 | nouveau_OF_copy_vbios_to_ramin(dev); | |
1192 | ||
1193 | /* Special flags */ | |
1194 | if (dev->pci_device == 0x01a0) | |
1195 | dev_priv->flags |= NV_NFORCE; | |
1196 | else if (dev->pci_device == 0x01f0) | |
1197 | dev_priv->flags |= NV_NFORCE2; | |
1198 | ||
1199 | /* For kernel modesetting, init card now and bring up fbcon */ | |
cd0b072f BS |
1200 | ret = nouveau_card_init(dev); |
1201 | if (ret) | |
a0d069ea | 1202 | goto err_ramin; |
6ee73861 BS |
1203 | |
1204 | return 0; | |
a0d069ea DC |
1205 | |
1206 | err_ramin: | |
1207 | iounmap(dev_priv->ramin); | |
1208 | err_mmio: | |
1209 | iounmap(dev_priv->mmio); | |
a0d069ea DC |
1210 | err_priv: |
1211 | kfree(dev_priv); | |
1212 | dev->dev_private = NULL; | |
1213 | err_out: | |
1214 | return ret; | |
6ee73861 BS |
1215 | } |
1216 | ||
6ee73861 BS |
1217 | void nouveau_lastclose(struct drm_device *dev) |
1218 | { | |
5ccb377f | 1219 | vga_switcheroo_process_delayed_switch(); |
6ee73861 BS |
1220 | } |
1221 | ||
1222 | int nouveau_unload(struct drm_device *dev) | |
1223 | { | |
1224 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1225 | ||
cd0b072f | 1226 | nouveau_card_takedown(dev); |
6ee73861 BS |
1227 | |
1228 | iounmap(dev_priv->mmio); | |
1229 | iounmap(dev_priv->ramin); | |
1230 | ||
1231 | kfree(dev_priv); | |
1232 | dev->dev_private = NULL; | |
1233 | return 0; | |
1234 | } | |
1235 | ||
6ee73861 | 1236 | /* Wait until (value(reg) & mask) == val, up until timeout has hit */ |
12fb9525 BS |
1237 | bool |
1238 | nouveau_wait_eq(struct drm_device *dev, uint64_t timeout, | |
1239 | uint32_t reg, uint32_t mask, uint32_t val) | |
6ee73861 BS |
1240 | { |
1241 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1242 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1243 | uint64_t start = ptimer->read(dev); | |
1244 | ||
1245 | do { | |
1246 | if ((nv_rd32(dev, reg) & mask) == val) | |
1247 | return true; | |
1248 | } while (ptimer->read(dev) - start < timeout); | |
1249 | ||
1250 | return false; | |
1251 | } | |
1252 | ||
12fb9525 BS |
1253 | /* Wait until (value(reg) & mask) != val, up until timeout has hit */ |
1254 | bool | |
1255 | nouveau_wait_ne(struct drm_device *dev, uint64_t timeout, | |
1256 | uint32_t reg, uint32_t mask, uint32_t val) | |
1257 | { | |
1258 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1259 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1260 | uint64_t start = ptimer->read(dev); | |
1261 | ||
1262 | do { | |
1263 | if ((nv_rd32(dev, reg) & mask) != val) | |
1264 | return true; | |
1265 | } while (ptimer->read(dev) - start < timeout); | |
1266 | ||
1267 | return false; | |
1268 | } | |
1269 | ||
78e2933d BS |
1270 | /* Wait until cond(data) == true, up until timeout has hit */ |
1271 | bool | |
1272 | nouveau_wait_cb(struct drm_device *dev, u64 timeout, | |
1273 | bool (*cond)(void *), void *data) | |
1274 | { | |
1275 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1276 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1277 | u64 start = ptimer->read(dev); | |
1278 | ||
1279 | do { | |
1280 | if (cond(data) == true) | |
1281 | return true; | |
1282 | } while (ptimer->read(dev) - start < timeout); | |
1283 | ||
1284 | return false; | |
1285 | } | |
1286 | ||
6ee73861 BS |
1287 | /* Waits for PGRAPH to go completely idle */ |
1288 | bool nouveau_wait_for_idle(struct drm_device *dev) | |
1289 | { | |
0541324a FJ |
1290 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
1291 | uint32_t mask = ~0; | |
1292 | ||
1293 | if (dev_priv->card_type == NV_40) | |
1294 | mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; | |
1295 | ||
1296 | if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) { | |
6ee73861 BS |
1297 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", |
1298 | nv_rd32(dev, NV04_PGRAPH_STATUS)); | |
1299 | return false; | |
1300 | } | |
1301 | ||
1302 | return true; | |
1303 | } | |
1304 |