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vga_switcheroo: initial implementation (v15)
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_state.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
27#include "drmP.h"
28#include "drm.h"
29#include "drm_sarea.h"
30#include "drm_crtc_helper.h"
31#include <linux/vgaarb.h>
6a9ee8af 32#include <linux/vga_switcheroo.h>
6ee73861
BS		 33
34#include "nouveau_drv.h"
35#include "nouveau_drm.h"
36#include "nv50_display.h"
37
38static int nouveau_stub_init(struct drm_device *dev) { return 0; }
39static void nouveau_stub_takedown(struct drm_device *dev) {}
40
41static int nouveau_init_engine_ptrs(struct drm_device *dev)
42{
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
44 struct nouveau_engine *engine = &dev_priv->engine;
45
46 switch (dev_priv->chipset & 0xf0) {
47 case 0x00:
48 engine->instmem.init = nv04_instmem_init;
49 engine->instmem.takedown = nv04_instmem_takedown;
50 engine->instmem.suspend = nv04_instmem_suspend;
51 engine->instmem.resume = nv04_instmem_resume;
52 engine->instmem.populate = nv04_instmem_populate;
53 engine->instmem.clear = nv04_instmem_clear;
54 engine->instmem.bind = nv04_instmem_bind;
55 engine->instmem.unbind = nv04_instmem_unbind;
56 engine->instmem.prepare_access = nv04_instmem_prepare_access;
57 engine->instmem.finish_access = nv04_instmem_finish_access;
58 engine->mc.init = nv04_mc_init;
59 engine->mc.takedown = nv04_mc_takedown;
60 engine->timer.init = nv04_timer_init;
61 engine->timer.read = nv04_timer_read;
62 engine->timer.takedown = nv04_timer_takedown;
63 engine->fb.init = nv04_fb_init;
64 engine->fb.takedown = nv04_fb_takedown;
65 engine->graph.grclass = nv04_graph_grclass;
66 engine->graph.init = nv04_graph_init;
67 engine->graph.takedown = nv04_graph_takedown;
68 engine->graph.fifo_access = nv04_graph_fifo_access;
69 engine->graph.channel = nv04_graph_channel;
70 engine->graph.create_context = nv04_graph_create_context;
71 engine->graph.destroy_context = nv04_graph_destroy_context;
72 engine->graph.load_context = nv04_graph_load_context;
73 engine->graph.unload_context = nv04_graph_unload_context;
74 engine->fifo.channels = 16;
75 engine->fifo.init = nv04_fifo_init;
76 engine->fifo.takedown = nouveau_stub_takedown;
77 engine->fifo.disable = nv04_fifo_disable;
78 engine->fifo.enable = nv04_fifo_enable;
79 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 80 engine->fifo.cache_flush = nv04_fifo_cache_flush;
81 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 82 engine->fifo.channel_id = nv04_fifo_channel_id;
83 engine->fifo.create_context = nv04_fifo_create_context;
84 engine->fifo.destroy_context = nv04_fifo_destroy_context;
85 engine->fifo.load_context = nv04_fifo_load_context;
86 engine->fifo.unload_context = nv04_fifo_unload_context;
87 break;
88 case 0x10:
89 engine->instmem.init = nv04_instmem_init;
90 engine->instmem.takedown = nv04_instmem_takedown;
91 engine->instmem.suspend = nv04_instmem_suspend;
92 engine->instmem.resume = nv04_instmem_resume;
93 engine->instmem.populate = nv04_instmem_populate;
94 engine->instmem.clear = nv04_instmem_clear;
95 engine->instmem.bind = nv04_instmem_bind;
96 engine->instmem.unbind = nv04_instmem_unbind;
97 engine->instmem.prepare_access = nv04_instmem_prepare_access;
98 engine->instmem.finish_access = nv04_instmem_finish_access;
99 engine->mc.init = nv04_mc_init;
100 engine->mc.takedown = nv04_mc_takedown;
101 engine->timer.init = nv04_timer_init;
102 engine->timer.read = nv04_timer_read;
103 engine->timer.takedown = nv04_timer_takedown;
104 engine->fb.init = nv10_fb_init;
105 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 106 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 107 engine->graph.grclass = nv10_graph_grclass;
108 engine->graph.init = nv10_graph_init;
109 engine->graph.takedown = nv10_graph_takedown;
110 engine->graph.channel = nv10_graph_channel;
111 engine->graph.create_context = nv10_graph_create_context;
112 engine->graph.destroy_context = nv10_graph_destroy_context;
113 engine->graph.fifo_access = nv04_graph_fifo_access;
114 engine->graph.load_context = nv10_graph_load_context;
115 engine->graph.unload_context = nv10_graph_unload_context;
cb00f7c1 116 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
6ee73861
BS		 117 engine->fifo.channels = 32;
118 engine->fifo.init = nv10_fifo_init;
119 engine->fifo.takedown = nouveau_stub_takedown;
120 engine->fifo.disable = nv04_fifo_disable;
121 engine->fifo.enable = nv04_fifo_enable;
122 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 123 engine->fifo.cache_flush = nv04_fifo_cache_flush;
124 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 125 engine->fifo.channel_id = nv10_fifo_channel_id;
126 engine->fifo.create_context = nv10_fifo_create_context;
127 engine->fifo.destroy_context = nv10_fifo_destroy_context;
128 engine->fifo.load_context = nv10_fifo_load_context;
129 engine->fifo.unload_context = nv10_fifo_unload_context;
130 break;
131 case 0x20:
132 engine->instmem.init = nv04_instmem_init;
133 engine->instmem.takedown = nv04_instmem_takedown;
134 engine->instmem.suspend = nv04_instmem_suspend;
135 engine->instmem.resume = nv04_instmem_resume;
136 engine->instmem.populate = nv04_instmem_populate;
137 engine->instmem.clear = nv04_instmem_clear;
138 engine->instmem.bind = nv04_instmem_bind;
139 engine->instmem.unbind = nv04_instmem_unbind;
140 engine->instmem.prepare_access = nv04_instmem_prepare_access;
141 engine->instmem.finish_access = nv04_instmem_finish_access;
142 engine->mc.init = nv04_mc_init;
143 engine->mc.takedown = nv04_mc_takedown;
144 engine->timer.init = nv04_timer_init;
145 engine->timer.read = nv04_timer_read;
146 engine->timer.takedown = nv04_timer_takedown;
147 engine->fb.init = nv10_fb_init;
148 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 149 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 150 engine->graph.grclass = nv20_graph_grclass;
151 engine->graph.init = nv20_graph_init;
152 engine->graph.takedown = nv20_graph_takedown;
153 engine->graph.channel = nv10_graph_channel;
154 engine->graph.create_context = nv20_graph_create_context;
155 engine->graph.destroy_context = nv20_graph_destroy_context;
156 engine->graph.fifo_access = nv04_graph_fifo_access;
157 engine->graph.load_context = nv20_graph_load_context;
158 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 159 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 160 engine->fifo.channels = 32;
161 engine->fifo.init = nv10_fifo_init;
162 engine->fifo.takedown = nouveau_stub_takedown;
163 engine->fifo.disable = nv04_fifo_disable;
164 engine->fifo.enable = nv04_fifo_enable;
165 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 166 engine->fifo.cache_flush = nv04_fifo_cache_flush;
167 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 168 engine->fifo.channel_id = nv10_fifo_channel_id;
169 engine->fifo.create_context = nv10_fifo_create_context;
170 engine->fifo.destroy_context = nv10_fifo_destroy_context;
171 engine->fifo.load_context = nv10_fifo_load_context;
172 engine->fifo.unload_context = nv10_fifo_unload_context;
173 break;
174 case 0x30:
175 engine->instmem.init = nv04_instmem_init;
176 engine->instmem.takedown = nv04_instmem_takedown;
177 engine->instmem.suspend = nv04_instmem_suspend;
178 engine->instmem.resume = nv04_instmem_resume;
179 engine->instmem.populate = nv04_instmem_populate;
180 engine->instmem.clear = nv04_instmem_clear;
181 engine->instmem.bind = nv04_instmem_bind;
182 engine->instmem.unbind = nv04_instmem_unbind;
183 engine->instmem.prepare_access = nv04_instmem_prepare_access;
184 engine->instmem.finish_access = nv04_instmem_finish_access;
185 engine->mc.init = nv04_mc_init;
186 engine->mc.takedown = nv04_mc_takedown;
187 engine->timer.init = nv04_timer_init;
188 engine->timer.read = nv04_timer_read;
189 engine->timer.takedown = nv04_timer_takedown;
190 engine->fb.init = nv10_fb_init;
191 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 192 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 193 engine->graph.grclass = nv30_graph_grclass;
194 engine->graph.init = nv30_graph_init;
195 engine->graph.takedown = nv20_graph_takedown;
196 engine->graph.fifo_access = nv04_graph_fifo_access;
197 engine->graph.channel = nv10_graph_channel;
198 engine->graph.create_context = nv20_graph_create_context;
199 engine->graph.destroy_context = nv20_graph_destroy_context;
200 engine->graph.load_context = nv20_graph_load_context;
201 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 202 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 203 engine->fifo.channels = 32;
204 engine->fifo.init = nv10_fifo_init;
205 engine->fifo.takedown = nouveau_stub_takedown;
206 engine->fifo.disable = nv04_fifo_disable;
207 engine->fifo.enable = nv04_fifo_enable;
208 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 209 engine->fifo.cache_flush = nv04_fifo_cache_flush;
210 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 211 engine->fifo.channel_id = nv10_fifo_channel_id;
212 engine->fifo.create_context = nv10_fifo_create_context;
213 engine->fifo.destroy_context = nv10_fifo_destroy_context;
214 engine->fifo.load_context = nv10_fifo_load_context;
215 engine->fifo.unload_context = nv10_fifo_unload_context;
216 break;
217 case 0x40:
218 case 0x60:
219 engine->instmem.init = nv04_instmem_init;
220 engine->instmem.takedown = nv04_instmem_takedown;
221 engine->instmem.suspend = nv04_instmem_suspend;
222 engine->instmem.resume = nv04_instmem_resume;
223 engine->instmem.populate = nv04_instmem_populate;
224 engine->instmem.clear = nv04_instmem_clear;
225 engine->instmem.bind = nv04_instmem_bind;
226 engine->instmem.unbind = nv04_instmem_unbind;
227 engine->instmem.prepare_access = nv04_instmem_prepare_access;
228 engine->instmem.finish_access = nv04_instmem_finish_access;
229 engine->mc.init = nv40_mc_init;
230 engine->mc.takedown = nv40_mc_takedown;
231 engine->timer.init = nv04_timer_init;
232 engine->timer.read = nv04_timer_read;
233 engine->timer.takedown = nv04_timer_takedown;
234 engine->fb.init = nv40_fb_init;
235 engine->fb.takedown = nv40_fb_takedown;
cb00f7c1 236 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
6ee73861
BS		 237 engine->graph.grclass = nv40_graph_grclass;
238 engine->graph.init = nv40_graph_init;
239 engine->graph.takedown = nv40_graph_takedown;
240 engine->graph.fifo_access = nv04_graph_fifo_access;
241 engine->graph.channel = nv40_graph_channel;
242 engine->graph.create_context = nv40_graph_create_context;
243 engine->graph.destroy_context = nv40_graph_destroy_context;
244 engine->graph.load_context = nv40_graph_load_context;
245 engine->graph.unload_context = nv40_graph_unload_context;
cb00f7c1 246 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
6ee73861
BS		 247 engine->fifo.channels = 32;
248 engine->fifo.init = nv40_fifo_init;
249 engine->fifo.takedown = nouveau_stub_takedown;
250 engine->fifo.disable = nv04_fifo_disable;
251 engine->fifo.enable = nv04_fifo_enable;
252 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 253 engine->fifo.cache_flush = nv04_fifo_cache_flush;
254 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 255 engine->fifo.channel_id = nv10_fifo_channel_id;
256 engine->fifo.create_context = nv40_fifo_create_context;
257 engine->fifo.destroy_context = nv40_fifo_destroy_context;
258 engine->fifo.load_context = nv40_fifo_load_context;
259 engine->fifo.unload_context = nv40_fifo_unload_context;
260 break;
261 case 0x50:
262 case 0x80: /* gotta love NVIDIA's consistency.. */
263 case 0x90:
264 case 0xA0:
265 engine->instmem.init = nv50_instmem_init;
266 engine->instmem.takedown = nv50_instmem_takedown;
267 engine->instmem.suspend = nv50_instmem_suspend;
268 engine->instmem.resume = nv50_instmem_resume;
269 engine->instmem.populate = nv50_instmem_populate;
270 engine->instmem.clear = nv50_instmem_clear;
271 engine->instmem.bind = nv50_instmem_bind;
272 engine->instmem.unbind = nv50_instmem_unbind;
273 engine->instmem.prepare_access = nv50_instmem_prepare_access;
274 engine->instmem.finish_access = nv50_instmem_finish_access;
275 engine->mc.init = nv50_mc_init;
276 engine->mc.takedown = nv50_mc_takedown;
277 engine->timer.init = nv04_timer_init;
278 engine->timer.read = nv04_timer_read;
279 engine->timer.takedown = nv04_timer_takedown;
280 engine->fb.init = nouveau_stub_init;
281 engine->fb.takedown = nouveau_stub_takedown;
282 engine->graph.grclass = nv50_graph_grclass;
283 engine->graph.init = nv50_graph_init;
284 engine->graph.takedown = nv50_graph_takedown;
285 engine->graph.fifo_access = nv50_graph_fifo_access;
286 engine->graph.channel = nv50_graph_channel;
287 engine->graph.create_context = nv50_graph_create_context;
288 engine->graph.destroy_context = nv50_graph_destroy_context;
289 engine->graph.load_context = nv50_graph_load_context;
290 engine->graph.unload_context = nv50_graph_unload_context;
291 engine->fifo.channels = 128;
292 engine->fifo.init = nv50_fifo_init;
293 engine->fifo.takedown = nv50_fifo_takedown;
294 engine->fifo.disable = nv04_fifo_disable;
295 engine->fifo.enable = nv04_fifo_enable;
296 engine->fifo.reassign = nv04_fifo_reassign;
297 engine->fifo.channel_id = nv50_fifo_channel_id;
298 engine->fifo.create_context = nv50_fifo_create_context;
299 engine->fifo.destroy_context = nv50_fifo_destroy_context;
300 engine->fifo.load_context = nv50_fifo_load_context;
301 engine->fifo.unload_context = nv50_fifo_unload_context;
302 break;
303 default:
304 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
305 return 1;
306 }
307
308 return 0;
309}
310
311static unsigned int
312nouveau_vga_set_decode(void *priv, bool state)
313{
9967b948
MK		 314 struct drm_device *dev = priv;
315 struct drm_nouveau_private *dev_priv = dev->dev_private;
316
317 if (dev_priv->chipset >= 0x40)
318 nv_wr32(dev, 0x88054, state);
319 else
320 nv_wr32(dev, 0x1854, state);
321
6ee73861
BS		 322 if (state)
323 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
324 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
325 else
326 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
327}
328
0735f62e
BS		 329static int
330nouveau_card_init_channel(struct drm_device *dev)
331{
332 struct drm_nouveau_private *dev_priv = dev->dev_private;
333 struct nouveau_gpuobj *gpuobj;
334 int ret;
335
336 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
337 (struct drm_file *)-2,
338 NvDmaFB, NvDmaTT);
339 if (ret)
340 return ret;
341
342 gpuobj = NULL;
343 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
344 0, nouveau_mem_fb_amount(dev),
345 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
346 &gpuobj);
347 if (ret)
348 goto out_err;
349
350 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
351 gpuobj, NULL);
352 if (ret)
353 goto out_err;
354
355 gpuobj = NULL;
356 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
357 dev_priv->gart_info.aper_size,
358 NV_DMA_ACCESS_RW, &gpuobj, NULL);
359 if (ret)
360 goto out_err;
361
362 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
363 gpuobj, NULL);
364 if (ret)
365 goto out_err;
366
367 return 0;
368out_err:
369 nouveau_gpuobj_del(dev, &gpuobj);
370 nouveau_channel_free(dev_priv->channel);
371 dev_priv->channel = NULL;
372 return ret;
373}
374
6a9ee8af
DA		 375static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
376 enum vga_switcheroo_state state)
377{
378 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
379 if (state == VGA_SWITCHEROO_ON) {
380 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
381 nouveau_pci_resume(pdev);
382 } else {
383 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
384 nouveau_pci_suspend(pdev, pmm);
385 }
386}
387
388static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
389{
390 struct drm_device *dev = pci_get_drvdata(pdev);
391 bool can_switch;
392
393 spin_lock(&dev->count_lock);
394 can_switch = (dev->open_count == 0);
395 spin_unlock(&dev->count_lock);
396 return can_switch;
397}
398
6ee73861
BS		 399int
400nouveau_card_init(struct drm_device *dev)
401{
402 struct drm_nouveau_private *dev_priv = dev->dev_private;
403 struct nouveau_engine *engine;
6ee73861
BS		 404 int ret;
405
406 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
407
408 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
409 return 0;
410
411 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
6a9ee8af
DA		 412 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
413 nouveau_switcheroo_can_switch);
6ee73861
BS		 414
415 /* Initialise internal driver API hooks */
416 ret = nouveau_init_engine_ptrs(dev);
417 if (ret)
c5804be0 418 goto out;
6ee73861
BS		 419 engine = &dev_priv->engine;
420 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
421
422 /* Parse BIOS tables / Run init tables if card not POSTed */
423 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
424 ret = nouveau_bios_init(dev);
425 if (ret)
c5804be0 426 goto out;
6ee73861
BS		 427 }
428
429 ret = nouveau_gpuobj_early_init(dev);
430 if (ret)
c5804be0 431 goto out_bios;
6ee73861
BS		 432
433 /* Initialise instance memory, must happen before mem_init so we
434 * know exactly how much VRAM we're able to use for "normal"
435 * purposes.
436 */
437 ret = engine->instmem.init(dev);
438 if (ret)
c5804be0 439 goto out_gpuobj_early;
6ee73861
BS		 440
441 /* Setup the memory manager */
442 ret = nouveau_mem_init(dev);
443 if (ret)
c5804be0 444 goto out_instmem;
6ee73861
BS		 445
446 ret = nouveau_gpuobj_init(dev);
447 if (ret)
c5804be0 448 goto out_mem;
6ee73861
BS		 449
450 /* PMC */
451 ret = engine->mc.init(dev);
452 if (ret)
c5804be0 453 goto out_gpuobj;
6ee73861
BS		 454
455 /* PTIMER */
456 ret = engine->timer.init(dev);
457 if (ret)
c5804be0 458 goto out_mc;
6ee73861
BS		 459
460 /* PFB */
461 ret = engine->fb.init(dev);
462 if (ret)
c5804be0 463 goto out_timer;
6ee73861 464
a32ed69d
MK		 465 if (nouveau_noaccel)
466 engine->graph.accel_blocked = true;
467 else {
468 /* PGRAPH */
469 ret = engine->graph.init(dev);
470 if (ret)
471 goto out_fb;
6ee73861 472
a32ed69d
MK		 473 /* PFIFO */
474 ret = engine->fifo.init(dev);
475 if (ret)
476 goto out_graph;
477 }
6ee73861
BS		 478
479 /* this call irq_preinstall, register irq handler and
480 * call irq_postinstall
481 */
482 ret = drm_irq_install(dev);
483 if (ret)
c5804be0 484 goto out_fifo;
6ee73861
BS		 485
486 ret = drm_vblank_init(dev, 0);
487 if (ret)
c5804be0 488 goto out_irq;
6ee73861
BS		 489
490 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
491
0735f62e
BS		 492 if (!engine->graph.accel_blocked) {
493 ret = nouveau_card_init_channel(dev);
494 if (ret)
495 goto out_irq;
6ee73861
BS		 496 }
497
498 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c5804be0 499 if (dev_priv->card_type >= NV_50)
6ee73861 500 ret = nv50_display_create(dev);
c5804be0 501 else
6ee73861 502 ret = nv04_display_create(dev);
c5804be0
MK		 503 if (ret)
504 goto out_irq;
6ee73861
BS		 505 }
506
507 ret = nouveau_backlight_init(dev);
508 if (ret)
509 NV_ERROR(dev, "Error %d registering backlight\n", ret);
510
511 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
512
513 if (drm_core_check_feature(dev, DRIVER_MODESET))
514 drm_helper_initial_config(dev);
515
516 return 0;
c5804be0
MK		 517
518out_irq:
519 drm_irq_uninstall(dev);
520out_fifo:
a32ed69d
MK		 521 if (!nouveau_noaccel)
522 engine->fifo.takedown(dev);
c5804be0 523out_graph:
a32ed69d
MK		 524 if (!nouveau_noaccel)
525 engine->graph.takedown(dev);
c5804be0
MK		 526out_fb:
527 engine->fb.takedown(dev);
528out_timer:
529 engine->timer.takedown(dev);
530out_mc:
531 engine->mc.takedown(dev);
532out_gpuobj:
533 nouveau_gpuobj_takedown(dev);
534out_mem:
535 nouveau_mem_close(dev);
536out_instmem:
537 engine->instmem.takedown(dev);
538out_gpuobj_early:
539 nouveau_gpuobj_late_takedown(dev);
540out_bios:
541 nouveau_bios_takedown(dev);
542out:
543 vga_client_register(dev->pdev, NULL, NULL, NULL);
544 return ret;
6ee73861
BS		 545}
546
547static void nouveau_card_takedown(struct drm_device *dev)
548{
549 struct drm_nouveau_private *dev_priv = dev->dev_private;
550 struct nouveau_engine *engine = &dev_priv->engine;
551
552 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
553
554 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
555 nouveau_backlight_exit(dev);
556
557 if (dev_priv->channel) {
558 nouveau_channel_free(dev_priv->channel);
559 dev_priv->channel = NULL;
560 }
561
a32ed69d
MK		 562 if (!nouveau_noaccel) {
563 engine->fifo.takedown(dev);
564 engine->graph.takedown(dev);
565 }
6ee73861
BS		 566 engine->fb.takedown(dev);
567 engine->timer.takedown(dev);
568 engine->mc.takedown(dev);
569
570 mutex_lock(&dev->struct_mutex);
71666475 571 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
6ee73861
BS		 572 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
573 mutex_unlock(&dev->struct_mutex);
574 nouveau_sgdma_takedown(dev);
575
576 nouveau_gpuobj_takedown(dev);
577 nouveau_mem_close(dev);
578 engine->instmem.takedown(dev);
579
580 if (drm_core_check_feature(dev, DRIVER_MODESET))
581 drm_irq_uninstall(dev);
582
583 nouveau_gpuobj_late_takedown(dev);
584 nouveau_bios_takedown(dev);
585
586 vga_client_register(dev->pdev, NULL, NULL, NULL);
587
588 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
589 }
590}
591
592/* here a client dies, release the stuff that was allocated for its
593 * file_priv */
594void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
595{
596 nouveau_channel_cleanup(dev, file_priv);
597}
598
599/* first module load, setup the mmio/fb mapping */
600/* KMS: we need mmio at load time, not when the first drm client opens. */
601int nouveau_firstopen(struct drm_device *dev)
602{
603 return 0;
604}
605
606/* if we have an OF card, copy vbios to RAMIN */
607static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
608{
609#if defined(__powerpc__)
610 int size, i;
611 const uint32_t *bios;
612 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
613 if (!dn) {
614 NV_INFO(dev, "Unable to get the OF node\n");
615 return;
616 }
617
618 bios = of_get_property(dn, "NVDA,BMP", &size);
619 if (bios) {
620 for (i = 0; i < size; i += 4)
621 nv_wi32(dev, i, bios[i/4]);
622 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
623 } else {
624 NV_INFO(dev, "Unable to get the OF bios\n");
625 }
626#endif
627}
628
629int nouveau_load(struct drm_device *dev, unsigned long flags)
630{
631 struct drm_nouveau_private *dev_priv;
632 uint32_t reg0;
633 resource_size_t mmio_start_offs;
634
635 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
636 if (!dev_priv)
637 return -ENOMEM;
638 dev->dev_private = dev_priv;
639 dev_priv->dev = dev;
640
641 dev_priv->flags = flags & NOUVEAU_FLAGS;
642 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
643
644 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
645 dev->pci_vendor, dev->pci_device, dev->pdev->class);
646
6ee73861
BS		 647 dev_priv->wq = create_workqueue("nouveau");
648 if (!dev_priv->wq)
649 return -EINVAL;
650
651 /* resource 0 is mmio regs */
652 /* resource 1 is linear FB */
653 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
654 /* resource 6 is bios */
655
656 /* map the mmio regs */
657 mmio_start_offs = pci_resource_start(dev->pdev, 0);
658 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
659 if (!dev_priv->mmio) {
660 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
661 "Please report your setup to " DRIVER_EMAIL "\n");
662 return -EINVAL;
663 }
664 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
665 (unsigned long long)mmio_start_offs);
666
667#ifdef __BIG_ENDIAN
668 /* Put the card in BE mode if it's not */
669 if (nv_rd32(dev, NV03_PMC_BOOT_1))
670 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
671
672 DRM_MEMORYBARRIER();
673#endif
674
675 /* Time to determine the card architecture */
676 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
677
678 /* We're dealing with >=NV10 */
679 if ((reg0 & 0x0f000000) > 0) {
680 /* Bit 27-20 contain the architecture in hex */
681 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
682 /* NV04 or NV05 */
683 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1dee7a93
BS		 684 if (reg0 & 0x00f00000)
685 dev_priv->chipset = 0x05;
686 else
687 dev_priv->chipset = 0x04;
6ee73861
BS		 688 } else
689 dev_priv->chipset = 0xff;
690
691 switch (dev_priv->chipset & 0xf0) {
692 case 0x00:
693 case 0x10:
694 case 0x20:
695 case 0x30:
696 dev_priv->card_type = dev_priv->chipset & 0xf0;
697 break;
698 case 0x40:
699 case 0x60:
700 dev_priv->card_type = NV_40;
701 break;
702 case 0x50:
703 case 0x80:
704 case 0x90:
705 case 0xa0:
706 dev_priv->card_type = NV_50;
707 break;
708 default:
709 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
710 return -EINVAL;
711 }
712
713 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
714 dev_priv->card_type, reg0);
715
716 /* map larger RAMIN aperture on NV40 cards */
717 dev_priv->ramin = NULL;
718 if (dev_priv->card_type >= NV_40) {
719 int ramin_bar = 2;
720 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
721 ramin_bar = 3;
722
723 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
724 dev_priv->ramin = ioremap(
725 pci_resource_start(dev->pdev, ramin_bar),
726 dev_priv->ramin_size);
727 if (!dev_priv->ramin) {
728 NV_ERROR(dev, "Failed to init RAMIN mapping, "
729 "limited instance memory available\n");
730 }
731 }
732
733 /* On older cards (or if the above failed), create a map covering
734 * the BAR0 PRAMIN aperture */
735 if (!dev_priv->ramin) {
736 dev_priv->ramin_size = 1 * 1024 * 1024;
737 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
738 dev_priv->ramin_size);
739 if (!dev_priv->ramin) {
740 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
741 return -ENOMEM;
742 }
743 }
744
745 nouveau_OF_copy_vbios_to_ramin(dev);
746
747 /* Special flags */
748 if (dev->pci_device == 0x01a0)
749 dev_priv->flags |= NV_NFORCE;
750 else if (dev->pci_device == 0x01f0)
751 dev_priv->flags |= NV_NFORCE2;
752
753 /* For kernel modesetting, init card now and bring up fbcon */
754 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
755 int ret = nouveau_card_init(dev);
756 if (ret)
757 return ret;
758 }
759
760 return 0;
761}
762
763static void nouveau_close(struct drm_device *dev)
764{
765 struct drm_nouveau_private *dev_priv = dev->dev_private;
766
111b459a
FJ		 767 /* In the case of an error dev_priv may not be allocated yet */
768 if (dev_priv)
6ee73861
BS		 769 nouveau_card_takedown(dev);
770}
771
772/* KMS: we need mmio at load time, not when the first drm client opens. */
773void nouveau_lastclose(struct drm_device *dev)
774{
775 if (drm_core_check_feature(dev, DRIVER_MODESET))
776 return;
777
778 nouveau_close(dev);
779}
780
781int nouveau_unload(struct drm_device *dev)
782{
783 struct drm_nouveau_private *dev_priv = dev->dev_private;
784
785 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
786 if (dev_priv->card_type >= NV_50)
787 nv50_display_destroy(dev);
788 else
789 nv04_display_destroy(dev);
790 nouveau_close(dev);
791 }
792
793 iounmap(dev_priv->mmio);
794 iounmap(dev_priv->ramin);
795
796 kfree(dev_priv);
797 dev->dev_private = NULL;
798 return 0;
799}
800
801int
802nouveau_ioctl_card_init(struct drm_device *dev, void *data,
803 struct drm_file *file_priv)
804{
805 return nouveau_card_init(dev);
806}
807
808int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
809 struct drm_file *file_priv)
810{
811 struct drm_nouveau_private *dev_priv = dev->dev_private;
812 struct drm_nouveau_getparam *getparam = data;
813
814 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
815
816 switch (getparam->param) {
817 case NOUVEAU_GETPARAM_CHIPSET_ID:
818 getparam->value = dev_priv->chipset;
819 break;
820 case NOUVEAU_GETPARAM_PCI_VENDOR:
821 getparam->value = dev->pci_vendor;
822 break;
823 case NOUVEAU_GETPARAM_PCI_DEVICE:
824 getparam->value = dev->pci_device;
825 break;
826 case NOUVEAU_GETPARAM_BUS_TYPE:
827 if (drm_device_is_agp(dev))
828 getparam->value = NV_AGP;
829 else if (drm_device_is_pcie(dev))
830 getparam->value = NV_PCIE;
831 else
832 getparam->value = NV_PCI;
833 break;
834 case NOUVEAU_GETPARAM_FB_PHYSICAL:
835 getparam->value = dev_priv->fb_phys;
836 break;
837 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
838 getparam->value = dev_priv->gart_info.aper_base;
839 break;
840 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
841 if (dev->sg) {
842 getparam->value = (unsigned long)dev->sg->virtual;
843 } else {
844 NV_ERROR(dev, "Requested PCIGART address, "
845 "while no PCIGART was created\n");
846 return -EINVAL;
847 }
848 break;
849 case NOUVEAU_GETPARAM_FB_SIZE:
850 getparam->value = dev_priv->fb_available_size;
851 break;
852 case NOUVEAU_GETPARAM_AGP_SIZE:
853 getparam->value = dev_priv->gart_info.aper_size;
854 break;
855 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
856 getparam->value = dev_priv->vm_vram_base;
857 break;
69c9700b
MK		 858 case NOUVEAU_GETPARAM_GRAPH_UNITS:
859 /* NV40 and NV50 versions are quite different, but register
860 * address is the same. User is supposed to know the card
861 * family anyway... */
862 if (dev_priv->chipset >= 0x40) {
863 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
864 break;
865 }
866 /* FALLTHRU */
6ee73861
BS		 867 default:
868 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
869 return -EINVAL;
870 }
871
872 return 0;
873}
874
875int
876nouveau_ioctl_setparam(struct drm_device *dev, void *data,
877 struct drm_file *file_priv)
878{
879 struct drm_nouveau_setparam *setparam = data;
880
881 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
882
883 switch (setparam->param) {
884 default:
885 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
886 return -EINVAL;
887 }
888
889 return 0;
890}
891
892/* Wait until (value(reg) & mask) == val, up until timeout has hit */
893bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
894 uint32_t reg, uint32_t mask, uint32_t val)
895{
896 struct drm_nouveau_private *dev_priv = dev->dev_private;
897 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
898 uint64_t start = ptimer->read(dev);
899
900 do {
901 if ((nv_rd32(dev, reg) & mask) == val)
902 return true;
903 } while (ptimer->read(dev) - start < timeout);
904
905 return false;
906}
907
908/* Waits for PGRAPH to go completely idle */
909bool nouveau_wait_for_idle(struct drm_device *dev)
910{
911 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
912 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
913 nv_rd32(dev, NV04_PGRAPH_STATUS));
914 return false;
915 }
916
917 return true;
918}
919
Linux 6.x block layer and io_uring tree(s)