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Merge branch 'tracing/core' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
37#define DRIVER_PATCHLEVEL 15
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 struct ttm_bo_kmap_obj kmap;
80 struct list_head head;
81
82 /* protected by ttm_bo_reserve() */
83 struct drm_file *reserved_by;
84 struct list_head entry;
85 int pbbo_index;
86
87 struct nouveau_channel *channel;
88
89 bool mappable;
90 bool no_vm;
91
92 uint32_t tile_mode;
93 uint32_t tile_flags;
a0af9add 94 struct nouveau_tile_reg *tile;
6ee73861
BS		 95
96 struct drm_gem_object *gem;
97 struct drm_file *cpu_filp;
98 int pin_refcnt;
99};
100
101static inline struct nouveau_bo *
102nouveau_bo(struct ttm_buffer_object *bo)
103{
104 return container_of(bo, struct nouveau_bo, bo);
105}
106
107static inline struct nouveau_bo *
108nouveau_gem_object(struct drm_gem_object *gem)
109{
110 return gem ? gem->driver_private : NULL;
111}
112
113/* TODO: submit equivalent to TTM generic API upstream? */
114static inline void __iomem *
115nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
116{
117 bool is_iomem;
118 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
119 &nvbo->kmap, &is_iomem);
120 WARN_ON_ONCE(ioptr && !is_iomem);
121 return ioptr;
122}
123
124struct mem_block {
125 struct mem_block *next;
126 struct mem_block *prev;
127 uint64_t start;
128 uint64_t size;
129 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
130};
131
132enum nouveau_flags {
133 NV_NFORCE = 0x10000000,
134 NV_NFORCE2 = 0x20000000
135};
136
137#define NVOBJ_ENGINE_SW 0
138#define NVOBJ_ENGINE_GR 1
139#define NVOBJ_ENGINE_DISPLAY 2
140#define NVOBJ_ENGINE_INT 0xdeadbeef
141
142#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
143#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
144#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
145#define NVOBJ_FLAG_FAKE (1 << 3)
146struct nouveau_gpuobj {
147 struct list_head list;
148
149 struct nouveau_channel *im_channel;
150 struct mem_block *im_pramin;
151 struct nouveau_bo *im_backing;
152 uint32_t im_backing_start;
153 uint32_t *im_backing_suspend;
154 int im_bound;
155
156 uint32_t flags;
157 int refcount;
158
159 uint32_t engine;
160 uint32_t class;
161
162 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
163 void *priv;
164};
165
166struct nouveau_gpuobj_ref {
167 struct list_head list;
168
169 struct nouveau_gpuobj *gpuobj;
170 uint32_t instance;
171
172 struct nouveau_channel *channel;
173 int handle;
174};
175
176struct nouveau_channel {
177 struct drm_device *dev;
178 int id;
179
180 /* owner of this fifo */
181 struct drm_file *file_priv;
182 /* mapping of the fifo itself */
183 struct drm_local_map *map;
184
185 /* mapping of the regs controling the fifo */
186 void __iomem *user;
187 uint32_t user_get;
188 uint32_t user_put;
189
190 /* Fencing */
191 struct {
192 /* lock protects the pending list only */
193 spinlock_t lock;
194 struct list_head pending;
195 uint32_t sequence;
196 uint32_t sequence_ack;
197 uint32_t last_sequence_irq;
198 } fence;
199
200 /* DMA push buffer */
201 struct nouveau_gpuobj_ref *pushbuf;
202 struct nouveau_bo *pushbuf_bo;
203 uint32_t pushbuf_base;
204
205 /* Notifier memory */
206 struct nouveau_bo *notifier_bo;
207 struct mem_block *notifier_heap;
208
209 /* PFIFO context */
210 struct nouveau_gpuobj_ref *ramfc;
211 struct nouveau_gpuobj_ref *cache;
212
213 /* PGRAPH context */
214 /* XXX may be merge 2 pointers as private data ??? */
215 struct nouveau_gpuobj_ref *ramin_grctx;
216 void *pgraph_ctx;
217
218 /* NV50 VM */
219 struct nouveau_gpuobj *vm_pd;
220 struct nouveau_gpuobj_ref *vm_gart_pt;
221 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
222
223 /* Objects */
224 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
225 struct mem_block *ramin_heap; /* Private PRAMIN heap */
226 struct nouveau_gpuobj_ref *ramht; /* Hash table */
227 struct list_head ramht_refs; /* Objects referenced by RAMHT */
228
229 /* GPU object info for stuff used in-kernel (mm_enabled) */
230 uint32_t m2mf_ntfy;
231 uint32_t vram_handle;
232 uint32_t gart_handle;
233 bool accel_done;
234
235 /* Push buffer state (only for drm's channel on !mm_enabled) */
236 struct {
237 int max;
238 int free;
239 int cur;
240 int put;
241 /* access via pushbuf_bo */
242 } dma;
243
244 uint32_t sw_subchannel[8];
245
246 struct {
247 struct nouveau_gpuobj *vblsem;
248 uint32_t vblsem_offset;
249 uint32_t vblsem_rval;
250 struct list_head vbl_wait;
251 } nvsw;
252
253 struct {
254 bool active;
255 char name[32];
256 struct drm_info_list info;
257 } debugfs;
258};
259
260struct nouveau_instmem_engine {
261 void *priv;
262
263 int (*init)(struct drm_device *dev);
264 void (*takedown)(struct drm_device *dev);
265 int (*suspend)(struct drm_device *dev);
266 void (*resume)(struct drm_device *dev);
267
268 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
269 uint32_t *size);
270 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
272 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
273 void (*prepare_access)(struct drm_device *, bool write);
274 void (*finish_access)(struct drm_device *);
275};
276
277struct nouveau_mc_engine {
278 int (*init)(struct drm_device *dev);
279 void (*takedown)(struct drm_device *dev);
280};
281
282struct nouveau_timer_engine {
283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
285 uint64_t (*read)(struct drm_device *dev);
286};
287
288struct nouveau_fb_engine {
cb00f7c1
FJ		 289 int num_tiles;
290
6ee73861
BS		 291 int (*init)(struct drm_device *dev);
292 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 293
294 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
295 uint32_t size, uint32_t pitch);
6ee73861
BS		 296};
297
298struct nouveau_fifo_engine {
299 void *priv;
300
301 int channels;
302
303 int (*init)(struct drm_device *);
304 void (*takedown)(struct drm_device *);
305
306 void (*disable)(struct drm_device *);
307 void (*enable)(struct drm_device *);
308 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 309 bool (*cache_flush)(struct drm_device *dev);
310 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 311
312 int (*channel_id)(struct drm_device *);
313
314 int (*create_context)(struct nouveau_channel *);
315 void (*destroy_context)(struct nouveau_channel *);
316 int (*load_context)(struct nouveau_channel *);
317 int (*unload_context)(struct drm_device *);
318};
319
320struct nouveau_pgraph_object_method {
321 int id;
322 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
323 uint32_t data);
324};
325
326struct nouveau_pgraph_object_class {
327 int id;
328 bool software;
329 struct nouveau_pgraph_object_method *methods;
330};
331
332struct nouveau_pgraph_engine {
333 struct nouveau_pgraph_object_class *grclass;
334 bool accel_blocked;
335 void *ctxprog;
336 void *ctxvals;
054b93e4 337 int grctx_size;
6ee73861
BS		 338
339 int (*init)(struct drm_device *);
340 void (*takedown)(struct drm_device *);
341
342 void (*fifo_access)(struct drm_device *, bool);
343
344 struct nouveau_channel *(*channel)(struct drm_device *);
345 int (*create_context)(struct nouveau_channel *);
346 void (*destroy_context)(struct nouveau_channel *);
347 int (*load_context)(struct nouveau_channel *);
348 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 349
350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
351 uint32_t size, uint32_t pitch);
6ee73861
BS		 352};
353
354struct nouveau_engine {
355 struct nouveau_instmem_engine instmem;
356 struct nouveau_mc_engine mc;
357 struct nouveau_timer_engine timer;
358 struct nouveau_fb_engine fb;
359 struct nouveau_pgraph_engine graph;
360 struct nouveau_fifo_engine fifo;
361};
362
363struct nouveau_pll_vals {
364 union {
365 struct {
366#ifdef __BIG_ENDIAN
367 uint8_t N1, M1, N2, M2;
368#else
369 uint8_t M1, N1, M2, N2;
370#endif
371 };
372 struct {
373 uint16_t NM1, NM2;
374 } __attribute__((packed));
375 };
376 int log2P;
377
378 int refclk;
379};
380
381enum nv04_fp_display_regs {
382 FP_DISPLAY_END,
383 FP_TOTAL,
384 FP_CRTC,
385 FP_SYNC_START,
386 FP_SYNC_END,
387 FP_VALID_START,
388 FP_VALID_END
389};
390
391struct nv04_crtc_reg {
392 unsigned char MiscOutReg; /* */
393 uint8_t CRTC[0x9f];
394 uint8_t CR58[0x10];
395 uint8_t Sequencer[5];
396 uint8_t Graphics[9];
397 uint8_t Attribute[21];
398 unsigned char DAC[768]; /* Internal Colorlookuptable */
399
400 /* PCRTC regs */
401 uint32_t fb_start;
402 uint32_t crtc_cfg;
403 uint32_t cursor_cfg;
404 uint32_t gpio_ext;
405 uint32_t crtc_830;
406 uint32_t crtc_834;
407 uint32_t crtc_850;
408 uint32_t crtc_eng_ctrl;
409
410 /* PRAMDAC regs */
411 uint32_t nv10_cursync;
412 struct nouveau_pll_vals pllvals;
413 uint32_t ramdac_gen_ctrl;
414 uint32_t ramdac_630;
415 uint32_t ramdac_634;
416 uint32_t tv_setup;
417 uint32_t tv_vtotal;
418 uint32_t tv_vskew;
419 uint32_t tv_vsync_delay;
420 uint32_t tv_htotal;
421 uint32_t tv_hskew;
422 uint32_t tv_hsync_delay;
423 uint32_t tv_hsync_delay2;
424 uint32_t fp_horiz_regs[7];
425 uint32_t fp_vert_regs[7];
426 uint32_t dither;
427 uint32_t fp_control;
428 uint32_t dither_regs[6];
429 uint32_t fp_debug_0;
430 uint32_t fp_debug_1;
431 uint32_t fp_debug_2;
432 uint32_t fp_margin_color;
433 uint32_t ramdac_8c0;
434 uint32_t ramdac_a20;
435 uint32_t ramdac_a24;
436 uint32_t ramdac_a34;
437 uint32_t ctv_regs[38];
438};
439
440struct nv04_output_reg {
441 uint32_t output;
442 int head;
443};
444
445struct nv04_mode_state {
446 uint32_t bpp;
447 uint32_t width;
448 uint32_t height;
449 uint32_t interlace;
450 uint32_t repaint0;
451 uint32_t repaint1;
452 uint32_t screen;
453 uint32_t scale;
454 uint32_t dither;
455 uint32_t extra;
456 uint32_t fifo;
457 uint32_t pixel;
458 uint32_t horiz;
459 int arbitration0;
460 int arbitration1;
461 uint32_t pll;
462 uint32_t pllB;
463 uint32_t vpll;
464 uint32_t vpll2;
465 uint32_t vpllB;
466 uint32_t vpll2B;
467 uint32_t pllsel;
468 uint32_t sel_clk;
469 uint32_t general;
470 uint32_t crtcOwner;
471 uint32_t head;
472 uint32_t head2;
473 uint32_t cursorConfig;
474 uint32_t cursor0;
475 uint32_t cursor1;
476 uint32_t cursor2;
477 uint32_t timingH;
478 uint32_t timingV;
479 uint32_t displayV;
480 uint32_t crtcSync;
481
482 struct nv04_crtc_reg crtc_reg[2];
483};
484
485enum nouveau_card_type {
486 NV_04 = 0x00,
487 NV_10 = 0x10,
488 NV_20 = 0x20,
489 NV_30 = 0x30,
490 NV_40 = 0x40,
491 NV_50 = 0x50,
492};
493
494struct drm_nouveau_private {
495 struct drm_device *dev;
496 enum {
497 NOUVEAU_CARD_INIT_DOWN,
498 NOUVEAU_CARD_INIT_DONE,
499 NOUVEAU_CARD_INIT_FAILED
500 } init_state;
501
502 /* the card type, takes NV_* as values */
503 enum nouveau_card_type card_type;
504 /* exact chipset, derived from NV_PMC_BOOT_0 */
505 int chipset;
506 int flags;
507
508 void __iomem *mmio;
509 void __iomem *ramin;
510 uint32_t ramin_size;
511
ac8fb975
BS		 512 struct nouveau_bo *vga_ram;
513
6ee73861
BS		 514 struct workqueue_struct *wq;
515 struct work_struct irq_work;
516
517 struct list_head vbl_waiting;
518
519 struct {
520 struct ttm_global_reference mem_global_ref;
521 struct ttm_bo_global_ref bo_global_ref;
522 struct ttm_bo_device bdev;
523 spinlock_t bo_list_lock;
524 struct list_head bo_list;
525 atomic_t validate_sequence;
526 } ttm;
527
528 struct fb_info *fbdev_info;
529
530 int fifo_alloc_count;
531 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
532
533 struct nouveau_engine engine;
534 struct nouveau_channel *channel;
535
536 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
537 struct nouveau_gpuobj *ramht;
538 uint32_t ramin_rsvd_vram;
539 uint32_t ramht_offset;
540 uint32_t ramht_size;
541 uint32_t ramht_bits;
542 uint32_t ramfc_offset;
543 uint32_t ramfc_size;
544 uint32_t ramro_offset;
545 uint32_t ramro_size;
546
547 /* base physical adresses */
548 uint64_t fb_phys;
549 uint64_t fb_available_size;
550 uint64_t fb_mappable_pages;
551 uint64_t fb_aper_free;
552
553 struct {
554 enum {
555 NOUVEAU_GART_NONE = 0,
556 NOUVEAU_GART_AGP,
557 NOUVEAU_GART_SGDMA
558 } type;
559 uint64_t aper_base;
560 uint64_t aper_size;
561 uint64_t aper_free;
562
563 struct nouveau_gpuobj *sg_ctxdma;
564 struct page *sg_dummy_page;
565 dma_addr_t sg_dummy_bus;
566
567 /* nottm hack */
568 struct drm_ttm_backend *sg_be;
569 unsigned long sg_handle;
570 } gart_info;
571
a0af9add
FJ		 572 /* nv10-nv40 tiling regions */
573 struct {
574 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
575 spinlock_t lock;
576 } tile;
577
6ee73861
BS		 578 /* G8x/G9x virtual address space */
579 uint64_t vm_gart_base;
580 uint64_t vm_gart_size;
581 uint64_t vm_vram_base;
582 uint64_t vm_vram_size;
583 uint64_t vm_end;
584 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
585 int vm_vram_pt_nr;
76befb8c 586 uint64_t vram_sys_base;
6ee73861
BS		 587
588 /* the mtrr covering the FB */
589 int fb_mtrr;
590
591 struct mem_block *ramin_heap;
592
593 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
594 uint32_t ctx_table_size;
595 struct nouveau_gpuobj_ref *ctx_table;
596
597 struct list_head gpuobj_list;
598
599 struct nvbios VBIOS;
600 struct nouveau_bios_info *vbios;
601
602 struct nv04_mode_state mode_reg;
603 struct nv04_mode_state saved_reg;
604 uint32_t saved_vga_font[4][16384];
605 uint32_t crtc_owner;
606 uint32_t dac_users[4];
607
608 struct nouveau_suspend_resume {
609 uint32_t fifo_mode;
610 uint32_t graph_ctx_control;
611 uint32_t graph_state;
612 uint32_t *ramin_copy;
613 uint64_t ramin_size;
614 } susres;
615
616 struct backlight_device *backlight;
617 bool acpi_dsm;
618
619 struct nouveau_channel *evo;
620
621 struct {
622 struct dentry *channel_root;
623 } debugfs;
624};
625
626static inline struct drm_nouveau_private *
627nouveau_bdev(struct ttm_bo_device *bd)
628{
629 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
630}
631
632static inline int
633nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
634{
635 struct nouveau_bo *prev;
636
637 if (!pnvbo)
638 return -EINVAL;
639 prev = *pnvbo;
640
641 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
642 if (prev) {
643 struct ttm_buffer_object *bo = &prev->bo;
644
645 ttm_bo_unref(&bo);
646 }
647
648 return 0;
649}
650
651#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
652 struct drm_nouveau_private *nv = dev->dev_private; \
653 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
654 NV_ERROR(dev, "called without init\n"); \
655 return -EINVAL; \
656 } \
657} while (0)
658
659#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
660 struct drm_nouveau_private *nv = dev->dev_private; \
661 if (!nouveau_channel_owner(dev, (cl), (id))) { \
662 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
663 DRM_CURRENTPID, (id)); \
664 return -EPERM; \
665 } \
666 (ch) = nv->fifos[(id)]; \
667} while (0)
668
669/* nouveau_drv.c */
670extern int nouveau_noagp;
671extern int nouveau_duallink;
672extern int nouveau_uscript_lvds;
673extern int nouveau_uscript_tmds;
674extern int nouveau_vram_pushbuf;
675extern int nouveau_vram_notify;
676extern int nouveau_fbpercrtc;
677extern char *nouveau_tv_norm;
678extern int nouveau_reg_debug;
679extern char *nouveau_vbios;
054b93e4 680extern int nouveau_ctxfw;
a1470890 681extern int nouveau_ignorelid;
a32ed69d
MK		 682extern int nouveau_nofbaccel;
683extern int nouveau_noaccel;
6ee73861
BS		 684
685/* nouveau_state.c */
686extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
687extern int nouveau_load(struct drm_device *, unsigned long flags);
688extern int nouveau_firstopen(struct drm_device *);
689extern void nouveau_lastclose(struct drm_device *);
690extern int nouveau_unload(struct drm_device *);
691extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
692 struct drm_file *);
693extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
694 struct drm_file *);
695extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
696 uint32_t reg, uint32_t mask, uint32_t val);
697extern bool nouveau_wait_for_idle(struct drm_device *);
698extern int nouveau_card_init(struct drm_device *);
699extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
700 struct drm_file *);
701extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
702 struct drm_file *);
703extern int nouveau_ioctl_resume(struct drm_device *, void *data,
704 struct drm_file *);
705
706/* nouveau_mem.c */
707extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
708 uint64_t size);
709extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
710 uint64_t size, int align2,
711 struct drm_file *, int tail);
712extern void nouveau_mem_takedown(struct mem_block **heap);
713extern void nouveau_mem_free_block(struct mem_block *);
714extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
715extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
716extern int nouveau_mem_init(struct drm_device *);
717extern int nouveau_mem_init_agp(struct drm_device *);
718extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 719extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
720 uint32_t addr,
721 uint32_t size,
722 uint32_t pitch);
723extern void nv10_mem_expire_tiling(struct drm_device *dev,
724 struct nouveau_tile_reg *tile,
725 struct nouveau_fence *fence);
6ee73861
BS		 726extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
727 uint32_t size, uint32_t flags,
728 uint64_t phys);
729extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
730 uint32_t size);
731
732/* nouveau_notifier.c */
733extern int nouveau_notifier_init_channel(struct nouveau_channel *);
734extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
735extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
736 int cout, uint32_t *offset);
737extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
738extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
739 struct drm_file *);
740extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
741 struct drm_file *);
742
743/* nouveau_channel.c */
744extern struct drm_ioctl_desc nouveau_ioctls[];
745extern int nouveau_max_ioctl;
746extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
747extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
748 int channel);
749extern int nouveau_channel_alloc(struct drm_device *dev,
750 struct nouveau_channel **chan,
751 struct drm_file *file_priv,
752 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
753extern void nouveau_channel_free(struct nouveau_channel *);
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BS		 754
755/* nouveau_object.c */
756extern int nouveau_gpuobj_early_init(struct drm_device *);
757extern int nouveau_gpuobj_init(struct drm_device *);
758extern void nouveau_gpuobj_takedown(struct drm_device *);
759extern void nouveau_gpuobj_late_takedown(struct drm_device *);
760extern int nouveau_gpuobj_suspend(struct drm_device *dev);
761extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
762extern void nouveau_gpuobj_resume(struct drm_device *dev);
763extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
764 uint32_t vram_h, uint32_t tt_h);
765extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
766extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
767 uint32_t size, int align, uint32_t flags,
768 struct nouveau_gpuobj **);
769extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
770extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
771 uint32_t handle, struct nouveau_gpuobj *,
772 struct nouveau_gpuobj_ref **);
773extern int nouveau_gpuobj_ref_del(struct drm_device *,
774 struct nouveau_gpuobj_ref **);
775extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
776 struct nouveau_gpuobj_ref **ref_ret);
777extern int nouveau_gpuobj_new_ref(struct drm_device *,
778 struct nouveau_channel *alloc_chan,
779 struct nouveau_channel *ref_chan,
780 uint32_t handle, uint32_t size, int align,
781 uint32_t flags, struct nouveau_gpuobj_ref **);
782extern int nouveau_gpuobj_new_fake(struct drm_device *,
783 uint32_t p_offset, uint32_t b_offset,
784 uint32_t size, uint32_t flags,
785 struct nouveau_gpuobj **,
786 struct nouveau_gpuobj_ref**);
787extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
788 uint64_t offset, uint64_t size, int access,
789 int target, struct nouveau_gpuobj **);
790extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
791 uint64_t offset, uint64_t size,
792 int access, struct nouveau_gpuobj **,
793 uint32_t *o_ret);
794extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
795 struct nouveau_gpuobj **);
f03a314b
FJ		 796extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
797 struct nouveau_gpuobj **);
6ee73861
BS		 798extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
799 struct drm_file *);
800extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
801 struct drm_file *);
802
803/* nouveau_irq.c */
804extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
805extern void nouveau_irq_preinstall(struct drm_device *);
806extern int nouveau_irq_postinstall(struct drm_device *);
807extern void nouveau_irq_uninstall(struct drm_device *);
808
809/* nouveau_sgdma.c */
810extern int nouveau_sgdma_init(struct drm_device *);
811extern void nouveau_sgdma_takedown(struct drm_device *);
812extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
813 uint32_t *page);
814extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
815
816/* nouveau_debugfs.c */
817#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
818extern int nouveau_debugfs_init(struct drm_minor *);
819extern void nouveau_debugfs_takedown(struct drm_minor *);
820extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
821extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
822#else
823static inline int
824nouveau_debugfs_init(struct drm_minor *minor)
825{
826 return 0;
827}
828
829static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
830{
831}
832
833static inline int
834nouveau_debugfs_channel_init(struct nouveau_channel *chan)
835{
836 return 0;
837}
838
839static inline void
840nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
841{
842}
843#endif
844
845/* nouveau_dma.c */
75c99da6 846extern void nouveau_dma_pre_init(struct nouveau_channel *);
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BS		 847extern int nouveau_dma_init(struct nouveau_channel *);
848extern int nouveau_dma_wait(struct nouveau_channel *, int size);
849
850/* nouveau_acpi.c */
851#ifdef CONFIG_ACPI
852extern int nouveau_hybrid_setup(struct drm_device *dev);
853extern bool nouveau_dsm_probe(struct drm_device *dev);
854#else
855static inline int nouveau_hybrid_setup(struct drm_device *dev)
856{
857 return 0;
858}
859static inline bool nouveau_dsm_probe(struct drm_device *dev)
860{
861 return false;
862}
863#endif
864
865/* nouveau_backlight.c */
866#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
867extern int nouveau_backlight_init(struct drm_device *);
868extern void nouveau_backlight_exit(struct drm_device *);
869#else
870static inline int nouveau_backlight_init(struct drm_device *dev)
871{
872 return 0;
873}
874
875static inline void nouveau_backlight_exit(struct drm_device *dev) { }
876#endif
877
878/* nouveau_bios.c */
879extern int nouveau_bios_init(struct drm_device *);
880extern void nouveau_bios_takedown(struct drm_device *dev);
881extern int nouveau_run_vbios_init(struct drm_device *);
882extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
883 struct dcb_entry *);
884extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
885 enum dcb_gpio_tag);
886extern struct dcb_connector_table_entry *
887nouveau_bios_connector_entry(struct drm_device *, int index);
888extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
889 struct pll_lims *);
890extern int nouveau_bios_run_display_table(struct drm_device *,
891 struct dcb_entry *,
892 uint32_t script, int pxclk);
893extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
894 int *length);
895extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
896extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
897extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
898 bool *dl, bool *if_is_24bit);
899extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
900 int head, int pxclk);
901extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
902 enum LVDS_script, int pxclk);
903
904/* nouveau_ttm.c */
905int nouveau_ttm_global_init(struct drm_nouveau_private *);
906void nouveau_ttm_global_release(struct drm_nouveau_private *);
907int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
908
909/* nouveau_dp.c */
910int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
911 uint8_t *data, int data_nr);
912bool nouveau_dp_detect(struct drm_encoder *);
913bool nouveau_dp_link_train(struct drm_encoder *);
914
915/* nv04_fb.c */
916extern int nv04_fb_init(struct drm_device *);
917extern void nv04_fb_takedown(struct drm_device *);
918
919/* nv10_fb.c */
920extern int nv10_fb_init(struct drm_device *);
921extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 922extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
923 uint32_t, uint32_t);
6ee73861
BS		 924
925/* nv40_fb.c */
926extern int nv40_fb_init(struct drm_device *);
927extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 928extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
929 uint32_t, uint32_t);
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BS		 930
931/* nv04_fifo.c */
932extern int nv04_fifo_init(struct drm_device *);
933extern void nv04_fifo_disable(struct drm_device *);
934extern void nv04_fifo_enable(struct drm_device *);
935extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 936extern bool nv04_fifo_cache_flush(struct drm_device *);
937extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 938extern int nv04_fifo_channel_id(struct drm_device *);
939extern int nv04_fifo_create_context(struct nouveau_channel *);
940extern void nv04_fifo_destroy_context(struct nouveau_channel *);
941extern int nv04_fifo_load_context(struct nouveau_channel *);
942extern int nv04_fifo_unload_context(struct drm_device *);
943
944/* nv10_fifo.c */
945extern int nv10_fifo_init(struct drm_device *);
946extern int nv10_fifo_channel_id(struct drm_device *);
947extern int nv10_fifo_create_context(struct nouveau_channel *);
948extern void nv10_fifo_destroy_context(struct nouveau_channel *);
949extern int nv10_fifo_load_context(struct nouveau_channel *);
950extern int nv10_fifo_unload_context(struct drm_device *);
951
952/* nv40_fifo.c */
953extern int nv40_fifo_init(struct drm_device *);
954extern int nv40_fifo_create_context(struct nouveau_channel *);
955extern void nv40_fifo_destroy_context(struct nouveau_channel *);
956extern int nv40_fifo_load_context(struct nouveau_channel *);
957extern int nv40_fifo_unload_context(struct drm_device *);
958
959/* nv50_fifo.c */
960extern int nv50_fifo_init(struct drm_device *);
961extern void nv50_fifo_takedown(struct drm_device *);
962extern int nv50_fifo_channel_id(struct drm_device *);
963extern int nv50_fifo_create_context(struct nouveau_channel *);
964extern void nv50_fifo_destroy_context(struct nouveau_channel *);
965extern int nv50_fifo_load_context(struct nouveau_channel *);
966extern int nv50_fifo_unload_context(struct drm_device *);
967
968/* nv04_graph.c */
969extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
970extern int nv04_graph_init(struct drm_device *);
971extern void nv04_graph_takedown(struct drm_device *);
972extern void nv04_graph_fifo_access(struct drm_device *, bool);
973extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
974extern int nv04_graph_create_context(struct nouveau_channel *);
975extern void nv04_graph_destroy_context(struct nouveau_channel *);
976extern int nv04_graph_load_context(struct nouveau_channel *);
977extern int nv04_graph_unload_context(struct drm_device *);
978extern void nv04_graph_context_switch(struct drm_device *);
979
980/* nv10_graph.c */
981extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
982extern int nv10_graph_init(struct drm_device *);
983extern void nv10_graph_takedown(struct drm_device *);
984extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
985extern int nv10_graph_create_context(struct nouveau_channel *);
986extern void nv10_graph_destroy_context(struct nouveau_channel *);
987extern int nv10_graph_load_context(struct nouveau_channel *);
988extern int nv10_graph_unload_context(struct drm_device *);
989extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 990extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
991 uint32_t, uint32_t);
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BS		 992
993/* nv20_graph.c */
994extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
995extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
996extern int nv20_graph_create_context(struct nouveau_channel *);
997extern void nv20_graph_destroy_context(struct nouveau_channel *);
998extern int nv20_graph_load_context(struct nouveau_channel *);
999extern int nv20_graph_unload_context(struct drm_device *);
1000extern int nv20_graph_init(struct drm_device *);
1001extern void nv20_graph_takedown(struct drm_device *);
1002extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1003extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1004 uint32_t, uint32_t);
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BS		 1005
1006/* nv40_graph.c */
1007extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1008extern int nv40_graph_init(struct drm_device *);
1009extern void nv40_graph_takedown(struct drm_device *);
1010extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1011extern int nv40_graph_create_context(struct nouveau_channel *);
1012extern void nv40_graph_destroy_context(struct nouveau_channel *);
1013extern int nv40_graph_load_context(struct nouveau_channel *);
1014extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1015extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1016extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1017 uint32_t, uint32_t);
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BS		 1018
1019/* nv50_graph.c */
1020extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1021extern int nv50_graph_init(struct drm_device *);
1022extern void nv50_graph_takedown(struct drm_device *);
1023extern void nv50_graph_fifo_access(struct drm_device *, bool);
1024extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1025extern int nv50_graph_create_context(struct nouveau_channel *);
1026extern void nv50_graph_destroy_context(struct nouveau_channel *);
1027extern int nv50_graph_load_context(struct nouveau_channel *);
1028extern int nv50_graph_unload_context(struct drm_device *);
1029extern void nv50_graph_context_switch(struct drm_device *);
1030
054b93e4
BS		 1031/* nouveau_grctx.c */
1032extern int nouveau_grctx_prog_load(struct drm_device *);
1033extern void nouveau_grctx_vals_load(struct drm_device *,
1034 struct nouveau_gpuobj *);
1035extern void nouveau_grctx_fini(struct drm_device *);
1036
6ee73861
BS		 1037/* nv04_instmem.c */
1038extern int nv04_instmem_init(struct drm_device *);
1039extern void nv04_instmem_takedown(struct drm_device *);
1040extern int nv04_instmem_suspend(struct drm_device *);
1041extern void nv04_instmem_resume(struct drm_device *);
1042extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1043 uint32_t *size);
1044extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1045extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1046extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1047extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1048extern void nv04_instmem_finish_access(struct drm_device *);
1049
1050/* nv50_instmem.c */
1051extern int nv50_instmem_init(struct drm_device *);
1052extern void nv50_instmem_takedown(struct drm_device *);
1053extern int nv50_instmem_suspend(struct drm_device *);
1054extern void nv50_instmem_resume(struct drm_device *);
1055extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1056 uint32_t *size);
1057extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1058extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1059extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1060extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1061extern void nv50_instmem_finish_access(struct drm_device *);
1062
1063/* nv04_mc.c */
1064extern int nv04_mc_init(struct drm_device *);
1065extern void nv04_mc_takedown(struct drm_device *);
1066
1067/* nv40_mc.c */
1068extern int nv40_mc_init(struct drm_device *);
1069extern void nv40_mc_takedown(struct drm_device *);
1070
1071/* nv50_mc.c */
1072extern int nv50_mc_init(struct drm_device *);
1073extern void nv50_mc_takedown(struct drm_device *);
1074
1075/* nv04_timer.c */
1076extern int nv04_timer_init(struct drm_device *);
1077extern uint64_t nv04_timer_read(struct drm_device *);
1078extern void nv04_timer_takedown(struct drm_device *);
1079
1080extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1081 unsigned long arg);
1082
1083/* nv04_dac.c */
1084extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
11d6eb2a 1085extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1086extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1087extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1088
1089/* nv04_dfp.c */
1090extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1091extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1092extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1093 int head, bool dl);
1094extern void nv04_dfp_disable(struct drm_device *dev, int head);
1095extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1096
1097/* nv04_tv.c */
1098extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1099extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1100
1101/* nv17_tv.c */
1102extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
6ee73861
BS		 1103
1104/* nv04_display.c */
1105extern int nv04_display_create(struct drm_device *);
1106extern void nv04_display_destroy(struct drm_device *);
1107extern void nv04_display_restore(struct drm_device *);
1108
1109/* nv04_crtc.c */
1110extern int nv04_crtc_create(struct drm_device *, int index);
1111
1112/* nouveau_bo.c */
1113extern struct ttm_bo_driver nouveau_bo_driver;
1114extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1115 int size, int align, uint32_t flags,
1116 uint32_t tile_mode, uint32_t tile_flags,
1117 bool no_vm, bool mappable, struct nouveau_bo **);
1118extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1119extern int nouveau_bo_unpin(struct nouveau_bo *);
1120extern int nouveau_bo_map(struct nouveau_bo *);
1121extern void nouveau_bo_unmap(struct nouveau_bo *);
1122extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1123extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1124extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1125extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1126extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1127
1128/* nouveau_fence.c */
1129struct nouveau_fence;
1130extern int nouveau_fence_init(struct nouveau_channel *);
1131extern void nouveau_fence_fini(struct nouveau_channel *);
1132extern void nouveau_fence_update(struct nouveau_channel *);
1133extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1134 bool emit);
1135extern int nouveau_fence_emit(struct nouveau_fence *);
1136struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1137extern bool nouveau_fence_signalled(void *obj, void *arg);
1138extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1139extern int nouveau_fence_flush(void *obj, void *arg);
1140extern void nouveau_fence_unref(void **obj);
1141extern void *nouveau_fence_ref(void *obj);
1142extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1143
1144/* nouveau_gem.c */
1145extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1146 int size, int align, uint32_t flags,
1147 uint32_t tile_mode, uint32_t tile_flags,
1148 bool no_vm, bool mappable, struct nouveau_bo **);
1149extern int nouveau_gem_object_new(struct drm_gem_object *);
1150extern void nouveau_gem_object_del(struct drm_gem_object *);
1151extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1152 struct drm_file *);
1153extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1154 struct drm_file *);
1155extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1156 struct drm_file *);
1157extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1158 struct drm_file *);
1159extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1160 struct drm_file *);
1161extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1162 struct drm_file *);
1163extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1164 struct drm_file *);
1165extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1166 struct drm_file *);
1167extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1168 struct drm_file *);
1169extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1170 struct drm_file *);
1171
1172/* nv17_gpio.c */
1173int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1174int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1175
1176#ifndef ioread32_native
1177#ifdef __BIG_ENDIAN
1178#define ioread16_native ioread16be
1179#define iowrite16_native iowrite16be
1180#define ioread32_native ioread32be
1181#define iowrite32_native iowrite32be
1182#else /* def __BIG_ENDIAN */
1183#define ioread16_native ioread16
1184#define iowrite16_native iowrite16
1185#define ioread32_native ioread32
1186#define iowrite32_native iowrite32
1187#endif /* def __BIG_ENDIAN else */
1188#endif /* !ioread32_native */
1189
1190/* channel control reg access */
1191static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1192{
1193 return ioread32_native(chan->user + reg);
1194}
1195
1196static inline void nvchan_wr32(struct nouveau_channel *chan,
1197 unsigned reg, u32 val)
1198{
1199 iowrite32_native(val, chan->user + reg);
1200}
1201
1202/* register access */
1203static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1204{
1205 struct drm_nouveau_private *dev_priv = dev->dev_private;
1206 return ioread32_native(dev_priv->mmio + reg);
1207}
1208
1209static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1210{
1211 struct drm_nouveau_private *dev_priv = dev->dev_private;
1212 iowrite32_native(val, dev_priv->mmio + reg);
1213}
1214
1215static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1216{
1217 struct drm_nouveau_private *dev_priv = dev->dev_private;
1218 return ioread8(dev_priv->mmio + reg);
1219}
1220
1221static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1222{
1223 struct drm_nouveau_private *dev_priv = dev->dev_private;
1224 iowrite8(val, dev_priv->mmio + reg);
1225}
1226
1227#define nv_wait(reg, mask, val) \
1228 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1229
1230/* PRAMIN access */
1231static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1232{
1233 struct drm_nouveau_private *dev_priv = dev->dev_private;
1234 return ioread32_native(dev_priv->ramin + offset);
1235}
1236
1237static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1238{
1239 struct drm_nouveau_private *dev_priv = dev->dev_private;
1240 iowrite32_native(val, dev_priv->ramin + offset);
1241}
1242
1243/* object access */
1244static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1245 unsigned index)
1246{
1247 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1248}
1249
1250static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1251 unsigned index, u32 val)
1252{
1253 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1254}
1255
1256/*
1257 * Logging
1258 * Argument d is (struct drm_device *).
1259 */
1260#define NV_PRINTK(level, d, fmt, arg...) \
1261 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1262 pci_name(d->pdev), ##arg)
1263#ifndef NV_DEBUG_NOTRACE
1264#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1265 if (drm_debug & DRM_UT_DRIVER) { \
1266 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1267 __LINE__, ##arg); \
1268 } \
1269} while (0)
1270#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1271 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1272 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1273 __LINE__, ##arg); \
1274 } \
1275} while (0)
1276#else
1277#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1278 if (drm_debug & DRM_UT_DRIVER) \
1279 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1280} while (0)
1281#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1282 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1283 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1284} while (0)
1285#endif
1286#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1287#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1288#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1289#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1290#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1291
1292/* nouveau_reg_debug bitmask */
1293enum {
1294 NOUVEAU_REG_DEBUG_MC = 0x1,
1295 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1296 NOUVEAU_REG_DEBUG_FB = 0x4,
1297 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1298 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1299 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1300 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1301 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1302 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1303 NOUVEAU_REG_DEBUG_EVO = 0x200,
1304};
1305
1306#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1307 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1308 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1309} while (0)
1310
1311static inline bool
1312nv_two_heads(struct drm_device *dev)
1313{
1314 struct drm_nouveau_private *dev_priv = dev->dev_private;
1315 const int impl = dev->pci_device & 0x0ff0;
1316
1317 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1318 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1319 return true;
1320
1321 return false;
1322}
1323
1324static inline bool
1325nv_gf4_disp_arch(struct drm_device *dev)
1326{
1327 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1328}
1329
1330static inline bool
1331nv_two_reg_pll(struct drm_device *dev)
1332{
1333 struct drm_nouveau_private *dev_priv = dev->dev_private;
1334 const int impl = dev->pci_device & 0x0ff0;
1335
1336 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1337 return true;
1338 return false;
1339}
1340
f03a314b
FJ		 1341#define NV_SW 0x0000506e
1342#define NV_SW_DMA_SEMAPHORE 0x00000060
1343#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1344#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1345#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1346#define NV_SW_DMA_VBLSEM 0x0000018c
1347#define NV_SW_VBLSEM_OFFSET 0x00000400
1348#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1349#define NV_SW_VBLSEM_RELEASE 0x00000408
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BS		 1350
1351#endif /* __NOUVEAU_DRV_H__ */
Linux 6.x block layer and io_uring tree(s)