[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_drv.c

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/console.h>
#include <linux/module.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
#include "nouveau_agp.h"
#include "nouveau_abi16.h"
#include "nouveau_hw.h"
#include "nouveau_fb.h"
#include "nouveau_fbcon.h"
#include "nouveau_pm.h"
#include <engine/fifo.h>
#include "nv50_display.h"

#include "drm_pciids.h"

MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
int nouveau_modeset = -1;
module_param_named(modeset, nouveau_modeset, int, 0400);

MODULE_PARM_DESC(vbios, "Override default VBIOS location");
char *nouveau_vbios;
module_param_named(vbios, nouveau_vbios, charp, 0400);

MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
int nouveau_vram_notify = 0;
module_param_named(vram_notify, nouveau_vram_notify, int, 0400);

MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
char *nouveau_vram_type;
module_param_named(vram_type, nouveau_vram_type, charp, 0400);

MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
int nouveau_duallink = 1;
module_param_named(duallink, nouveau_duallink, int, 0400);

MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
int nouveau_uscript_lvds = -1;
module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);

MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
int nouveau_uscript_tmds = -1;
module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);

MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
int nouveau_ignorelid = 0;
module_param_named(ignorelid, nouveau_ignorelid, int, 0400);

MODULE_PARM_DESC(noaccel, "Disable all acceleration");
int nouveau_noaccel = -1;
module_param_named(noaccel, nouveau_noaccel, int, 0400);

MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
int nouveau_nofbaccel = 0;
module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);

MODULE_PARM_DESC(force_post, "Force POST");
int nouveau_force_post = 0;
module_param_named(force_post, nouveau_force_post, int, 0400);

MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
int nouveau_override_conntype = 0;
module_param_named(override_conntype, nouveau_override_conntype, int, 0400);

MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
int nouveau_tv_disable = 0;
module_param_named(tv_disable, nouveau_tv_disable, int, 0400);

MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
		 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
		 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
		 "\t\tDefault: PAL\n"
		 "\t\t*NOTE* Ignored for cards with external TV encoders.");
char *nouveau_tv_norm;
module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);

MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
		"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
		"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
		"\t\t0x100 vgaattr, 0x200 EVO (G80+)");
int nouveau_reg_debug;
module_param_named(reg_debug, nouveau_reg_debug, int, 0600);

MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
char *nouveau_perflvl;
module_param_named(perflvl, nouveau_perflvl, charp, 0400);

MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
int nouveau_perflvl_wr;
module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);

MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
int nouveau_msi;
module_param_named(msi, nouveau_msi, int, 0400);

MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
int nouveau_ctxfw;
module_param_named(ctxfw, nouveau_ctxfw, int, 0400);

MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
int nouveau_mxmdcb = 1;
module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);

int nouveau_fbpercrtc;
#if 0
module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
#endif

static struct pci_device_id pciidlist[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{}
};

MODULE_DEVICE_TABLE(pci, pciidlist);

static struct drm_driver driver;

static int __devinit
nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	return drm_get_pci_dev(pdev, ent, &driver);
}

static void
nouveau_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

int
nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct nouveau_channel *chan;
	struct drm_crtc *crtc;
	int ret, i, e;

	if (pm_state.event == PM_EVENT_PRETHAW)
		return 0;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	NV_INFO(dev, "Disabling display...\n");
	nouveau_display_fini(dev);

	NV_INFO(dev, "Disabling fbcon...\n");
	nouveau_fbcon_set_suspend(dev, 1);

	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_unpin(nouveau_fb->nvbo);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nouveau_bo_unmap(nv_crtc->cursor.nvbo);
		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	}

	NV_INFO(dev, "Evicting buffers...\n");
	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);

	NV_INFO(dev, "Idling channels...\n");
	for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
		chan = dev_priv->channels.ptr[i];

		if (chan && chan->pushbuf_bo)
			nouveau_channel_idle(chan);
	}

	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
		if (!dev_priv->eng[e])
			continue;

		ret = dev_priv->eng[e]->fini(dev, e, true);
		if (ret) {
			NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
			goto out_abort;
		}
	}

	ret = pinstmem->suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		goto out_abort;
	}

	NV_INFO(dev, "Suspending GPU objects...\n");
	ret = nouveau_gpuobj_suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		pinstmem->resume(dev);
		goto out_abort;
	}

	nouveau_agp_fini(dev);

	NV_INFO(dev, "And we're gone!\n");
	pci_save_state(pdev);
	if (pm_state.event == PM_EVENT_SUSPEND) {
		pci_disable_device(pdev);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	return 0;

out_abort:
	NV_INFO(dev, "Re-enabling acceleration..\n");
	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
		if (dev_priv->eng[e])
			dev_priv->eng[e]->init(dev, e);
	}
	return ret;
}

int
nouveau_pci_resume(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	struct drm_crtc *crtc;
	int ret, i;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	NV_INFO(dev, "We're back, enabling device...\n");
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	if (pci_enable_device(pdev))
		return -1;
	pci_set_master(dev->pdev);

	/* Make sure the AGP controller is in a consistent state */
	nouveau_agp_reset(dev);

	/* Make the CRTCs accessible */
	engine->display.early_init(dev);

	NV_INFO(dev, "POSTing device...\n");
	ret = nouveau_run_vbios_init(dev);
	if (ret)
		return ret;

	nouveau_agp_init(dev);

	NV_INFO(dev, "Restoring GPU objects...\n");
	nouveau_gpuobj_resume(dev);

	NV_INFO(dev, "Reinitialising engines...\n");
	engine->instmem.resume(dev);
	engine->mc.init(dev);
	engine->timer.init(dev);
	engine->fb.init(dev);
	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
		if (dev_priv->eng[i])
			dev_priv->eng[i]->init(dev, i);
	}

	nouveau_irq_postinstall(dev);

	/* Re-write SKIPS, they'll have been lost over the suspend */
	if (nouveau_vram_pushbuf) {
		struct nouveau_channel *chan;
		int j;

		for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
			chan = dev_priv->channels.ptr[i];
			if (!chan || !chan->pushbuf_bo)
				continue;

			for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
				nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
		}
	}

	nouveau_pm_resume(dev);

	NV_INFO(dev, "Restoring mode...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
		if (!ret)
			ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
		if (ret)
			NV_ERROR(dev, "Could not pin/map cursor.\n");
	}

	nouveau_fbcon_set_suspend(dev, 0);
	nouveau_fbcon_zfill_all(dev);

	nouveau_display_init(dev);

	/* Force CLUT to get re-loaded during modeset */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nv_crtc->lut.depth = 0;
	}

	drm_helper_resume_force_mode(dev);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
		u32 offset = nv_crtc->cursor.nvbo->bo.offset;

		nv_crtc->cursor.set_offset(nv_crtc, offset);
		nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
						 nv_crtc->cursor_saved_y);
	}

	return 0;
}

static struct drm_ioctl_desc nouveau_ioctls[] = {
	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
};

static const struct file_operations nouveau_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = nouveau_ttm_mmap,
	.poll = drm_poll,
	.fasync = drm_fasync,
	.read = drm_read,
#if defined(CONFIG_COMPAT)
	.compat_ioctl = nouveau_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

static struct drm_driver driver = {
	.driver_features =
		DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
		DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
		DRIVER_MODESET | DRIVER_PRIME,
	.load = nouveau_load,
	.firstopen = nouveau_firstopen,
	.lastclose = nouveau_lastclose,
	.unload = nouveau_unload,
	.open = nouveau_open,
	.preclose = nouveau_preclose,
	.postclose = nouveau_postclose,
#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	.debugfs_init = nouveau_debugfs_init,
	.debugfs_cleanup = nouveau_debugfs_takedown,
#endif
	.irq_preinstall = nouveau_irq_preinstall,
	.irq_postinstall = nouveau_irq_postinstall,
	.irq_uninstall = nouveau_irq_uninstall,
	.irq_handler = nouveau_irq_handler,
	.get_vblank_counter = drm_vblank_count,
	.enable_vblank = nouveau_vblank_enable,
	.disable_vblank = nouveau_vblank_disable,
	.ioctls = nouveau_ioctls,
	.fops = &nouveau_driver_fops,

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = nouveau_gem_prime_export,
	.gem_prime_import = nouveau_gem_prime_import,

	.gem_init_object = nouveau_gem_object_new,
	.gem_free_object = nouveau_gem_object_del,
	.gem_open_object = nouveau_gem_object_open,
	.gem_close_object = nouveau_gem_object_close,

	.dumb_create = nouveau_display_dumb_create,
	.dumb_map_offset = nouveau_display_dumb_map_offset,
	.dumb_destroy = nouveau_display_dumb_destroy,

	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
#ifdef GIT_REVISION
	.date = GIT_REVISION,
#else
	.date = DRIVER_DATE,
#endif
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
};

static struct pci_driver nouveau_pci_driver = {
		.name = DRIVER_NAME,
		.id_table = pciidlist,
		.probe = nouveau_pci_probe,
		.remove = nouveau_pci_remove,
		.suspend = nouveau_pci_suspend,
		.resume = nouveau_pci_resume
};

static int __init nouveau_init(void)
{
	driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);

	if (nouveau_modeset == -1) {
#ifdef CONFIG_VGA_CONSOLE
		if (vgacon_text_force())
			nouveau_modeset = 0;
		else
#endif
			nouveau_modeset = 1;
	}

	if (!nouveau_modeset)
		return 0;

	nouveau_register_dsm_handler();
	return drm_pci_init(&driver, &nouveau_pci_driver);
}

static void __exit nouveau_exit(void)
{
	if (!nouveau_modeset)
		return;

	drm_pci_exit(&driver, &nouveau_pci_driver);
	nouveau_unregister_dsm_handler();
}

module_init(nouveau_init);
module_exit(nouveau_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include <linux/console.h>
e0cd3608	26	#include <linux/module.h>
6ee73861 BS	27
	28	#include "drmP.h"
	29	#include "drm.h"
	30	#include "drm_crtc_helper.h"
	31	#include "nouveau_drv.h"
aa4cc5d2	32	#include "nouveau_agp.h"
2a259a3d	33	#include "nouveau_abi16.h"
6ee73861 BS	34	#include "nouveau_hw.h"
	35	#include "nouveau_fb.h"
	36	#include "nouveau_fbcon.h"
64f1c11a	37	#include "nouveau_pm.h"
02a841d4	38	#include <engine/fifo.h>
6ee73861 BS	39	#include "nv50_display.h"
	40
	41	#include "drm_pciids.h"
	42
6ee73861	43	MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
03bc9675	44	int nouveau_modeset = -1;
6ee73861 BS	45	module_param_named(modeset, nouveau_modeset, int, 0400);
	46
	47	MODULE_PARM_DESC(vbios, "Override default VBIOS location");
	48	char *nouveau_vbios;
	49	module_param_named(vbios, nouveau_vbios, charp, 0400);
	50
	51	MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
	52	int nouveau_vram_pushbuf;
	53	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	54
	55	MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
2dfe36b1	56	int nouveau_vram_notify = 0;
6ee73861 BS	57	module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
6ee73861 BS	58
7ad2d31c BS	59	MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
	60	char *nouveau_vram_type;
	61	module_param_named(vram_type, nouveau_vram_type, charp, 0400);
	62
6ee73861 BS	63	MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
	64	int nouveau_duallink = 1;
	65	module_param_named(duallink, nouveau_duallink, int, 0400);
	66
	67	MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
	68	int nouveau_uscript_lvds = -1;
	69	module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
	70
	71	MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
	72	int nouveau_uscript_tmds = -1;
	73	module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
	74
a1470890 BS	75	MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
	76	int nouveau_ignorelid = 0;
	77	module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
	78
81e2d422	79	MODULE_PARM_DESC(noaccel, "Disable all acceleration");
aba99a84	80	int nouveau_noaccel = -1;
a32ed69d MK	81	module_param_named(noaccel, nouveau_noaccel, int, 0400);
a32ed69d MK	82
81e2d422	83	MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
a32ed69d MK	84	int nouveau_nofbaccel = 0;
	85	module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
	86
0cba1b76 MK	87	MODULE_PARM_DESC(force_post, "Force POST");
	88	int nouveau_force_post = 0;
	89	module_param_named(force_post, nouveau_force_post, int, 0400);
	90
da647d5b BS	91	MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
	92	int nouveau_override_conntype = 0;
	93	module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
	94
1a5f985c	95	MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
f4053509 BS	96	int nouveau_tv_disable = 0;
	97	module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
	98
6ee73861 BS	99	MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
	100	"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
	101	"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
	102	"\t\tDefault: PAL\n"
	103	"\t\tNOTE Ignored for cards with external TV encoders.");
	104	char *nouveau_tv_norm;
	105	module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
	106
	107	MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
	108	"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
	109	"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
1a5f985c	110	"\t\t0x100 vgaattr, 0x200 EVO (G80+)");
6ee73861 BS	111	int nouveau_reg_debug;
	112	module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
	113
1a5f985c	114	MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
6f876986 BS	115	char *nouveau_perflvl;
	116	module_param_named(perflvl, nouveau_perflvl, charp, 0400);
	117
1a5f985c	118	MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
6f876986 BS	119	int nouveau_perflvl_wr;
	120	module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
	121
1a5f985c	122	MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
35fa2f2a BS	123	int nouveau_msi;
	124	module_param_named(msi, nouveau_msi, int, 0400);
	125
1a5f985c	126	MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
0411de85 BS	127	int nouveau_ctxfw;
	128	module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
	129
1a5f985c	130	MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
b4c26818 BS	131	int nouveau_mxmdcb = 1;
	132	module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
	133
6ee73861 BS	134	int nouveau_fbpercrtc;
	135	#if 0
	136	module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
	137	#endif
	138
	139	static struct pci_device_id pciidlist[] = {
	140	{
	141	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	142	.class = PCI_BASE_CLASS_DISPLAY << 16,
	143	.class_mask = 0xff << 16,
	144	},
	145	{
	146	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
	147	.class = PCI_BASE_CLASS_DISPLAY << 16,
	148	.class_mask = 0xff << 16,
	149	},
	150	{}
	151	};
	152
	153	MODULE_DEVICE_TABLE(pci, pciidlist);
	154
	155	static struct drm_driver driver;
	156
	157	static int __devinit
	158	nouveau_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	159	{
dcdb1674	160	return drm_get_pci_dev(pdev, ent, &driver);
6ee73861 BS	161	}
	162
	163	static void
	164	nouveau_pci_remove(struct pci_dev *pdev)
	165	{
	166	struct drm_device *dev = pci_get_drvdata(pdev);
	167
	168	drm_put_dev(dev);
	169	}
	170
6a9ee8af	171	int
6ee73861 BS	172	nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
	173	{
	174	struct drm_device *dev = pci_get_drvdata(pdev);
	175	struct drm_nouveau_private *dev_priv = dev->dev_private;
	176	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
c420b2dc	177	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
6ee73861 BS	178	struct nouveau_channel *chan;
6ee73861 BS	179	struct drm_crtc *crtc;
92abe749	180	int ret, i, e;
6ee73861	181
6ee73861 BS	182	if (pm_state.event == PM_EVENT_PRETHAW)
	183	return 0;
	184
5bcf719b DA	185	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	186	return 0;
	187
f62b27db BS	188	NV_INFO(dev, "Disabling display...\n");
f62b27db BS	189	nouveau_display_fini(dev);
4bfb94a1	190
cf41d53b BS	191	NV_INFO(dev, "Disabling fbcon...\n");
cf41d53b BS	192	nouveau_fbcon_set_suspend(dev, 1);
6ee73861	193
81441570	194	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
6ee73861 BS	195	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	196	struct nouveau_framebuffer *nouveau_fb;
	197
	198	nouveau_fb = nouveau_framebuffer(crtc->fb);
	199	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	200	continue;
	201
	202	nouveau_bo_unpin(nouveau_fb->nvbo);
	203	}
	204
b334f2b3 MM	205	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	206	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	207
	208	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
	209	nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	210	}
	211
6ee73861 BS	212	NV_INFO(dev, "Evicting buffers...\n");
	213	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
	214
	215	NV_INFO(dev, "Idling channels...\n");
c420b2dc	216	for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
cff5c133	217	chan = dev_priv->channels.ptr[i];
6ee73861	218
6dccd311 FJ	219	if (chan && chan->pushbuf_bo)
6dccd311 FJ	220	nouveau_channel_idle(chan);
6ee73861 BS	221	}
6ee73861 BS	222
92abe749	223	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
6c320fef BS	224	if (!dev_priv->eng[e])
	225	continue;
	226
	227	ret = dev_priv->eng[e]->fini(dev, e, true);
	228	if (ret) {
13f90122	229	NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
6c320fef	230	goto out_abort;
92abe749 BS	231	}
92abe749 BS	232	}
6ee73861	233
dc1e5c0d	234	ret = pinstmem->suspend(dev);
6ee73861 BS	235	if (ret) {
	236	NV_ERROR(dev, "... failed: %d\n", ret);
	237	goto out_abort;
	238	}
	239
dc1e5c0d BS	240	NV_INFO(dev, "Suspending GPU objects...\n");
dc1e5c0d BS	241	ret = nouveau_gpuobj_suspend(dev);
6ee73861 BS	242	if (ret) {
6ee73861 BS	243	NV_ERROR(dev, "... failed: %d\n", ret);
dc1e5c0d	244	pinstmem->resume(dev);
6ee73861 BS	245	goto out_abort;
	246	}
	247
aa4cc5d2 BS	248	nouveau_agp_fini(dev);
aa4cc5d2 BS	249
6ee73861 BS	250	NV_INFO(dev, "And we're gone!\n");
	251	pci_save_state(pdev);
	252	if (pm_state.event == PM_EVENT_SUSPEND) {
	253	pci_disable_device(pdev);
	254	pci_set_power_state(pdev, PCI_D3hot);
	255	}
	256
6ee73861 BS	257	return 0;
	258
	259	out_abort:
	260	NV_INFO(dev, "Re-enabling acceleration..\n");
92abe749 BS	261	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
	262	if (dev_priv->eng[e])
	263	dev_priv->eng[e]->init(dev, e);
	264	}
6ee73861 BS	265	return ret;
	266	}
	267
6a9ee8af	268	int
6ee73861 BS	269	nouveau_pci_resume(struct pci_dev *pdev)
	270	{
	271	struct drm_device *dev = pci_get_drvdata(pdev);
c420b2dc	272	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
6ee73861 BS	273	struct drm_nouveau_private *dev_priv = dev->dev_private;
	274	struct nouveau_engine *engine = &dev_priv->engine;
	275	struct drm_crtc *crtc;
6ee73861 BS	276	int ret, i;
6ee73861 BS	277
5bcf719b DA	278	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	279	return 0;
	280
6ee73861 BS	281	NV_INFO(dev, "We're back, enabling device...\n");
	282	pci_set_power_state(pdev, PCI_D0);
	283	pci_restore_state(pdev);
	284	if (pci_enable_device(pdev))
	285	return -1;
	286	pci_set_master(dev->pdev);
	287
e04d8e82	288	/* Make sure the AGP controller is in a consistent state */
aa4cc5d2	289	nouveau_agp_reset(dev);
e04d8e82	290
c88c2e06 FJ	291	/* Make the CRTCs accessible */
	292	engine->display.early_init(dev);
	293
6ee73861 BS	294	NV_INFO(dev, "POSTing device...\n");
	295	ret = nouveau_run_vbios_init(dev);
	296	if (ret)
	297	return ret;
	298
aa4cc5d2	299	nouveau_agp_init(dev);
6ee73861	300
dc1e5c0d BS	301	NV_INFO(dev, "Restoring GPU objects...\n");
	302	nouveau_gpuobj_resume(dev);
	303
6ee73861 BS	304	NV_INFO(dev, "Reinitialising engines...\n");
	305	engine->instmem.resume(dev);
	306	engine->mc.init(dev);
	307	engine->timer.init(dev);
	308	engine->fb.init(dev);
6dfdd7a6 BS	309	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
	310	if (dev_priv->eng[i])
	311	dev_priv->eng[i]->init(dev, i);
	312	}
6ee73861	313
6ee73861 BS	314	nouveau_irq_postinstall(dev);
	315
	316	/* Re-write SKIPS, they'll have been lost over the suspend */
	317	if (nouveau_vram_pushbuf) {
	318	struct nouveau_channel *chan;
	319	int j;
	320
c420b2dc	321	for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
cff5c133	322	chan = dev_priv->channels.ptr[i];
3c8868d3	323	if (!chan \|\| !chan->pushbuf_bo)
6ee73861 BS	324	continue;
	325
	326	for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
	327	nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
	328	}
	329	}
	330
71d91f65 ML	331	nouveau_pm_resume(dev);
71d91f65 ML	332
6ee73861 BS	333	NV_INFO(dev, "Restoring mode...\n");
	334	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	335	struct nouveau_framebuffer *nouveau_fb;
	336
	337	nouveau_fb = nouveau_framebuffer(crtc->fb);
	338	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	339	continue;
	340
	341	nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	342	}
	343
b334f2b3 MM	344	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
b334f2b3 MM	345	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
b334f2b3 MM	346
	347	ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
	348	if (!ret)
	349	ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
	350	if (ret)
	351	NV_ERROR(dev, "Could not pin/map cursor.\n");
	352	}
	353
cf41d53b BS	354	nouveau_fbcon_set_suspend(dev, 0);
	355	nouveau_fbcon_zfill_all(dev);
	356
f62b27db	357	nouveau_display_init(dev);
6ee73861 BS	358
	359	/* Force CLUT to get re-loaded during modeset */
	360	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	361	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	362
	363	nv_crtc->lut.depth = 0;
	364	}
	365
6ee73861	366	drm_helper_resume_force_mode(dev);
38651674	367
a4eaa0a0 ML	368	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	369	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	370	u32 offset = nv_crtc->cursor.nvbo->bo.offset;
	371
	372	nv_crtc->cursor.set_offset(nv_crtc, offset);
	373	nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
	374	nv_crtc->cursor_saved_y);
	375	}
	376
6ee73861 BS	377	return 0;
	378	}
	379
2a259a3d BS	380	static struct drm_ioctl_desc nouveau_ioctls[] = {
	381	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED\|DRM_AUTH),
	382	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED\|DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	383	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED\|DRM_AUTH),
	384	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED\|DRM_AUTH),
	385	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED\|DRM_AUTH),
	386	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED\|DRM_AUTH),
	387	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED\|DRM_AUTH),
	388	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED\|DRM_AUTH),
	389	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED\|DRM_AUTH),
	390	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED\|DRM_AUTH),
	391	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED\|DRM_AUTH),
	392	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED\|DRM_AUTH),
	393	};
	394
e08e96de AV	395	static const struct file_operations nouveau_driver_fops = {
	396	.owner = THIS_MODULE,
	397	.open = drm_open,
	398	.release = drm_release,
	399	.unlocked_ioctl = drm_ioctl,
	400	.mmap = nouveau_ttm_mmap,
	401	.poll = drm_poll,
	402	.fasync = drm_fasync,
	403	.read = drm_read,
	404	#if defined(CONFIG_COMPAT)
	405	.compat_ioctl = nouveau_compat_ioctl,
	406	#endif
	407	.llseek = noop_llseek,
	408	};
	409
6ee73861 BS	410	static struct drm_driver driver = {
	411	.driver_features =
	412	DRIVER_USE_AGP \| DRIVER_PCI_DMA \| DRIVER_SG \|
cd0b072f	413	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_GEM \|
22b33e8e	414	DRIVER_MODESET \| DRIVER_PRIME,
6ee73861 BS	415	.load = nouveau_load,
	416	.firstopen = nouveau_firstopen,
	417	.lastclose = nouveau_lastclose,
	418	.unload = nouveau_unload,
3f0a68d8	419	.open = nouveau_open,
6ee73861	420	.preclose = nouveau_preclose,
3f0a68d8	421	.postclose = nouveau_postclose,
6ee73861 BS	422	#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	423	.debugfs_init = nouveau_debugfs_init,
	424	.debugfs_cleanup = nouveau_debugfs_takedown,
	425	#endif
	426	.irq_preinstall = nouveau_irq_preinstall,
	427	.irq_postinstall = nouveau_irq_postinstall,
	428	.irq_uninstall = nouveau_irq_uninstall,
	429	.irq_handler = nouveau_irq_handler,
042206c0 FJ	430	.get_vblank_counter = drm_vblank_count,
	431	.enable_vblank = nouveau_vblank_enable,
	432	.disable_vblank = nouveau_vblank_disable,
6ee73861	433	.ioctls = nouveau_ioctls,
e08e96de	434	.fops = &nouveau_driver_fops,
22b33e8e DA	435
	436	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	437	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	438	.gem_prime_export = nouveau_gem_prime_export,
	439	.gem_prime_import = nouveau_gem_prime_import,
	440
6ee73861 BS	441	.gem_init_object = nouveau_gem_object_new,
6ee73861 BS	442	.gem_free_object = nouveau_gem_object_del,
639212d0 BS	443	.gem_open_object = nouveau_gem_object_open,
639212d0 BS	444	.gem_close_object = nouveau_gem_object_close,
6ee73861	445
33dbc27f BS	446	.dumb_create = nouveau_display_dumb_create,
	447	.dumb_map_offset = nouveau_display_dumb_map_offset,
	448	.dumb_destroy = nouveau_display_dumb_destroy,
	449
6ee73861 BS	450	.name = DRIVER_NAME,
	451	.desc = DRIVER_DESC,
	452	#ifdef GIT_REVISION
	453	.date = GIT_REVISION,
	454	#else
	455	.date = DRIVER_DATE,
	456	#endif
	457	.major = DRIVER_MAJOR,
	458	.minor = DRIVER_MINOR,
	459	.patchlevel = DRIVER_PATCHLEVEL,
	460	};
	461
8410ea3b DA	462	static struct pci_driver nouveau_pci_driver = {
	463	.name = DRIVER_NAME,
	464	.id_table = pciidlist,
	465	.probe = nouveau_pci_probe,
	466	.remove = nouveau_pci_remove,
	467	.suspend = nouveau_pci_suspend,
	468	.resume = nouveau_pci_resume
	469	};
	470
6ee73861 BS	471	static int __init nouveau_init(void)
6ee73861 BS	472	{
2a259a3d	473	driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
6ee73861 BS	474
	475	if (nouveau_modeset == -1) {
	476	#ifdef CONFIG_VGA_CONSOLE
	477	if (vgacon_text_force())
	478	nouveau_modeset = 0;
	479	else
	480	#endif
	481	nouveau_modeset = 1;
	482	}
	483
cd0b072f BS	484	if (!nouveau_modeset)
cd0b072f BS	485	return 0;
6ee73861	486
cd0b072f	487	nouveau_register_dsm_handler();
8410ea3b	488	return drm_pci_init(&driver, &nouveau_pci_driver);
6ee73861 BS	489	}
	490
	491	static void __exit nouveau_exit(void)
	492	{
cd0b072f BS	493	if (!nouveau_modeset)
	494	return;
	495
8410ea3b	496	drm_pci_exit(&driver, &nouveau_pci_driver);
6a9ee8af	497	nouveau_unregister_dsm_handler();
6ee73861 BS	498	}
	499
	500	module_init(nouveau_init);
	501	module_exit(nouveau_exit);
	502
	503	MODULE_AUTHOR(DRIVER_AUTHOR);
	504	MODULE_DESCRIPTION(DRIVER_DESC);
	505	MODULE_LICENSE("GPL and additional rights");