[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_drv.c

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/console.h>
#include <linux/module.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nouveau_fb.h"
#include "nouveau_fbcon.h"
#include "nouveau_pm.h"
#include "nv50_display.h"

#include "drm_pciids.h"

MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
int nouveau_agpmode = -1;
module_param_named(agpmode, nouveau_agpmode, int, 0400);

MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
int nouveau_modeset = -1;
module_param_named(modeset, nouveau_modeset, int, 0400);

MODULE_PARM_DESC(vbios, "Override default VBIOS location");
char *nouveau_vbios;
module_param_named(vbios, nouveau_vbios, charp, 0400);

MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
int nouveau_vram_notify = 0;
module_param_named(vram_notify, nouveau_vram_notify, int, 0400);

MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
char *nouveau_vram_type;
module_param_named(vram_type, nouveau_vram_type, charp, 0400);

MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
int nouveau_duallink = 1;
module_param_named(duallink, nouveau_duallink, int, 0400);

MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
int nouveau_uscript_lvds = -1;
module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);

MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
int nouveau_uscript_tmds = -1;
module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);

MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
int nouveau_ignorelid = 0;
module_param_named(ignorelid, nouveau_ignorelid, int, 0400);

MODULE_PARM_DESC(noaccel, "Disable all acceleration");
int nouveau_noaccel = -1;
module_param_named(noaccel, nouveau_noaccel, int, 0400);

MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
int nouveau_nofbaccel = 0;
module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);

MODULE_PARM_DESC(force_post, "Force POST");
int nouveau_force_post = 0;
module_param_named(force_post, nouveau_force_post, int, 0400);

MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
int nouveau_override_conntype = 0;
module_param_named(override_conntype, nouveau_override_conntype, int, 0400);

MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
int nouveau_tv_disable = 0;
module_param_named(tv_disable, nouveau_tv_disable, int, 0400);

MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
		 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
		 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
		 "\t\tDefault: PAL\n"
		 "\t\t*NOTE* Ignored for cards with external TV encoders.");
char *nouveau_tv_norm;
module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);

MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
		"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
		"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
		"\t\t0x100 vgaattr, 0x200 EVO (G80+)");
int nouveau_reg_debug;
module_param_named(reg_debug, nouveau_reg_debug, int, 0600);

MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
char *nouveau_perflvl;
module_param_named(perflvl, nouveau_perflvl, charp, 0400);

MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
int nouveau_perflvl_wr;
module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);

MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
int nouveau_msi;
module_param_named(msi, nouveau_msi, int, 0400);

MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
int nouveau_ctxfw;
module_param_named(ctxfw, nouveau_ctxfw, int, 0400);

MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
int nouveau_mxmdcb = 1;
module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);

int nouveau_fbpercrtc;
#if 0
module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
#endif

static struct pci_device_id pciidlist[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{}
};

MODULE_DEVICE_TABLE(pci, pciidlist);

static struct drm_driver driver;

static int __devinit
nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	return drm_get_pci_dev(pdev, ent, &driver);
}

static void
nouveau_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

int
nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_channel *chan;
	struct drm_crtc *crtc;
	int ret, i, e;

	if (pm_state.event == PM_EVENT_PRETHAW)
		return 0;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	NV_INFO(dev, "Disabling display...\n");
	nouveau_display_fini(dev);

	NV_INFO(dev, "Disabling fbcon...\n");
	nouveau_fbcon_set_suspend(dev, 1);

	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_unpin(nouveau_fb->nvbo);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nouveau_bo_unmap(nv_crtc->cursor.nvbo);
		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	}

	NV_INFO(dev, "Evicting buffers...\n");
	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);

	NV_INFO(dev, "Idling channels...\n");
	for (i = 0; i < pfifo->channels; i++) {
		chan = dev_priv->channels.ptr[i];

		if (chan && chan->pushbuf_bo)
			nouveau_channel_idle(chan);
	}

	pfifo->reassign(dev, false);
	pfifo->disable(dev);
	pfifo->unload_context(dev);

	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
		if (!dev_priv->eng[e])
			continue;

		ret = dev_priv->eng[e]->fini(dev, e, true);
		if (ret) {
			NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
			goto out_abort;
		}
	}

	ret = pinstmem->suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		goto out_abort;
	}

	NV_INFO(dev, "Suspending GPU objects...\n");
	ret = nouveau_gpuobj_suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		pinstmem->resume(dev);
		goto out_abort;
	}

	NV_INFO(dev, "And we're gone!\n");
	pci_save_state(pdev);
	if (pm_state.event == PM_EVENT_SUSPEND) {
		pci_disable_device(pdev);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	return 0;

out_abort:
	NV_INFO(dev, "Re-enabling acceleration..\n");
	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
		if (dev_priv->eng[e])
			dev_priv->eng[e]->init(dev, e);
	}
	pfifo->enable(dev);
	pfifo->reassign(dev, true);
	return ret;
}

int
nouveau_pci_resume(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	struct drm_crtc *crtc;
	int ret, i;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	NV_INFO(dev, "We're back, enabling device...\n");
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	if (pci_enable_device(pdev))
		return -1;
	pci_set_master(dev->pdev);

	/* Make sure the AGP controller is in a consistent state */
	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
		nouveau_mem_reset_agp(dev);

	/* Make the CRTCs accessible */
	engine->display.early_init(dev);

	NV_INFO(dev, "POSTing device...\n");
	ret = nouveau_run_vbios_init(dev);
	if (ret)
		return ret;

	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
		ret = nouveau_mem_init_agp(dev);
		if (ret) {
			NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "Restoring GPU objects...\n");
	nouveau_gpuobj_resume(dev);

	NV_INFO(dev, "Reinitialising engines...\n");
	engine->instmem.resume(dev);
	engine->mc.init(dev);
	engine->timer.init(dev);
	engine->fb.init(dev);
	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
		if (dev_priv->eng[i])
			dev_priv->eng[i]->init(dev, i);
	}
	engine->fifo.init(dev);

	nouveau_irq_postinstall(dev);

	/* Re-write SKIPS, they'll have been lost over the suspend */
	if (nouveau_vram_pushbuf) {
		struct nouveau_channel *chan;
		int j;

		for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
			chan = dev_priv->channels.ptr[i];
			if (!chan || !chan->pushbuf_bo)
				continue;

			for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
				nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
		}
	}

	nouveau_pm_resume(dev);

	NV_INFO(dev, "Restoring mode...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
		if (!ret)
			ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
		if (ret)
			NV_ERROR(dev, "Could not pin/map cursor.\n");
	}

	nouveau_fbcon_set_suspend(dev, 0);
	nouveau_fbcon_zfill_all(dev);

	nouveau_display_init(dev);

	/* Force CLUT to get re-loaded during modeset */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nv_crtc->lut.depth = 0;
	}

	drm_helper_resume_force_mode(dev);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
		u32 offset = nv_crtc->cursor.nvbo->bo.offset;

		nv_crtc->cursor.set_offset(nv_crtc, offset);
		nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
						 nv_crtc->cursor_saved_y);
	}

	return 0;
}

static const struct file_operations nouveau_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = nouveau_ttm_mmap,
	.poll = drm_poll,
	.fasync = drm_fasync,
	.read = drm_read,
#if defined(CONFIG_COMPAT)
	.compat_ioctl = nouveau_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

static struct drm_driver driver = {
	.driver_features =
		DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
		DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
		DRIVER_MODESET,
	.load = nouveau_load,
	.firstopen = nouveau_firstopen,
	.lastclose = nouveau_lastclose,
	.unload = nouveau_unload,
	.open = nouveau_open,
	.preclose = nouveau_preclose,
	.postclose = nouveau_postclose,
#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	.debugfs_init = nouveau_debugfs_init,
	.debugfs_cleanup = nouveau_debugfs_takedown,
#endif
	.irq_preinstall = nouveau_irq_preinstall,
	.irq_postinstall = nouveau_irq_postinstall,
	.irq_uninstall = nouveau_irq_uninstall,
	.irq_handler = nouveau_irq_handler,
	.get_vblank_counter = drm_vblank_count,
	.enable_vblank = nouveau_vblank_enable,
	.disable_vblank = nouveau_vblank_disable,
	.reclaim_buffers = drm_core_reclaim_buffers,
	.ioctls = nouveau_ioctls,
	.fops = &nouveau_driver_fops,
	.gem_init_object = nouveau_gem_object_new,
	.gem_free_object = nouveau_gem_object_del,
	.gem_open_object = nouveau_gem_object_open,
	.gem_close_object = nouveau_gem_object_close,

	.dumb_create = nouveau_display_dumb_create,
	.dumb_map_offset = nouveau_display_dumb_map_offset,
	.dumb_destroy = nouveau_display_dumb_destroy,

	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
#ifdef GIT_REVISION
	.date = GIT_REVISION,
#else
	.date = DRIVER_DATE,
#endif
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
};

static struct pci_driver nouveau_pci_driver = {
		.name = DRIVER_NAME,
		.id_table = pciidlist,
		.probe = nouveau_pci_probe,
		.remove = nouveau_pci_remove,
		.suspend = nouveau_pci_suspend,
		.resume = nouveau_pci_resume
};

static int __init nouveau_init(void)
{
	driver.num_ioctls = nouveau_max_ioctl;

	if (nouveau_modeset == -1) {
#ifdef CONFIG_VGA_CONSOLE
		if (vgacon_text_force())
			nouveau_modeset = 0;
		else
#endif
			nouveau_modeset = 1;
	}

	if (!nouveau_modeset)
		return 0;

	nouveau_register_dsm_handler();
	return drm_pci_init(&driver, &nouveau_pci_driver);
}

static void __exit nouveau_exit(void)
{
	if (!nouveau_modeset)
		return;

	drm_pci_exit(&driver, &nouveau_pci_driver);
	nouveau_unregister_dsm_handler();
}

module_init(nouveau_init);
module_exit(nouveau_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include <linux/console.h>
e0cd3608	26	#include <linux/module.h>
6ee73861 BS	27
	28	#include "drmP.h"
	29	#include "drm.h"
	30	#include "drm_crtc_helper.h"
	31	#include "nouveau_drv.h"
	32	#include "nouveau_hw.h"
	33	#include "nouveau_fb.h"
	34	#include "nouveau_fbcon.h"
64f1c11a	35	#include "nouveau_pm.h"
6ee73861 BS	36	#include "nv50_display.h"
	37
	38	#include "drm_pciids.h"
	39
de5899bd FJ	40	MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
	41	int nouveau_agpmode = -1;
	42	module_param_named(agpmode, nouveau_agpmode, int, 0400);
6ee73861 BS	43
6ee73861 BS	44	MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
03bc9675	45	int nouveau_modeset = -1;
6ee73861 BS	46	module_param_named(modeset, nouveau_modeset, int, 0400);
	47
	48	MODULE_PARM_DESC(vbios, "Override default VBIOS location");
	49	char *nouveau_vbios;
	50	module_param_named(vbios, nouveau_vbios, charp, 0400);
	51
	52	MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
	53	int nouveau_vram_pushbuf;
	54	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	55
	56	MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
2dfe36b1	57	int nouveau_vram_notify = 0;
6ee73861 BS	58	module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
6ee73861 BS	59
7ad2d31c BS	60	MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
	61	char *nouveau_vram_type;
	62	module_param_named(vram_type, nouveau_vram_type, charp, 0400);
	63
6ee73861 BS	64	MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
	65	int nouveau_duallink = 1;
	66	module_param_named(duallink, nouveau_duallink, int, 0400);
	67
	68	MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
	69	int nouveau_uscript_lvds = -1;
	70	module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
	71
	72	MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
	73	int nouveau_uscript_tmds = -1;
	74	module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
	75
a1470890 BS	76	MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
	77	int nouveau_ignorelid = 0;
	78	module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
	79
81e2d422	80	MODULE_PARM_DESC(noaccel, "Disable all acceleration");
aba99a84	81	int nouveau_noaccel = -1;
a32ed69d MK	82	module_param_named(noaccel, nouveau_noaccel, int, 0400);
a32ed69d MK	83
81e2d422	84	MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
a32ed69d MK	85	int nouveau_nofbaccel = 0;
	86	module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
	87
0cba1b76 MK	88	MODULE_PARM_DESC(force_post, "Force POST");
	89	int nouveau_force_post = 0;
	90	module_param_named(force_post, nouveau_force_post, int, 0400);
	91
da647d5b BS	92	MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
	93	int nouveau_override_conntype = 0;
	94	module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
	95
1a5f985c	96	MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
f4053509 BS	97	int nouveau_tv_disable = 0;
	98	module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
	99
6ee73861 BS	100	MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
	101	"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
	102	"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
	103	"\t\tDefault: PAL\n"
	104	"\t\tNOTE Ignored for cards with external TV encoders.");
	105	char *nouveau_tv_norm;
	106	module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
	107
	108	MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
	109	"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
	110	"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
1a5f985c	111	"\t\t0x100 vgaattr, 0x200 EVO (G80+)");
6ee73861 BS	112	int nouveau_reg_debug;
	113	module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
	114
1a5f985c	115	MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
6f876986 BS	116	char *nouveau_perflvl;
	117	module_param_named(perflvl, nouveau_perflvl, charp, 0400);
	118
1a5f985c	119	MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
6f876986 BS	120	int nouveau_perflvl_wr;
	121	module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
	122
1a5f985c	123	MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
35fa2f2a BS	124	int nouveau_msi;
	125	module_param_named(msi, nouveau_msi, int, 0400);
	126
1a5f985c	127	MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
0411de85 BS	128	int nouveau_ctxfw;
	129	module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
	130
1a5f985c	131	MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
b4c26818 BS	132	int nouveau_mxmdcb = 1;
	133	module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
	134
6ee73861 BS	135	int nouveau_fbpercrtc;
	136	#if 0
	137	module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
	138	#endif
	139
	140	static struct pci_device_id pciidlist[] = {
	141	{
	142	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	143	.class = PCI_BASE_CLASS_DISPLAY << 16,
	144	.class_mask = 0xff << 16,
	145	},
	146	{
	147	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
	148	.class = PCI_BASE_CLASS_DISPLAY << 16,
	149	.class_mask = 0xff << 16,
	150	},
	151	{}
	152	};
	153
	154	MODULE_DEVICE_TABLE(pci, pciidlist);
	155
	156	static struct drm_driver driver;
	157
	158	static int __devinit
	159	nouveau_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	160	{
dcdb1674	161	return drm_get_pci_dev(pdev, ent, &driver);
6ee73861 BS	162	}
	163
	164	static void
	165	nouveau_pci_remove(struct pci_dev *pdev)
	166	{
	167	struct drm_device *dev = pci_get_drvdata(pdev);
	168
	169	drm_put_dev(dev);
	170	}
	171
6a9ee8af	172	int
6ee73861 BS	173	nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
	174	{
	175	struct drm_device *dev = pci_get_drvdata(pdev);
	176	struct drm_nouveau_private *dev_priv = dev->dev_private;
	177	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
6ee73861 BS	178	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	179	struct nouveau_channel *chan;
	180	struct drm_crtc *crtc;
92abe749	181	int ret, i, e;
6ee73861	182
6ee73861 BS	183	if (pm_state.event == PM_EVENT_PRETHAW)
	184	return 0;
	185
5bcf719b DA	186	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	187	return 0;
	188
f62b27db BS	189	NV_INFO(dev, "Disabling display...\n");
f62b27db BS	190	nouveau_display_fini(dev);
4bfb94a1	191
cf41d53b BS	192	NV_INFO(dev, "Disabling fbcon...\n");
cf41d53b BS	193	nouveau_fbcon_set_suspend(dev, 1);
6ee73861	194
81441570	195	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
6ee73861 BS	196	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	197	struct nouveau_framebuffer *nouveau_fb;
	198
	199	nouveau_fb = nouveau_framebuffer(crtc->fb);
	200	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	201	continue;
	202
	203	nouveau_bo_unpin(nouveau_fb->nvbo);
	204	}
	205
b334f2b3 MM	206	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	207	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	208
	209	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
	210	nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	211	}
	212
6ee73861 BS	213	NV_INFO(dev, "Evicting buffers...\n");
	214	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
	215
	216	NV_INFO(dev, "Idling channels...\n");
	217	for (i = 0; i < pfifo->channels; i++) {
cff5c133	218	chan = dev_priv->channels.ptr[i];
6ee73861	219
6dccd311 FJ	220	if (chan && chan->pushbuf_bo)
6dccd311 FJ	221	nouveau_channel_idle(chan);
6ee73861 BS	222	}
6ee73861 BS	223
6ee73861 BS	224	pfifo->reassign(dev, false);
	225	pfifo->disable(dev);
	226	pfifo->unload_context(dev);
92abe749 BS	227
92abe749 BS	228	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
6c320fef BS	229	if (!dev_priv->eng[e])
	230	continue;
	231
	232	ret = dev_priv->eng[e]->fini(dev, e, true);
	233	if (ret) {
13f90122	234	NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
6c320fef	235	goto out_abort;
92abe749 BS	236	}
92abe749 BS	237	}
6ee73861	238
dc1e5c0d	239	ret = pinstmem->suspend(dev);
6ee73861 BS	240	if (ret) {
	241	NV_ERROR(dev, "... failed: %d\n", ret);
	242	goto out_abort;
	243	}
	244
dc1e5c0d BS	245	NV_INFO(dev, "Suspending GPU objects...\n");
dc1e5c0d BS	246	ret = nouveau_gpuobj_suspend(dev);
6ee73861 BS	247	if (ret) {
6ee73861 BS	248	NV_ERROR(dev, "... failed: %d\n", ret);
dc1e5c0d	249	pinstmem->resume(dev);
6ee73861 BS	250	goto out_abort;
	251	}
	252
	253	NV_INFO(dev, "And we're gone!\n");
	254	pci_save_state(pdev);
	255	if (pm_state.event == PM_EVENT_SUSPEND) {
	256	pci_disable_device(pdev);
	257	pci_set_power_state(pdev, PCI_D3hot);
	258	}
	259
6ee73861 BS	260	return 0;
	261
	262	out_abort:
	263	NV_INFO(dev, "Re-enabling acceleration..\n");
92abe749 BS	264	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
	265	if (dev_priv->eng[e])
	266	dev_priv->eng[e]->init(dev, e);
	267	}
6ee73861 BS	268	pfifo->enable(dev);
6ee73861 BS	269	pfifo->reassign(dev, true);
6ee73861 BS	270	return ret;
	271	}
	272
6a9ee8af	273	int
6ee73861 BS	274	nouveau_pci_resume(struct pci_dev *pdev)
	275	{
	276	struct drm_device *dev = pci_get_drvdata(pdev);
	277	struct drm_nouveau_private *dev_priv = dev->dev_private;
	278	struct nouveau_engine *engine = &dev_priv->engine;
	279	struct drm_crtc *crtc;
6ee73861 BS	280	int ret, i;
6ee73861 BS	281
5bcf719b DA	282	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	283	return 0;
	284
6ee73861 BS	285	NV_INFO(dev, "We're back, enabling device...\n");
	286	pci_set_power_state(pdev, PCI_D0);
	287	pci_restore_state(pdev);
	288	if (pci_enable_device(pdev))
	289	return -1;
	290	pci_set_master(dev->pdev);
	291
e04d8e82 FJ	292	/* Make sure the AGP controller is in a consistent state */
	293	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
	294	nouveau_mem_reset_agp(dev);
	295
c88c2e06 FJ	296	/* Make the CRTCs accessible */
	297	engine->display.early_init(dev);
	298
6ee73861 BS	299	NV_INFO(dev, "POSTing device...\n");
	300	ret = nouveau_run_vbios_init(dev);
	301	if (ret)
	302	return ret;
	303
	304	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
	305	ret = nouveau_mem_init_agp(dev);
	306	if (ret) {
	307	NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
	308	return ret;
	309	}
	310	}
	311
dc1e5c0d BS	312	NV_INFO(dev, "Restoring GPU objects...\n");
	313	nouveau_gpuobj_resume(dev);
	314
6ee73861 BS	315	NV_INFO(dev, "Reinitialising engines...\n");
	316	engine->instmem.resume(dev);
	317	engine->mc.init(dev);
	318	engine->timer.init(dev);
	319	engine->fb.init(dev);
6dfdd7a6 BS	320	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
	321	if (dev_priv->eng[i])
	322	dev_priv->eng[i]->init(dev, i);
	323	}
6ee73861 BS	324	engine->fifo.init(dev);
6ee73861 BS	325
6ee73861 BS	326	nouveau_irq_postinstall(dev);
	327
	328	/* Re-write SKIPS, they'll have been lost over the suspend */
	329	if (nouveau_vram_pushbuf) {
	330	struct nouveau_channel *chan;
	331	int j;
	332
	333	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
cff5c133	334	chan = dev_priv->channels.ptr[i];
3c8868d3	335	if (!chan \|\| !chan->pushbuf_bo)
6ee73861 BS	336	continue;
	337
	338	for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
	339	nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
	340	}
	341	}
	342
71d91f65 ML	343	nouveau_pm_resume(dev);
71d91f65 ML	344
6ee73861 BS	345	NV_INFO(dev, "Restoring mode...\n");
	346	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	347	struct nouveau_framebuffer *nouveau_fb;
	348
	349	nouveau_fb = nouveau_framebuffer(crtc->fb);
	350	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	351	continue;
	352
	353	nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	354	}
	355
b334f2b3 MM	356	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
b334f2b3 MM	357	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
b334f2b3 MM	358
	359	ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
	360	if (!ret)
	361	ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
	362	if (ret)
	363	NV_ERROR(dev, "Could not pin/map cursor.\n");
	364	}
	365
cf41d53b BS	366	nouveau_fbcon_set_suspend(dev, 0);
	367	nouveau_fbcon_zfill_all(dev);
	368
f62b27db	369	nouveau_display_init(dev);
6ee73861 BS	370
	371	/* Force CLUT to get re-loaded during modeset */
	372	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	373	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	374
	375	nv_crtc->lut.depth = 0;
	376	}
	377
6ee73861	378	drm_helper_resume_force_mode(dev);
38651674	379
a4eaa0a0 ML	380	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	381	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	382	u32 offset = nv_crtc->cursor.nvbo->bo.offset;
	383
	384	nv_crtc->cursor.set_offset(nv_crtc, offset);
	385	nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
	386	nv_crtc->cursor_saved_y);
	387	}
	388
6ee73861 BS	389	return 0;
	390	}
	391
e08e96de AV	392	static const struct file_operations nouveau_driver_fops = {
	393	.owner = THIS_MODULE,
	394	.open = drm_open,
	395	.release = drm_release,
	396	.unlocked_ioctl = drm_ioctl,
	397	.mmap = nouveau_ttm_mmap,
	398	.poll = drm_poll,
	399	.fasync = drm_fasync,
	400	.read = drm_read,
	401	#if defined(CONFIG_COMPAT)
	402	.compat_ioctl = nouveau_compat_ioctl,
	403	#endif
	404	.llseek = noop_llseek,
	405	};
	406
6ee73861 BS	407	static struct drm_driver driver = {
	408	.driver_features =
	409	DRIVER_USE_AGP \| DRIVER_PCI_DMA \| DRIVER_SG \|
cd0b072f BS	410	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_GEM \|
cd0b072f BS	411	DRIVER_MODESET,
6ee73861 BS	412	.load = nouveau_load,
	413	.firstopen = nouveau_firstopen,
	414	.lastclose = nouveau_lastclose,
	415	.unload = nouveau_unload,
3f0a68d8	416	.open = nouveau_open,
6ee73861	417	.preclose = nouveau_preclose,
3f0a68d8	418	.postclose = nouveau_postclose,
6ee73861 BS	419	#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	420	.debugfs_init = nouveau_debugfs_init,
	421	.debugfs_cleanup = nouveau_debugfs_takedown,
	422	#endif
	423	.irq_preinstall = nouveau_irq_preinstall,
	424	.irq_postinstall = nouveau_irq_postinstall,
	425	.irq_uninstall = nouveau_irq_uninstall,
	426	.irq_handler = nouveau_irq_handler,
042206c0 FJ	427	.get_vblank_counter = drm_vblank_count,
	428	.enable_vblank = nouveau_vblank_enable,
	429	.disable_vblank = nouveau_vblank_disable,
6ee73861	430	.reclaim_buffers = drm_core_reclaim_buffers,
6ee73861	431	.ioctls = nouveau_ioctls,
e08e96de	432	.fops = &nouveau_driver_fops,
6ee73861 BS	433	.gem_init_object = nouveau_gem_object_new,
6ee73861 BS	434	.gem_free_object = nouveau_gem_object_del,
639212d0 BS	435	.gem_open_object = nouveau_gem_object_open,
639212d0 BS	436	.gem_close_object = nouveau_gem_object_close,
6ee73861	437
33dbc27f BS	438	.dumb_create = nouveau_display_dumb_create,
	439	.dumb_map_offset = nouveau_display_dumb_map_offset,
	440	.dumb_destroy = nouveau_display_dumb_destroy,
	441
6ee73861 BS	442	.name = DRIVER_NAME,
	443	.desc = DRIVER_DESC,
	444	#ifdef GIT_REVISION
	445	.date = GIT_REVISION,
	446	#else
	447	.date = DRIVER_DATE,
	448	#endif
	449	.major = DRIVER_MAJOR,
	450	.minor = DRIVER_MINOR,
	451	.patchlevel = DRIVER_PATCHLEVEL,
	452	};
	453
8410ea3b DA	454	static struct pci_driver nouveau_pci_driver = {
	455	.name = DRIVER_NAME,
	456	.id_table = pciidlist,
	457	.probe = nouveau_pci_probe,
	458	.remove = nouveau_pci_remove,
	459	.suspend = nouveau_pci_suspend,
	460	.resume = nouveau_pci_resume
	461	};
	462
6ee73861 BS	463	static int __init nouveau_init(void)
	464	{
	465	driver.num_ioctls = nouveau_max_ioctl;
	466
	467	if (nouveau_modeset == -1) {
	468	#ifdef CONFIG_VGA_CONSOLE
	469	if (vgacon_text_force())
	470	nouveau_modeset = 0;
	471	else
	472	#endif
	473	nouveau_modeset = 1;
	474	}
	475
cd0b072f BS	476	if (!nouveau_modeset)
cd0b072f BS	477	return 0;
6ee73861	478
cd0b072f	479	nouveau_register_dsm_handler();
8410ea3b	480	return drm_pci_init(&driver, &nouveau_pci_driver);
6ee73861 BS	481	}
	482
	483	static void __exit nouveau_exit(void)
	484	{
cd0b072f BS	485	if (!nouveau_modeset)
	486	return;
	487
8410ea3b	488	drm_pci_exit(&driver, &nouveau_pci_driver);
6a9ee8af	489	nouveau_unregister_dsm_handler();
6ee73861 BS	490	}
	491
	492	module_init(nouveau_init);
	493	module_exit(nouveau_exit);
	494
	495	MODULE_AUTHOR(DRIVER_AUTHOR);
	496	MODULE_DESCRIPTION(DRIVER_DESC);
	497	MODULE_LICENSE("GPL and additional rights");