[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_drv.c

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/console.h>
#include <linux/module.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
#include "nouveau_abi16.h"
#include "nouveau_hw.h"
#include "nouveau_fb.h"
#include "nouveau_fbcon.h"
#include "nouveau_pm.h"
#include <engine/fifo.h>
#include "nv50_display.h"

#include "drm_pciids.h"

MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
int nouveau_agpmode = -1;
module_param_named(agpmode, nouveau_agpmode, int, 0400);

MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
int nouveau_modeset = -1;
module_param_named(modeset, nouveau_modeset, int, 0400);

MODULE_PARM_DESC(vbios, "Override default VBIOS location");
char *nouveau_vbios;
module_param_named(vbios, nouveau_vbios, charp, 0400);

MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
int nouveau_vram_notify = 0;
module_param_named(vram_notify, nouveau_vram_notify, int, 0400);

MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
char *nouveau_vram_type;
module_param_named(vram_type, nouveau_vram_type, charp, 0400);

MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
int nouveau_duallink = 1;
module_param_named(duallink, nouveau_duallink, int, 0400);

MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
int nouveau_uscript_lvds = -1;
module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);

MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
int nouveau_uscript_tmds = -1;
module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);

MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
int nouveau_ignorelid = 0;
module_param_named(ignorelid, nouveau_ignorelid, int, 0400);

MODULE_PARM_DESC(noaccel, "Disable all acceleration");
int nouveau_noaccel = -1;
module_param_named(noaccel, nouveau_noaccel, int, 0400);

MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
int nouveau_nofbaccel = 0;
module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);

MODULE_PARM_DESC(force_post, "Force POST");
int nouveau_force_post = 0;
module_param_named(force_post, nouveau_force_post, int, 0400);

MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
int nouveau_override_conntype = 0;
module_param_named(override_conntype, nouveau_override_conntype, int, 0400);

MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
int nouveau_tv_disable = 0;
module_param_named(tv_disable, nouveau_tv_disable, int, 0400);

MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
		 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
		 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
		 "\t\tDefault: PAL\n"
		 "\t\t*NOTE* Ignored for cards with external TV encoders.");
char *nouveau_tv_norm;
module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);

MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
		"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
		"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
		"\t\t0x100 vgaattr, 0x200 EVO (G80+)");
int nouveau_reg_debug;
module_param_named(reg_debug, nouveau_reg_debug, int, 0600);

MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
char *nouveau_perflvl;
module_param_named(perflvl, nouveau_perflvl, charp, 0400);

MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
int nouveau_perflvl_wr;
module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);

MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
int nouveau_msi;
module_param_named(msi, nouveau_msi, int, 0400);

MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
int nouveau_ctxfw;
module_param_named(ctxfw, nouveau_ctxfw, int, 0400);

MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
int nouveau_mxmdcb = 1;
module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);

int nouveau_fbpercrtc;
#if 0
module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
#endif

static struct pci_device_id pciidlist[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{}
};

MODULE_DEVICE_TABLE(pci, pciidlist);

static struct drm_driver driver;

static int __devinit
nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	return drm_get_pci_dev(pdev, ent, &driver);
}

static void
nouveau_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

int
nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct nouveau_channel *chan;
	struct drm_crtc *crtc;
	int ret, i, e;

	if (pm_state.event == PM_EVENT_PRETHAW)
		return 0;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	NV_INFO(dev, "Disabling display...\n");
	nouveau_display_fini(dev);

	NV_INFO(dev, "Disabling fbcon...\n");
	nouveau_fbcon_set_suspend(dev, 1);

	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_unpin(nouveau_fb->nvbo);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nouveau_bo_unmap(nv_crtc->cursor.nvbo);
		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	}

	NV_INFO(dev, "Evicting buffers...\n");
	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);

	NV_INFO(dev, "Idling channels...\n");
	for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
		chan = dev_priv->channels.ptr[i];

		if (chan && chan->pushbuf_bo)
			nouveau_channel_idle(chan);
	}

	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
		if (!dev_priv->eng[e])
			continue;

		ret = dev_priv->eng[e]->fini(dev, e, true);
		if (ret) {
			NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
			goto out_abort;
		}
	}

	ret = pinstmem->suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		goto out_abort;
	}

	NV_INFO(dev, "Suspending GPU objects...\n");
	ret = nouveau_gpuobj_suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		pinstmem->resume(dev);
		goto out_abort;
	}

	NV_INFO(dev, "And we're gone!\n");
	pci_save_state(pdev);
	if (pm_state.event == PM_EVENT_SUSPEND) {
		pci_disable_device(pdev);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	return 0;

out_abort:
	NV_INFO(dev, "Re-enabling acceleration..\n");
	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
		if (dev_priv->eng[e])
			dev_priv->eng[e]->init(dev, e);
	}
	return ret;
}

int
nouveau_pci_resume(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	struct drm_crtc *crtc;
	int ret, i;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	NV_INFO(dev, "We're back, enabling device...\n");
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	if (pci_enable_device(pdev))
		return -1;
	pci_set_master(dev->pdev);

	/* Make sure the AGP controller is in a consistent state */
	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
		nouveau_mem_reset_agp(dev);

	/* Make the CRTCs accessible */
	engine->display.early_init(dev);

	NV_INFO(dev, "POSTing device...\n");
	ret = nouveau_run_vbios_init(dev);
	if (ret)
		return ret;

	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
		ret = nouveau_mem_init_agp(dev);
		if (ret) {
			NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "Restoring GPU objects...\n");
	nouveau_gpuobj_resume(dev);

	NV_INFO(dev, "Reinitialising engines...\n");
	engine->instmem.resume(dev);
	engine->mc.init(dev);
	engine->timer.init(dev);
	engine->fb.init(dev);
	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
		if (dev_priv->eng[i])
			dev_priv->eng[i]->init(dev, i);
	}

	nouveau_irq_postinstall(dev);

	/* Re-write SKIPS, they'll have been lost over the suspend */
	if (nouveau_vram_pushbuf) {
		struct nouveau_channel *chan;
		int j;

		for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
			chan = dev_priv->channels.ptr[i];
			if (!chan || !chan->pushbuf_bo)
				continue;

			for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
				nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
		}
	}

	nouveau_pm_resume(dev);

	NV_INFO(dev, "Restoring mode...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
		if (!ret)
			ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
		if (ret)
			NV_ERROR(dev, "Could not pin/map cursor.\n");
	}

	nouveau_fbcon_set_suspend(dev, 0);
	nouveau_fbcon_zfill_all(dev);

	nouveau_display_init(dev);

	/* Force CLUT to get re-loaded during modeset */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nv_crtc->lut.depth = 0;
	}

	drm_helper_resume_force_mode(dev);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
		u32 offset = nv_crtc->cursor.nvbo->bo.offset;

		nv_crtc->cursor.set_offset(nv_crtc, offset);
		nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
						 nv_crtc->cursor_saved_y);
	}

	return 0;
}

static struct drm_ioctl_desc nouveau_ioctls[] = {
	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
};

static const struct file_operations nouveau_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = nouveau_ttm_mmap,
	.poll = drm_poll,
	.fasync = drm_fasync,
	.read = drm_read,
#if defined(CONFIG_COMPAT)
	.compat_ioctl = nouveau_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

static struct drm_driver driver = {
	.driver_features =
		DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
		DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
		DRIVER_MODESET | DRIVER_PRIME,
	.load = nouveau_load,
	.firstopen = nouveau_firstopen,
	.lastclose = nouveau_lastclose,
	.unload = nouveau_unload,
	.open = nouveau_open,
	.preclose = nouveau_preclose,
	.postclose = nouveau_postclose,
#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	.debugfs_init = nouveau_debugfs_init,
	.debugfs_cleanup = nouveau_debugfs_takedown,
#endif
	.irq_preinstall = nouveau_irq_preinstall,
	.irq_postinstall = nouveau_irq_postinstall,
	.irq_uninstall = nouveau_irq_uninstall,
	.irq_handler = nouveau_irq_handler,
	.get_vblank_counter = drm_vblank_count,
	.enable_vblank = nouveau_vblank_enable,
	.disable_vblank = nouveau_vblank_disable,
	.ioctls = nouveau_ioctls,
	.fops = &nouveau_driver_fops,

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = nouveau_gem_prime_export,
	.gem_prime_import = nouveau_gem_prime_import,

	.gem_init_object = nouveau_gem_object_new,
	.gem_free_object = nouveau_gem_object_del,
	.gem_open_object = nouveau_gem_object_open,
	.gem_close_object = nouveau_gem_object_close,

	.dumb_create = nouveau_display_dumb_create,
	.dumb_map_offset = nouveau_display_dumb_map_offset,
	.dumb_destroy = nouveau_display_dumb_destroy,

	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
#ifdef GIT_REVISION
	.date = GIT_REVISION,
#else
	.date = DRIVER_DATE,
#endif
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
};

static struct pci_driver nouveau_pci_driver = {
		.name = DRIVER_NAME,
		.id_table = pciidlist,
		.probe = nouveau_pci_probe,
		.remove = nouveau_pci_remove,
		.suspend = nouveau_pci_suspend,
		.resume = nouveau_pci_resume
};

static int __init nouveau_init(void)
{
	driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);

	if (nouveau_modeset == -1) {
#ifdef CONFIG_VGA_CONSOLE
		if (vgacon_text_force())
			nouveau_modeset = 0;
		else
#endif
			nouveau_modeset = 1;
	}

	if (!nouveau_modeset)
		return 0;

	nouveau_register_dsm_handler();
	return drm_pci_init(&driver, &nouveau_pci_driver);
}

static void __exit nouveau_exit(void)
{
	if (!nouveau_modeset)
		return;

	drm_pci_exit(&driver, &nouveau_pci_driver);
	nouveau_unregister_dsm_handler();
}

module_init(nouveau_init);
module_exit(nouveau_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include <linux/console.h>
e0cd3608	26	#include <linux/module.h>
6ee73861 BS	27
	28	#include "drmP.h"
	29	#include "drm.h"
	30	#include "drm_crtc_helper.h"
	31	#include "nouveau_drv.h"
2a259a3d	32	#include "nouveau_abi16.h"
6ee73861 BS	33	#include "nouveau_hw.h"
	34	#include "nouveau_fb.h"
	35	#include "nouveau_fbcon.h"
64f1c11a	36	#include "nouveau_pm.h"
02a841d4	37	#include <engine/fifo.h>
6ee73861 BS	38	#include "nv50_display.h"
	39
	40	#include "drm_pciids.h"
	41
de5899bd FJ	42	MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
	43	int nouveau_agpmode = -1;
	44	module_param_named(agpmode, nouveau_agpmode, int, 0400);
6ee73861 BS	45
6ee73861 BS	46	MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
03bc9675	47	int nouveau_modeset = -1;
6ee73861 BS	48	module_param_named(modeset, nouveau_modeset, int, 0400);
	49
	50	MODULE_PARM_DESC(vbios, "Override default VBIOS location");
	51	char *nouveau_vbios;
	52	module_param_named(vbios, nouveau_vbios, charp, 0400);
	53
	54	MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
	55	int nouveau_vram_pushbuf;
	56	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	57
	58	MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
2dfe36b1	59	int nouveau_vram_notify = 0;
6ee73861 BS	60	module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
6ee73861 BS	61
7ad2d31c BS	62	MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
	63	char *nouveau_vram_type;
	64	module_param_named(vram_type, nouveau_vram_type, charp, 0400);
	65
6ee73861 BS	66	MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
	67	int nouveau_duallink = 1;
	68	module_param_named(duallink, nouveau_duallink, int, 0400);
	69
	70	MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
	71	int nouveau_uscript_lvds = -1;
	72	module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
	73
	74	MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
	75	int nouveau_uscript_tmds = -1;
	76	module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
	77
a1470890 BS	78	MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
	79	int nouveau_ignorelid = 0;
	80	module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
	81
81e2d422	82	MODULE_PARM_DESC(noaccel, "Disable all acceleration");
aba99a84	83	int nouveau_noaccel = -1;
a32ed69d MK	84	module_param_named(noaccel, nouveau_noaccel, int, 0400);
a32ed69d MK	85
81e2d422	86	MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
a32ed69d MK	87	int nouveau_nofbaccel = 0;
	88	module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
	89
0cba1b76 MK	90	MODULE_PARM_DESC(force_post, "Force POST");
	91	int nouveau_force_post = 0;
	92	module_param_named(force_post, nouveau_force_post, int, 0400);
	93
da647d5b BS	94	MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
	95	int nouveau_override_conntype = 0;
	96	module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
	97
1a5f985c	98	MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
f4053509 BS	99	int nouveau_tv_disable = 0;
	100	module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
	101
6ee73861 BS	102	MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
	103	"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
	104	"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
	105	"\t\tDefault: PAL\n"
	106	"\t\tNOTE Ignored for cards with external TV encoders.");
	107	char *nouveau_tv_norm;
	108	module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
	109
	110	MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
	111	"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
	112	"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
1a5f985c	113	"\t\t0x100 vgaattr, 0x200 EVO (G80+)");
6ee73861 BS	114	int nouveau_reg_debug;
	115	module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
	116
1a5f985c	117	MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
6f876986 BS	118	char *nouveau_perflvl;
	119	module_param_named(perflvl, nouveau_perflvl, charp, 0400);
	120
1a5f985c	121	MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
6f876986 BS	122	int nouveau_perflvl_wr;
	123	module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
	124
1a5f985c	125	MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
35fa2f2a BS	126	int nouveau_msi;
	127	module_param_named(msi, nouveau_msi, int, 0400);
	128
1a5f985c	129	MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
0411de85 BS	130	int nouveau_ctxfw;
	131	module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
	132
1a5f985c	133	MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
b4c26818 BS	134	int nouveau_mxmdcb = 1;
	135	module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
	136
6ee73861 BS	137	int nouveau_fbpercrtc;
	138	#if 0
	139	module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
	140	#endif
	141
	142	static struct pci_device_id pciidlist[] = {
	143	{
	144	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	145	.class = PCI_BASE_CLASS_DISPLAY << 16,
	146	.class_mask = 0xff << 16,
	147	},
	148	{
	149	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
	150	.class = PCI_BASE_CLASS_DISPLAY << 16,
	151	.class_mask = 0xff << 16,
	152	},
	153	{}
	154	};
	155
	156	MODULE_DEVICE_TABLE(pci, pciidlist);
	157
	158	static struct drm_driver driver;
	159
	160	static int __devinit
	161	nouveau_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	162	{
dcdb1674	163	return drm_get_pci_dev(pdev, ent, &driver);
6ee73861 BS	164	}
	165
	166	static void
	167	nouveau_pci_remove(struct pci_dev *pdev)
	168	{
	169	struct drm_device *dev = pci_get_drvdata(pdev);
	170
	171	drm_put_dev(dev);
	172	}
	173
6a9ee8af	174	int
6ee73861 BS	175	nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
	176	{
	177	struct drm_device *dev = pci_get_drvdata(pdev);
	178	struct drm_nouveau_private *dev_priv = dev->dev_private;
	179	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
c420b2dc	180	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
6ee73861 BS	181	struct nouveau_channel *chan;
6ee73861 BS	182	struct drm_crtc *crtc;
92abe749	183	int ret, i, e;
6ee73861	184
6ee73861 BS	185	if (pm_state.event == PM_EVENT_PRETHAW)
	186	return 0;
	187
5bcf719b DA	188	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	189	return 0;
	190
f62b27db BS	191	NV_INFO(dev, "Disabling display...\n");
f62b27db BS	192	nouveau_display_fini(dev);
4bfb94a1	193
cf41d53b BS	194	NV_INFO(dev, "Disabling fbcon...\n");
cf41d53b BS	195	nouveau_fbcon_set_suspend(dev, 1);
6ee73861	196
81441570	197	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
6ee73861 BS	198	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	199	struct nouveau_framebuffer *nouveau_fb;
	200
	201	nouveau_fb = nouveau_framebuffer(crtc->fb);
	202	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	203	continue;
	204
	205	nouveau_bo_unpin(nouveau_fb->nvbo);
	206	}
	207
b334f2b3 MM	208	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	209	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	210
	211	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
	212	nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	213	}
	214
6ee73861 BS	215	NV_INFO(dev, "Evicting buffers...\n");
	216	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
	217
	218	NV_INFO(dev, "Idling channels...\n");
c420b2dc	219	for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
cff5c133	220	chan = dev_priv->channels.ptr[i];
6ee73861	221
6dccd311 FJ	222	if (chan && chan->pushbuf_bo)
6dccd311 FJ	223	nouveau_channel_idle(chan);
6ee73861 BS	224	}
6ee73861 BS	225
92abe749	226	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
6c320fef BS	227	if (!dev_priv->eng[e])
	228	continue;
	229
	230	ret = dev_priv->eng[e]->fini(dev, e, true);
	231	if (ret) {
13f90122	232	NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
6c320fef	233	goto out_abort;
92abe749 BS	234	}
92abe749 BS	235	}
6ee73861	236
dc1e5c0d	237	ret = pinstmem->suspend(dev);
6ee73861 BS	238	if (ret) {
	239	NV_ERROR(dev, "... failed: %d\n", ret);
	240	goto out_abort;
	241	}
	242
dc1e5c0d BS	243	NV_INFO(dev, "Suspending GPU objects...\n");
dc1e5c0d BS	244	ret = nouveau_gpuobj_suspend(dev);
6ee73861 BS	245	if (ret) {
6ee73861 BS	246	NV_ERROR(dev, "... failed: %d\n", ret);
dc1e5c0d	247	pinstmem->resume(dev);
6ee73861 BS	248	goto out_abort;
	249	}
	250
	251	NV_INFO(dev, "And we're gone!\n");
	252	pci_save_state(pdev);
	253	if (pm_state.event == PM_EVENT_SUSPEND) {
	254	pci_disable_device(pdev);
	255	pci_set_power_state(pdev, PCI_D3hot);
	256	}
	257
6ee73861 BS	258	return 0;
	259
	260	out_abort:
	261	NV_INFO(dev, "Re-enabling acceleration..\n");
92abe749 BS	262	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
	263	if (dev_priv->eng[e])
	264	dev_priv->eng[e]->init(dev, e);
	265	}
6ee73861 BS	266	return ret;
	267	}
	268
6a9ee8af	269	int
6ee73861 BS	270	nouveau_pci_resume(struct pci_dev *pdev)
	271	{
	272	struct drm_device *dev = pci_get_drvdata(pdev);
c420b2dc	273	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
6ee73861 BS	274	struct drm_nouveau_private *dev_priv = dev->dev_private;
	275	struct nouveau_engine *engine = &dev_priv->engine;
	276	struct drm_crtc *crtc;
6ee73861 BS	277	int ret, i;
6ee73861 BS	278
5bcf719b DA	279	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	280	return 0;
	281
6ee73861 BS	282	NV_INFO(dev, "We're back, enabling device...\n");
	283	pci_set_power_state(pdev, PCI_D0);
	284	pci_restore_state(pdev);
	285	if (pci_enable_device(pdev))
	286	return -1;
	287	pci_set_master(dev->pdev);
	288
e04d8e82 FJ	289	/* Make sure the AGP controller is in a consistent state */
	290	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
	291	nouveau_mem_reset_agp(dev);
	292
c88c2e06 FJ	293	/* Make the CRTCs accessible */
	294	engine->display.early_init(dev);
	295
6ee73861 BS	296	NV_INFO(dev, "POSTing device...\n");
	297	ret = nouveau_run_vbios_init(dev);
	298	if (ret)
	299	return ret;
	300
	301	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
	302	ret = nouveau_mem_init_agp(dev);
	303	if (ret) {
	304	NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
	305	return ret;
	306	}
	307	}
	308
dc1e5c0d BS	309	NV_INFO(dev, "Restoring GPU objects...\n");
	310	nouveau_gpuobj_resume(dev);
	311
6ee73861 BS	312	NV_INFO(dev, "Reinitialising engines...\n");
	313	engine->instmem.resume(dev);
	314	engine->mc.init(dev);
	315	engine->timer.init(dev);
	316	engine->fb.init(dev);
6dfdd7a6 BS	317	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
	318	if (dev_priv->eng[i])
	319	dev_priv->eng[i]->init(dev, i);
	320	}
6ee73861	321
6ee73861 BS	322	nouveau_irq_postinstall(dev);
	323
	324	/* Re-write SKIPS, they'll have been lost over the suspend */
	325	if (nouveau_vram_pushbuf) {
	326	struct nouveau_channel *chan;
	327	int j;
	328
c420b2dc	329	for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
cff5c133	330	chan = dev_priv->channels.ptr[i];
3c8868d3	331	if (!chan \|\| !chan->pushbuf_bo)
6ee73861 BS	332	continue;
	333
	334	for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
	335	nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
	336	}
	337	}
	338
71d91f65 ML	339	nouveau_pm_resume(dev);
71d91f65 ML	340
6ee73861 BS	341	NV_INFO(dev, "Restoring mode...\n");
	342	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	343	struct nouveau_framebuffer *nouveau_fb;
	344
	345	nouveau_fb = nouveau_framebuffer(crtc->fb);
	346	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	347	continue;
	348
	349	nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	350	}
	351
b334f2b3 MM	352	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
b334f2b3 MM	353	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
b334f2b3 MM	354
	355	ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
	356	if (!ret)
	357	ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
	358	if (ret)
	359	NV_ERROR(dev, "Could not pin/map cursor.\n");
	360	}
	361
cf41d53b BS	362	nouveau_fbcon_set_suspend(dev, 0);
	363	nouveau_fbcon_zfill_all(dev);
	364
f62b27db	365	nouveau_display_init(dev);
6ee73861 BS	366
	367	/* Force CLUT to get re-loaded during modeset */
	368	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	369	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	370
	371	nv_crtc->lut.depth = 0;
	372	}
	373
6ee73861	374	drm_helper_resume_force_mode(dev);
38651674	375
a4eaa0a0 ML	376	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	377	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	378	u32 offset = nv_crtc->cursor.nvbo->bo.offset;
	379
	380	nv_crtc->cursor.set_offset(nv_crtc, offset);
	381	nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
	382	nv_crtc->cursor_saved_y);
	383	}
	384
6ee73861 BS	385	return 0;
	386	}
	387
2a259a3d BS	388	static struct drm_ioctl_desc nouveau_ioctls[] = {
	389	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED\|DRM_AUTH),
	390	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED\|DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	391	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED\|DRM_AUTH),
	392	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED\|DRM_AUTH),
	393	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED\|DRM_AUTH),
	394	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED\|DRM_AUTH),
	395	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED\|DRM_AUTH),
	396	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED\|DRM_AUTH),
	397	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED\|DRM_AUTH),
	398	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED\|DRM_AUTH),
	399	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED\|DRM_AUTH),
	400	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED\|DRM_AUTH),
	401	};
	402
e08e96de AV	403	static const struct file_operations nouveau_driver_fops = {
	404	.owner = THIS_MODULE,
	405	.open = drm_open,
	406	.release = drm_release,
	407	.unlocked_ioctl = drm_ioctl,
	408	.mmap = nouveau_ttm_mmap,
	409	.poll = drm_poll,
	410	.fasync = drm_fasync,
	411	.read = drm_read,
	412	#if defined(CONFIG_COMPAT)
	413	.compat_ioctl = nouveau_compat_ioctl,
	414	#endif
	415	.llseek = noop_llseek,
	416	};
	417
6ee73861 BS	418	static struct drm_driver driver = {
	419	.driver_features =
	420	DRIVER_USE_AGP \| DRIVER_PCI_DMA \| DRIVER_SG \|
cd0b072f	421	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_GEM \|
22b33e8e	422	DRIVER_MODESET \| DRIVER_PRIME,
6ee73861 BS	423	.load = nouveau_load,
	424	.firstopen = nouveau_firstopen,
	425	.lastclose = nouveau_lastclose,
	426	.unload = nouveau_unload,
3f0a68d8	427	.open = nouveau_open,
6ee73861	428	.preclose = nouveau_preclose,
3f0a68d8	429	.postclose = nouveau_postclose,
6ee73861 BS	430	#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	431	.debugfs_init = nouveau_debugfs_init,
	432	.debugfs_cleanup = nouveau_debugfs_takedown,
	433	#endif
	434	.irq_preinstall = nouveau_irq_preinstall,
	435	.irq_postinstall = nouveau_irq_postinstall,
	436	.irq_uninstall = nouveau_irq_uninstall,
	437	.irq_handler = nouveau_irq_handler,
042206c0 FJ	438	.get_vblank_counter = drm_vblank_count,
	439	.enable_vblank = nouveau_vblank_enable,
	440	.disable_vblank = nouveau_vblank_disable,
6ee73861	441	.ioctls = nouveau_ioctls,
e08e96de	442	.fops = &nouveau_driver_fops,
22b33e8e DA	443
	444	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	445	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	446	.gem_prime_export = nouveau_gem_prime_export,
	447	.gem_prime_import = nouveau_gem_prime_import,
	448
6ee73861 BS	449	.gem_init_object = nouveau_gem_object_new,
6ee73861 BS	450	.gem_free_object = nouveau_gem_object_del,
639212d0 BS	451	.gem_open_object = nouveau_gem_object_open,
639212d0 BS	452	.gem_close_object = nouveau_gem_object_close,
6ee73861	453
33dbc27f BS	454	.dumb_create = nouveau_display_dumb_create,
	455	.dumb_map_offset = nouveau_display_dumb_map_offset,
	456	.dumb_destroy = nouveau_display_dumb_destroy,
	457
6ee73861 BS	458	.name = DRIVER_NAME,
	459	.desc = DRIVER_DESC,
	460	#ifdef GIT_REVISION
	461	.date = GIT_REVISION,
	462	#else
	463	.date = DRIVER_DATE,
	464	#endif
	465	.major = DRIVER_MAJOR,
	466	.minor = DRIVER_MINOR,
	467	.patchlevel = DRIVER_PATCHLEVEL,
	468	};
	469
8410ea3b DA	470	static struct pci_driver nouveau_pci_driver = {
	471	.name = DRIVER_NAME,
	472	.id_table = pciidlist,
	473	.probe = nouveau_pci_probe,
	474	.remove = nouveau_pci_remove,
	475	.suspend = nouveau_pci_suspend,
	476	.resume = nouveau_pci_resume
	477	};
	478
6ee73861 BS	479	static int __init nouveau_init(void)
6ee73861 BS	480	{
2a259a3d	481	driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
6ee73861 BS	482
	483	if (nouveau_modeset == -1) {
	484	#ifdef CONFIG_VGA_CONSOLE
	485	if (vgacon_text_force())
	486	nouveau_modeset = 0;
	487	else
	488	#endif
	489	nouveau_modeset = 1;
	490	}
	491
cd0b072f BS	492	if (!nouveau_modeset)
cd0b072f BS	493	return 0;
6ee73861	494
cd0b072f	495	nouveau_register_dsm_handler();
8410ea3b	496	return drm_pci_init(&driver, &nouveau_pci_driver);
6ee73861 BS	497	}
	498
	499	static void __exit nouveau_exit(void)
	500	{
cd0b072f BS	501	if (!nouveau_modeset)
	502	return;
	503
8410ea3b	504	drm_pci_exit(&driver, &nouveau_pci_driver);
6a9ee8af	505	nouveau_unregister_dsm_handler();
6ee73861 BS	506	}
	507
	508	module_init(nouveau_init);
	509	module_exit(nouveau_exit);
	510
	511	MODULE_AUTHOR(DRIVER_AUTHOR);
	512	MODULE_DESCRIPTION(DRIVER_DESC);
	513	MODULE_LICENSE("GPL and additional rights");