Commit | Line | Data |
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94580299 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
77145f1c | 25 | #include <linux/console.h> |
c5fd936e | 26 | #include <linux/delay.h> |
94580299 BS |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> | |
5addcf0a DA |
29 | #include <linux/pm_runtime.h> |
30 | #include <linux/vga_switcheroo.h> | |
fdb751ef | 31 | |
ae95621b MY |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
fdb751ef | 34 | |
ebb945a9 | 35 | #include <core/gpuobj.h> |
c33e05a1 | 36 | #include <core/option.h> |
7974dd1b BS |
37 | #include <core/pci.h> |
38 | #include <core/tegra.h> | |
94580299 | 39 | |
04b88677 | 40 | #include <nvif/driver.h> |
a7cf0180 | 41 | #include <nvif/fifo.h> |
37e1c45a | 42 | #include <nvif/user.h> |
04b88677 | 43 | |
923bc416 | 44 | #include <nvif/class.h> |
845f2725 | 45 | #include <nvif/cl0002.h> |
8ed1730c | 46 | #include <nvif/cla06f.h> |
538b269b | 47 | |
4dc28134 | 48 | #include "nouveau_drv.h" |
ebb945a9 | 49 | #include "nouveau_dma.h" |
77145f1c BS |
50 | #include "nouveau_ttm.h" |
51 | #include "nouveau_gem.h" | |
77145f1c | 52 | #include "nouveau_vga.h" |
8d021d71 | 53 | #include "nouveau_led.h" |
b9ed919f | 54 | #include "nouveau_hwmon.h" |
77145f1c BS |
55 | #include "nouveau_acpi.h" |
56 | #include "nouveau_bios.h" | |
57 | #include "nouveau_ioctl.h" | |
ebb945a9 BS |
58 | #include "nouveau_abi16.h" |
59 | #include "nouveau_fbcon.h" | |
60 | #include "nouveau_fence.h" | |
33b903e8 | 61 | #include "nouveau_debugfs.h" |
27111a23 | 62 | #include "nouveau_usif.h" |
703fa264 | 63 | #include "nouveau_connector.h" |
055a65d5 | 64 | #include "nouveau_platform.h" |
eeaf06ac | 65 | #include "nouveau_svm.h" |
ebb945a9 | 66 | |
94580299 BS |
67 | MODULE_PARM_DESC(config, "option string to pass to driver core"); |
68 | static char *nouveau_config; | |
69 | module_param_named(config, nouveau_config, charp, 0400); | |
70 | ||
71 | MODULE_PARM_DESC(debug, "debug string to pass to driver core"); | |
72 | static char *nouveau_debug; | |
73 | module_param_named(debug, nouveau_debug, charp, 0400); | |
74 | ||
ebb945a9 BS |
75 | MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); |
76 | static int nouveau_noaccel = 0; | |
77 | module_param_named(noaccel, nouveau_noaccel, int, 0400); | |
78 | ||
9430738d BS |
79 | MODULE_PARM_DESC(modeset, "enable driver (default: auto, " |
80 | "0 = disabled, 1 = enabled, 2 = headless)"); | |
81 | int nouveau_modeset = -1; | |
77145f1c BS |
82 | module_param_named(modeset, nouveau_modeset, int, 0400); |
83 | ||
eb493fbc LP |
84 | MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); |
85 | static int nouveau_atomic = 0; | |
86 | module_param_named(atomic, nouveau_atomic, int, 0400); | |
87 | ||
5addcf0a | 88 | MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); |
321f5c5f | 89 | static int nouveau_runtime_pm = -1; |
5addcf0a DA |
90 | module_param_named(runpm, nouveau_runtime_pm, int, 0400); |
91 | ||
915b4d11 DH |
92 | static struct drm_driver driver_stub; |
93 | static struct drm_driver driver_pci; | |
94 | static struct drm_driver driver_platform; | |
77145f1c | 95 | |
94580299 | 96 | static u64 |
420b9469 | 97 | nouveau_pci_name(struct pci_dev *pdev) |
94580299 BS |
98 | { |
99 | u64 name = (u64)pci_domain_nr(pdev->bus) << 32; | |
100 | name |= pdev->bus->number << 16; | |
101 | name |= PCI_SLOT(pdev->devfn) << 8; | |
102 | return name | PCI_FUNC(pdev->devfn); | |
103 | } | |
104 | ||
420b9469 AC |
105 | static u64 |
106 | nouveau_platform_name(struct platform_device *platformdev) | |
107 | { | |
108 | return platformdev->id; | |
109 | } | |
110 | ||
111 | static u64 | |
112 | nouveau_name(struct drm_device *dev) | |
113 | { | |
114 | if (dev->pdev) | |
115 | return nouveau_pci_name(dev->pdev); | |
116 | else | |
76adb460 | 117 | return nouveau_platform_name(to_platform_device(dev->dev)); |
420b9469 AC |
118 | } |
119 | ||
814a2324 | 120 | static inline bool |
11e451e7 | 121 | nouveau_cli_work_ready(struct dma_fence *fence) |
814a2324 | 122 | { |
11e451e7 BS |
123 | if (!dma_fence_is_signaled(fence)) |
124 | return false; | |
814a2324 BS |
125 | dma_fence_put(fence); |
126 | return true; | |
127 | } | |
128 | ||
129 | static void | |
11e451e7 | 130 | nouveau_cli_work(struct work_struct *w) |
814a2324 | 131 | { |
11e451e7 | 132 | struct nouveau_cli *cli = container_of(w, typeof(*cli), work); |
814a2324 BS |
133 | struct nouveau_cli_work *work, *wtmp; |
134 | mutex_lock(&cli->lock); | |
135 | list_for_each_entry_safe(work, wtmp, &cli->worker, head) { | |
11e451e7 | 136 | if (!work->fence || nouveau_cli_work_ready(work->fence)) { |
814a2324 BS |
137 | list_del(&work->head); |
138 | work->func(work); | |
139 | } | |
140 | } | |
141 | mutex_unlock(&cli->lock); | |
142 | } | |
143 | ||
144 | static void | |
145 | nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb) | |
146 | { | |
147 | struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb); | |
148 | schedule_work(&work->cli->work); | |
149 | } | |
150 | ||
151 | void | |
152 | nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence, | |
153 | struct nouveau_cli_work *work) | |
154 | { | |
155 | work->fence = dma_fence_get(fence); | |
156 | work->cli = cli; | |
157 | mutex_lock(&cli->lock); | |
158 | list_add_tail(&work->head, &cli->worker); | |
814a2324 BS |
159 | if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence)) |
160 | nouveau_cli_work_fence(fence, &work->cb); | |
b26a2319 | 161 | mutex_unlock(&cli->lock); |
814a2324 BS |
162 | } |
163 | ||
20d8a88e BS |
164 | static void |
165 | nouveau_cli_fini(struct nouveau_cli *cli) | |
166 | { | |
11e451e7 BS |
167 | /* All our channels are dead now, which means all the fences they |
168 | * own are signalled, and all callback functions have been called. | |
169 | * | |
170 | * So, after flushing the workqueue, there should be nothing left. | |
171 | */ | |
172 | flush_work(&cli->work); | |
173 | WARN_ON(!list_empty(&cli->worker)); | |
174 | ||
20d8a88e | 175 | usif_client_fini(cli); |
bfe91afa | 176 | nouveau_vmm_fini(&cli->svm); |
24e8375b | 177 | nouveau_vmm_fini(&cli->vmm); |
01670a79 | 178 | nvif_mmu_fini(&cli->mmu); |
1167c6bc | 179 | nvif_device_fini(&cli->device); |
cb7e88e7 | 180 | mutex_lock(&cli->drm->master.lock); |
20d8a88e | 181 | nvif_client_fini(&cli->base); |
cb7e88e7 | 182 | mutex_unlock(&cli->drm->master.lock); |
20d8a88e BS |
183 | } |
184 | ||
94580299 | 185 | static int |
20d8a88e BS |
186 | nouveau_cli_init(struct nouveau_drm *drm, const char *sname, |
187 | struct nouveau_cli *cli) | |
94580299 | 188 | { |
7f507624 BS |
189 | static const struct nvif_mclass |
190 | mems[] = { | |
191 | { NVIF_CLASS_MEM_GF100, -1 }, | |
192 | { NVIF_CLASS_MEM_NV50 , -1 }, | |
193 | { NVIF_CLASS_MEM_NV04 , -1 }, | |
194 | {} | |
195 | }; | |
01670a79 BS |
196 | static const struct nvif_mclass |
197 | mmus[] = { | |
198 | { NVIF_CLASS_MMU_GF100, -1 }, | |
199 | { NVIF_CLASS_MMU_NV50 , -1 }, | |
200 | { NVIF_CLASS_MMU_NV04 , -1 }, | |
201 | {} | |
202 | }; | |
96da0bcd BS |
203 | static const struct nvif_mclass |
204 | vmms[] = { | |
205 | { NVIF_CLASS_VMM_GP100, -1 }, | |
206 | { NVIF_CLASS_VMM_GM200, -1 }, | |
207 | { NVIF_CLASS_VMM_GF100, -1 }, | |
208 | { NVIF_CLASS_VMM_NV50 , -1 }, | |
209 | { NVIF_CLASS_VMM_NV04 , -1 }, | |
210 | {} | |
211 | }; | |
20d8a88e | 212 | u64 device = nouveau_name(drm->dev); |
9ad97ede | 213 | int ret; |
9ad97ede | 214 | |
20d8a88e | 215 | snprintf(cli->name, sizeof(cli->name), "%s", sname); |
e75c091b | 216 | cli->drm = drm; |
20d8a88e BS |
217 | mutex_init(&cli->mutex); |
218 | usif_client_init(cli); | |
219 | ||
814a2324 BS |
220 | INIT_WORK(&cli->work, nouveau_cli_work); |
221 | INIT_LIST_HEAD(&cli->worker); | |
cb7e88e7 BS |
222 | mutex_init(&cli->lock); |
223 | ||
224 | if (cli == &drm->master) { | |
80e60973 BS |
225 | ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, |
226 | cli->name, device, &cli->base); | |
227 | } else { | |
cb7e88e7 BS |
228 | mutex_lock(&drm->master.lock); |
229 | ret = nvif_client_init(&drm->master.base, cli->name, device, | |
9ad97ede | 230 | &cli->base); |
cb7e88e7 | 231 | mutex_unlock(&drm->master.lock); |
dd5700ea | 232 | } |
20d8a88e | 233 | if (ret) { |
a43b16dd | 234 | NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret); |
20d8a88e | 235 | goto done; |
dd5700ea | 236 | } |
94580299 | 237 | |
1167c6bc BS |
238 | ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE, |
239 | &(struct nv_device_v0) { | |
240 | .device = ~0, | |
241 | }, sizeof(struct nv_device_v0), | |
242 | &cli->device); | |
243 | if (ret) { | |
a43b16dd | 244 | NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret); |
1167c6bc BS |
245 | goto done; |
246 | } | |
247 | ||
01670a79 BS |
248 | ret = nvif_mclass(&cli->device.object, mmus); |
249 | if (ret < 0) { | |
a43b16dd | 250 | NV_PRINTK(err, cli, "No supported MMU class\n"); |
01670a79 BS |
251 | goto done; |
252 | } | |
253 | ||
254 | ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu); | |
255 | if (ret) { | |
a43b16dd | 256 | NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret); |
01670a79 BS |
257 | goto done; |
258 | } | |
259 | ||
96da0bcd BS |
260 | ret = nvif_mclass(&cli->mmu.object, vmms); |
261 | if (ret < 0) { | |
a43b16dd | 262 | NV_PRINTK(err, cli, "No supported VMM class\n"); |
96da0bcd BS |
263 | goto done; |
264 | } | |
265 | ||
266 | ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); | |
267 | if (ret) { | |
a43b16dd | 268 | NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret); |
96da0bcd BS |
269 | goto done; |
270 | } | |
271 | ||
7f507624 BS |
272 | ret = nvif_mclass(&cli->mmu.object, mems); |
273 | if (ret < 0) { | |
a43b16dd | 274 | NV_PRINTK(err, cli, "No supported MEM class\n"); |
7f507624 BS |
275 | goto done; |
276 | } | |
277 | ||
278 | cli->mem = &mems[ret]; | |
7f507624 | 279 | return 0; |
20d8a88e BS |
280 | done: |
281 | if (ret) | |
282 | nouveau_cli_fini(cli); | |
283 | return ret; | |
94580299 BS |
284 | } |
285 | ||
ebb945a9 | 286 | static void |
f0eee9ae BS |
287 | nouveau_accel_ce_fini(struct nouveau_drm *drm) |
288 | { | |
289 | nouveau_channel_idle(drm->cechan); | |
290 | nvif_object_fini(&drm->ttm.copy); | |
291 | nouveau_channel_del(&drm->cechan); | |
292 | } | |
293 | ||
294 | static void | |
295 | nouveau_accel_ce_init(struct nouveau_drm *drm) | |
296 | { | |
297 | struct nvif_device *device = &drm->client.device; | |
298 | int ret = 0; | |
299 | ||
300 | /* Allocate channel that has access to a (preferably async) copy | |
301 | * engine, to use for TTM buffer moves. | |
302 | */ | |
303 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { | |
304 | ret = nouveau_channel_new(drm, device, | |
305 | nvif_fifo_runlist_ce(device), 0, | |
306 | true, &drm->cechan); | |
307 | } else | |
308 | if (device->info.chipset >= 0xa3 && | |
309 | device->info.chipset != 0xaa && | |
310 | device->info.chipset != 0xac) { | |
311 | /* Prior to Kepler, there's only a single runlist, so all | |
312 | * engines can be accessed from any channel. | |
313 | * | |
314 | * We still want to use a separate channel though. | |
315 | */ | |
316 | ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false, | |
317 | &drm->cechan); | |
318 | } | |
319 | ||
320 | if (ret) | |
321 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
322 | } | |
323 | ||
324 | static void | |
325 | nouveau_accel_gr_fini(struct nouveau_drm *drm) | |
ebb945a9 | 326 | { |
fbd58ebd | 327 | nouveau_channel_idle(drm->channel); |
0ad72863 | 328 | nvif_object_fini(&drm->ntfy); |
f027f491 | 329 | nvkm_gpuobj_del(&drm->notify); |
0ad72863 | 330 | nvif_object_fini(&drm->nvsw); |
fbd58ebd | 331 | nouveau_channel_del(&drm->channel); |
f0eee9ae | 332 | } |
fbd58ebd | 333 | |
f0eee9ae BS |
334 | static void |
335 | nouveau_accel_gr_init(struct nouveau_drm *drm) | |
336 | { | |
337 | struct nvif_device *device = &drm->client.device; | |
338 | u32 arg0, arg1; | |
339 | int ret; | |
340 | ||
341 | /* Allocate channel that has access to the graphics engine. */ | |
342 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { | |
343 | arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR); | |
344 | arg1 = 1; | |
345 | } else { | |
346 | arg0 = NvDmaFB; | |
347 | arg1 = NvDmaTT; | |
348 | } | |
349 | ||
350 | ret = nouveau_channel_new(drm, device, arg0, arg1, false, | |
351 | &drm->channel); | |
352 | if (ret) { | |
353 | NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); | |
354 | nouveau_accel_gr_fini(drm); | |
355 | return; | |
356 | } | |
357 | ||
358 | /* A SW class is used on pre-NV50 HW to assist with handling the | |
359 | * synchronisation of page flips, as well as to implement fences | |
360 | * on TNT/TNT2 HW that lacks any kind of support in host. | |
361 | */ | |
362 | if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { | |
363 | ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW, | |
364 | nouveau_abi16_swclass(drm), NULL, 0, | |
365 | &drm->nvsw); | |
366 | if (ret == 0) { | |
367 | ret = RING_SPACE(drm->channel, 2); | |
368 | if (ret == 0) { | |
369 | BEGIN_NV04(drm->channel, NvSubSw, 0, 1); | |
370 | OUT_RING (drm->channel, drm->nvsw.handle); | |
371 | } | |
372 | } | |
373 | ||
374 | if (ret) { | |
375 | NV_ERROR(drm, "failed to allocate sw class, %d\n", ret); | |
376 | nouveau_accel_gr_fini(drm); | |
377 | return; | |
378 | } | |
379 | } | |
380 | ||
381 | /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason, | |
382 | * even if notification is never requested, so, allocate a ctxdma on | |
383 | * any GPU where it's possible we'll end up using M2MF for BO moves. | |
384 | */ | |
385 | if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { | |
386 | ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL, | |
387 | &drm->notify); | |
388 | if (ret) { | |
389 | NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); | |
390 | nouveau_accel_gr_fini(drm); | |
391 | return; | |
392 | } | |
393 | ||
394 | ret = nvif_object_init(&drm->channel->user, NvNotify0, | |
395 | NV_DMA_IN_MEMORY, | |
396 | &(struct nv_dma_v0) { | |
397 | .target = NV_DMA_V0_TARGET_VRAM, | |
398 | .access = NV_DMA_V0_ACCESS_RDWR, | |
399 | .start = drm->notify->addr, | |
400 | .limit = drm->notify->addr + 31 | |
401 | }, sizeof(struct nv_dma_v0), | |
402 | &drm->ntfy); | |
403 | if (ret) { | |
404 | nouveau_accel_gr_fini(drm); | |
405 | return; | |
406 | } | |
407 | } | |
408 | } | |
fbd58ebd | 409 | |
f0eee9ae BS |
410 | static void |
411 | nouveau_accel_fini(struct nouveau_drm *drm) | |
412 | { | |
413 | nouveau_accel_ce_fini(drm); | |
414 | nouveau_accel_gr_fini(drm); | |
ebb945a9 BS |
415 | if (drm->fence) |
416 | nouveau_fence(drm)->dtor(drm); | |
417 | } | |
418 | ||
419 | static void | |
420 | nouveau_accel_init(struct nouveau_drm *drm) | |
421 | { | |
1167c6bc | 422 | struct nvif_device *device = &drm->client.device; |
41a63406 | 423 | struct nvif_sclass *sclass; |
41a63406 | 424 | int ret, i, n; |
ebb945a9 | 425 | |
967e7bde | 426 | if (nouveau_noaccel) |
ebb945a9 BS |
427 | return; |
428 | ||
f0eee9ae | 429 | /* Initialise global support for channels, and synchronisation. */ |
eb47db4f BS |
430 | ret = nouveau_channels_init(drm); |
431 | if (ret) | |
432 | return; | |
433 | ||
967e7bde BS |
434 | /*XXX: this is crap, but the fence/channel stuff is a little |
435 | * backwards in some places. this will be fixed. | |
436 | */ | |
41a63406 | 437 | ret = n = nvif_object_sclass_get(&device->object, &sclass); |
967e7bde BS |
438 | if (ret < 0) |
439 | return; | |
440 | ||
41a63406 BS |
441 | for (ret = -ENOSYS, i = 0; i < n; i++) { |
442 | switch (sclass[i].oclass) { | |
bbf8906b | 443 | case NV03_CHANNEL_DMA: |
967e7bde BS |
444 | ret = nv04_fence_create(drm); |
445 | break; | |
bbf8906b | 446 | case NV10_CHANNEL_DMA: |
967e7bde BS |
447 | ret = nv10_fence_create(drm); |
448 | break; | |
bbf8906b BS |
449 | case NV17_CHANNEL_DMA: |
450 | case NV40_CHANNEL_DMA: | |
967e7bde BS |
451 | ret = nv17_fence_create(drm); |
452 | break; | |
bbf8906b | 453 | case NV50_CHANNEL_GPFIFO: |
967e7bde BS |
454 | ret = nv50_fence_create(drm); |
455 | break; | |
bbf8906b | 456 | case G82_CHANNEL_GPFIFO: |
967e7bde BS |
457 | ret = nv84_fence_create(drm); |
458 | break; | |
bbf8906b BS |
459 | case FERMI_CHANNEL_GPFIFO: |
460 | case KEPLER_CHANNEL_GPFIFO_A: | |
63f8c9b7 | 461 | case KEPLER_CHANNEL_GPFIFO_B: |
a1020afe | 462 | case MAXWELL_CHANNEL_GPFIFO_A: |
e8ff9794 | 463 | case PASCAL_CHANNEL_GPFIFO_A: |
37e1c45a | 464 | case VOLTA_CHANNEL_GPFIFO_A: |
641d0b30 | 465 | case TURING_CHANNEL_GPFIFO_A: |
967e7bde BS |
466 | ret = nvc0_fence_create(drm); |
467 | break; | |
468 | default: | |
469 | break; | |
470 | } | |
471 | } | |
472 | ||
41a63406 | 473 | nvif_object_sclass_put(&sclass); |
ebb945a9 BS |
474 | if (ret) { |
475 | NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); | |
476 | nouveau_accel_fini(drm); | |
477 | return; | |
478 | } | |
479 | ||
f0eee9ae BS |
480 | /* Volta requires access to a doorbell register for kickoff. */ |
481 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { | |
482 | ret = nvif_user_init(device); | |
00fc6f6f | 483 | if (ret) |
ebb945a9 | 484 | return; |
ebb945a9 BS |
485 | } |
486 | ||
f0eee9ae BS |
487 | /* Allocate channels we need to support various functions. */ |
488 | nouveau_accel_gr_init(drm); | |
489 | nouveau_accel_ce_init(drm); | |
ebb945a9 | 490 | |
f0eee9ae | 491 | /* Initialise accelerated TTM buffer moves. */ |
49981046 | 492 | nouveau_bo_move_init(drm); |
ebb945a9 BS |
493 | } |
494 | ||
5b8a43ae | 495 | static int |
cfea88a4 | 496 | nouveau_drm_device_init(struct drm_device *dev) |
94580299 | 497 | { |
94580299 BS |
498 | struct nouveau_drm *drm; |
499 | int ret; | |
500 | ||
20d8a88e BS |
501 | if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) |
502 | return -ENOMEM; | |
503 | dev->dev_private = drm; | |
504 | drm->dev = dev; | |
505 | ||
cb7e88e7 BS |
506 | ret = nouveau_cli_init(drm, "DRM-master", &drm->master); |
507 | if (ret) | |
c4cee69a | 508 | goto fail_alloc; |
cb7e88e7 | 509 | |
20d8a88e | 510 | ret = nouveau_cli_init(drm, "DRM", &drm->client); |
94580299 | 511 | if (ret) |
c4cee69a | 512 | goto fail_master; |
94580299 | 513 | |
1167c6bc BS |
514 | dev->irq_enabled = true; |
515 | ||
989aa5b7 | 516 | nvxx_client(&drm->client.base)->debug = |
be83cd4e | 517 | nvkm_dbgopt(nouveau_debug, "DRM"); |
77145f1c | 518 | |
94580299 | 519 | INIT_LIST_HEAD(&drm->clients); |
ebb945a9 | 520 | spin_lock_init(&drm->tile.lock); |
94580299 | 521 | |
77145f1c BS |
522 | /* workaround an odd issue on nvc1 by disabling the device's |
523 | * nosnoop capability. hopefully won't cause issues until a | |
524 | * better fix is found - assuming there is one... | |
525 | */ | |
1167c6bc BS |
526 | if (drm->client.device.info.chipset == 0xc1) |
527 | nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); | |
ebb945a9 | 528 | |
77145f1c | 529 | nouveau_vga_init(drm); |
cb75d97e | 530 | |
ebb945a9 | 531 | ret = nouveau_ttm_init(drm); |
94580299 | 532 | if (ret) |
77145f1c BS |
533 | goto fail_ttm; |
534 | ||
535 | ret = nouveau_bios_init(dev); | |
536 | if (ret) | |
537 | goto fail_bios; | |
538 | ||
d7f9bb65 BS |
539 | nouveau_accel_init(drm); |
540 | ||
77145f1c | 541 | ret = nouveau_display_create(dev); |
ebb945a9 | 542 | if (ret) |
77145f1c BS |
543 | goto fail_dispctor; |
544 | ||
545 | if (dev->mode_config.num_crtc) { | |
0f9976dd | 546 | ret = nouveau_display_init(dev, false, false); |
77145f1c BS |
547 | if (ret) |
548 | goto fail_dispinit; | |
549 | } | |
550 | ||
b126a200 | 551 | nouveau_debugfs_init(drm); |
b9ed919f | 552 | nouveau_hwmon_init(dev); |
eeaf06ac | 553 | nouveau_svm_init(drm); |
ebb945a9 | 554 | nouveau_fbcon_init(dev); |
8d021d71 | 555 | nouveau_led_init(dev); |
5addcf0a | 556 | |
8fa4338a | 557 | if (nouveau_pmops_runtime()) { |
5addcf0a DA |
558 | pm_runtime_use_autosuspend(dev->dev); |
559 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
560 | pm_runtime_set_active(dev->dev); | |
561 | pm_runtime_allow(dev->dev); | |
562 | pm_runtime_mark_last_busy(dev->dev); | |
563 | pm_runtime_put(dev->dev); | |
564 | } | |
7326ead9 | 565 | |
94580299 BS |
566 | return 0; |
567 | ||
77145f1c BS |
568 | fail_dispinit: |
569 | nouveau_display_destroy(dev); | |
570 | fail_dispctor: | |
d7f9bb65 | 571 | nouveau_accel_fini(drm); |
77145f1c BS |
572 | nouveau_bios_takedown(dev); |
573 | fail_bios: | |
ebb945a9 | 574 | nouveau_ttm_fini(drm); |
77145f1c | 575 | fail_ttm: |
77145f1c | 576 | nouveau_vga_fini(drm); |
20d8a88e | 577 | nouveau_cli_fini(&drm->client); |
c4cee69a | 578 | fail_master: |
cb7e88e7 | 579 | nouveau_cli_fini(&drm->master); |
c4cee69a | 580 | fail_alloc: |
20d8a88e | 581 | kfree(drm); |
94580299 BS |
582 | return ret; |
583 | } | |
584 | ||
11b3c20b | 585 | static void |
cfea88a4 | 586 | nouveau_drm_device_fini(struct drm_device *dev) |
94580299 | 587 | { |
77145f1c | 588 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 | 589 | |
8fa4338a | 590 | if (nouveau_pmops_runtime()) { |
c1b16b45 | 591 | pm_runtime_get_sync(dev->dev); |
55c868a3 | 592 | pm_runtime_forbid(dev->dev); |
c1b16b45 LW |
593 | } |
594 | ||
8d021d71 | 595 | nouveau_led_fini(dev); |
ebb945a9 | 596 | nouveau_fbcon_fini(dev); |
eeaf06ac | 597 | nouveau_svm_fini(drm); |
b9ed919f | 598 | nouveau_hwmon_fini(dev); |
b126a200 | 599 | nouveau_debugfs_fini(drm); |
77145f1c | 600 | |
9430738d | 601 | if (dev->mode_config.num_crtc) |
2f7ca781 | 602 | nouveau_display_fini(dev, false, false); |
77145f1c BS |
603 | nouveau_display_destroy(dev); |
604 | ||
d7f9bb65 | 605 | nouveau_accel_fini(drm); |
77145f1c | 606 | nouveau_bios_takedown(dev); |
94580299 | 607 | |
ebb945a9 | 608 | nouveau_ttm_fini(drm); |
77145f1c | 609 | nouveau_vga_fini(drm); |
cb75d97e | 610 | |
20d8a88e | 611 | nouveau_cli_fini(&drm->client); |
cb7e88e7 | 612 | nouveau_cli_fini(&drm->master); |
20d8a88e | 613 | kfree(drm); |
94580299 BS |
614 | } |
615 | ||
cfea88a4 LP |
616 | static int nouveau_drm_probe(struct pci_dev *pdev, |
617 | const struct pci_device_id *pent) | |
618 | { | |
619 | struct nvkm_device *device; | |
620 | struct drm_device *drm_dev; | |
621 | struct apertures_struct *aper; | |
622 | bool boot = false; | |
623 | int ret; | |
624 | ||
625 | if (vga_switcheroo_client_probe_defer(pdev)) | |
626 | return -EPROBE_DEFER; | |
627 | ||
628 | /* We need to check that the chipset is supported before booting | |
629 | * fbdev off the hardware, as there's no way to put it back. | |
630 | */ | |
631 | ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device); | |
632 | if (ret) | |
633 | return ret; | |
634 | ||
635 | nvkm_device_del(&device); | |
636 | ||
637 | /* Remove conflicting drivers (vesafb, efifb etc). */ | |
638 | aper = alloc_apertures(3); | |
639 | if (!aper) | |
640 | return -ENOMEM; | |
641 | ||
642 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
643 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
644 | aper->count = 1; | |
645 | ||
646 | if (pci_resource_len(pdev, 2)) { | |
647 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
648 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
649 | aper->count++; | |
650 | } | |
651 | ||
652 | if (pci_resource_len(pdev, 3)) { | |
653 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
654 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
655 | aper->count++; | |
656 | } | |
657 | ||
658 | #ifdef CONFIG_X86 | |
659 | boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
660 | #endif | |
661 | if (nouveau_modeset != 2) | |
662 | drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot); | |
663 | kfree(aper); | |
664 | ||
665 | ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, | |
666 | true, true, ~0ULL, &device); | |
667 | if (ret) | |
668 | return ret; | |
669 | ||
670 | pci_set_master(pdev); | |
671 | ||
672 | if (nouveau_atomic) | |
673 | driver_pci.driver_features |= DRIVER_ATOMIC; | |
674 | ||
675 | drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev); | |
676 | if (IS_ERR(drm_dev)) { | |
677 | ret = PTR_ERR(drm_dev); | |
678 | goto fail_nvkm; | |
679 | } | |
680 | ||
681 | ret = pci_enable_device(pdev); | |
682 | if (ret) | |
683 | goto fail_drm; | |
684 | ||
685 | drm_dev->pdev = pdev; | |
686 | pci_set_drvdata(pdev, drm_dev); | |
687 | ||
688 | ret = nouveau_drm_device_init(drm_dev); | |
689 | if (ret) | |
690 | goto fail_pci; | |
691 | ||
692 | ret = drm_dev_register(drm_dev, pent->driver_data); | |
693 | if (ret) | |
694 | goto fail_drm_dev_init; | |
695 | ||
696 | return 0; | |
697 | ||
698 | fail_drm_dev_init: | |
699 | nouveau_drm_device_fini(drm_dev); | |
700 | fail_pci: | |
701 | pci_disable_device(pdev); | |
702 | fail_drm: | |
703 | drm_dev_put(drm_dev); | |
704 | fail_nvkm: | |
705 | nvkm_device_del(&device); | |
706 | return ret; | |
707 | } | |
708 | ||
8ba9ff11 AC |
709 | void |
710 | nouveau_drm_device_remove(struct drm_device *dev) | |
94580299 | 711 | { |
cfea88a4 | 712 | struct pci_dev *pdev = dev->pdev; |
77145f1c | 713 | struct nouveau_drm *drm = nouveau_drm(dev); |
be83cd4e | 714 | struct nvkm_client *client; |
76ecea5b | 715 | struct nvkm_device *device; |
77145f1c | 716 | |
cfea88a4 LP |
717 | drm_dev_unregister(dev); |
718 | ||
7d3428cd | 719 | dev->irq_enabled = false; |
989aa5b7 | 720 | client = nvxx_client(&drm->client.base); |
4e7e62d6 | 721 | device = nvkm_device_find(client->device); |
77145f1c | 722 | |
cfea88a4 LP |
723 | nouveau_drm_device_fini(dev); |
724 | pci_disable_device(pdev); | |
725 | drm_dev_put(dev); | |
e781dc8f | 726 | nvkm_device_del(&device); |
94580299 | 727 | } |
8ba9ff11 AC |
728 | |
729 | static void | |
730 | nouveau_drm_remove(struct pci_dev *pdev) | |
731 | { | |
732 | struct drm_device *dev = pci_get_drvdata(pdev); | |
733 | ||
734 | nouveau_drm_device_remove(dev); | |
735 | } | |
94580299 | 736 | |
cd897837 | 737 | static int |
05c63c2f | 738 | nouveau_do_suspend(struct drm_device *dev, bool runtime) |
94580299 | 739 | { |
77145f1c | 740 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 BS |
741 | int ret; |
742 | ||
eeaf06ac | 743 | nouveau_svm_suspend(drm); |
8d021d71 MP |
744 | nouveau_led_suspend(dev); |
745 | ||
6fbb702e | 746 | if (dev->mode_config.num_crtc) { |
2d38a535 | 747 | NV_DEBUG(drm, "suspending console...\n"); |
6fbb702e | 748 | nouveau_fbcon_set_suspend(dev, 1); |
2d38a535 | 749 | NV_DEBUG(drm, "suspending display...\n"); |
6fbb702e | 750 | ret = nouveau_display_suspend(dev, runtime); |
9430738d BS |
751 | if (ret) |
752 | return ret; | |
753 | } | |
94580299 | 754 | |
2d38a535 | 755 | NV_DEBUG(drm, "evicting buffers...\n"); |
ebb945a9 BS |
756 | ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); |
757 | ||
2d38a535 | 758 | NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); |
81dff21b BS |
759 | if (drm->cechan) { |
760 | ret = nouveau_channel_idle(drm->cechan); | |
761 | if (ret) | |
f3980dc5 | 762 | goto fail_display; |
81dff21b BS |
763 | } |
764 | ||
765 | if (drm->channel) { | |
766 | ret = nouveau_channel_idle(drm->channel); | |
767 | if (ret) | |
f3980dc5 | 768 | goto fail_display; |
81dff21b BS |
769 | } |
770 | ||
2d38a535 | 771 | NV_DEBUG(drm, "suspending fence...\n"); |
ebb945a9 | 772 | if (drm->fence && nouveau_fence(drm)->suspend) { |
f3980dc5 IM |
773 | if (!nouveau_fence(drm)->suspend(drm)) { |
774 | ret = -ENOMEM; | |
775 | goto fail_display; | |
776 | } | |
ebb945a9 BS |
777 | } |
778 | ||
2d38a535 | 779 | NV_DEBUG(drm, "suspending object tree...\n"); |
cb7e88e7 | 780 | ret = nvif_client_suspend(&drm->master.base); |
94580299 BS |
781 | if (ret) |
782 | goto fail_client; | |
783 | ||
94580299 BS |
784 | return 0; |
785 | ||
786 | fail_client: | |
f3980dc5 IM |
787 | if (drm->fence && nouveau_fence(drm)->resume) |
788 | nouveau_fence(drm)->resume(drm); | |
789 | ||
790 | fail_display: | |
9430738d | 791 | if (dev->mode_config.num_crtc) { |
2d38a535 | 792 | NV_DEBUG(drm, "resuming display...\n"); |
6fbb702e | 793 | nouveau_display_resume(dev, runtime); |
9430738d | 794 | } |
94580299 BS |
795 | return ret; |
796 | } | |
797 | ||
cd897837 | 798 | static int |
6fbb702e | 799 | nouveau_do_resume(struct drm_device *dev, bool runtime) |
2d8b9ccb DA |
800 | { |
801 | struct nouveau_drm *drm = nouveau_drm(dev); | |
2d8b9ccb | 802 | |
2d38a535 | 803 | NV_DEBUG(drm, "resuming object tree...\n"); |
cb7e88e7 | 804 | nvif_client_resume(&drm->master.base); |
94580299 | 805 | |
2d38a535 | 806 | NV_DEBUG(drm, "resuming fence...\n"); |
81dff21b BS |
807 | if (drm->fence && nouveau_fence(drm)->resume) |
808 | nouveau_fence(drm)->resume(drm); | |
809 | ||
77145f1c | 810 | nouveau_run_vbios_init(dev); |
77145f1c | 811 | |
9430738d | 812 | if (dev->mode_config.num_crtc) { |
2d38a535 | 813 | NV_DEBUG(drm, "resuming display...\n"); |
6fbb702e | 814 | nouveau_display_resume(dev, runtime); |
2d38a535 | 815 | NV_DEBUG(drm, "resuming console...\n"); |
6fbb702e | 816 | nouveau_fbcon_set_suspend(dev, 0); |
9430738d | 817 | } |
5addcf0a | 818 | |
8d021d71 | 819 | nouveau_led_resume(dev); |
eeaf06ac | 820 | nouveau_svm_resume(drm); |
77145f1c | 821 | return 0; |
94580299 BS |
822 | } |
823 | ||
7bb6d442 BS |
824 | int |
825 | nouveau_pmops_suspend(struct device *dev) | |
826 | { | |
827 | struct pci_dev *pdev = to_pci_dev(dev); | |
828 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
829 | int ret; | |
830 | ||
831 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || | |
832 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
833 | return 0; | |
834 | ||
835 | ret = nouveau_do_suspend(drm_dev, false); | |
836 | if (ret) | |
837 | return ret; | |
838 | ||
839 | pci_save_state(pdev); | |
840 | pci_disable_device(pdev); | |
7bb6d442 | 841 | pci_set_power_state(pdev, PCI_D3hot); |
c5fd936e | 842 | udelay(200); |
7bb6d442 BS |
843 | return 0; |
844 | } | |
845 | ||
846 | int | |
847 | nouveau_pmops_resume(struct device *dev) | |
2d8b9ccb DA |
848 | { |
849 | struct pci_dev *pdev = to_pci_dev(dev); | |
850 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
851 | int ret; | |
852 | ||
5addcf0a DA |
853 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || |
854 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
2d8b9ccb DA |
855 | return 0; |
856 | ||
857 | pci_set_power_state(pdev, PCI_D0); | |
858 | pci_restore_state(pdev); | |
859 | ret = pci_enable_device(pdev); | |
860 | if (ret) | |
861 | return ret; | |
862 | pci_set_master(pdev); | |
863 | ||
0b2fe659 HG |
864 | ret = nouveau_do_resume(drm_dev, false); |
865 | ||
866 | /* Monitors may have been connected / disconnected during suspend */ | |
867 | schedule_work(&nouveau_drm(drm_dev)->hpd_work); | |
868 | ||
869 | return ret; | |
2d8b9ccb DA |
870 | } |
871 | ||
7bb6d442 BS |
872 | static int |
873 | nouveau_pmops_freeze(struct device *dev) | |
2d8b9ccb DA |
874 | { |
875 | struct pci_dev *pdev = to_pci_dev(dev); | |
876 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 877 | return nouveau_do_suspend(drm_dev, false); |
2d8b9ccb DA |
878 | } |
879 | ||
7bb6d442 BS |
880 | static int |
881 | nouveau_pmops_thaw(struct device *dev) | |
2d8b9ccb DA |
882 | { |
883 | struct pci_dev *pdev = to_pci_dev(dev); | |
884 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 885 | return nouveau_do_resume(drm_dev, false); |
2d8b9ccb DA |
886 | } |
887 | ||
321f5c5f | 888 | bool |
5499473c | 889 | nouveau_pmops_runtime(void) |
321f5c5f BS |
890 | { |
891 | if (nouveau_runtime_pm == -1) | |
892 | return nouveau_is_optimus() || nouveau_is_v1_dsm(); | |
893 | return nouveau_runtime_pm == 1; | |
894 | } | |
895 | ||
7bb6d442 BS |
896 | static int |
897 | nouveau_pmops_runtime_suspend(struct device *dev) | |
898 | { | |
899 | struct pci_dev *pdev = to_pci_dev(dev); | |
900 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
901 | int ret; | |
902 | ||
321f5c5f | 903 | if (!nouveau_pmops_runtime()) { |
7bb6d442 BS |
904 | pm_runtime_forbid(dev); |
905 | return -EBUSY; | |
906 | } | |
907 | ||
7bb6d442 BS |
908 | nouveau_switcheroo_optimus_dsm(); |
909 | ret = nouveau_do_suspend(drm_dev, true); | |
910 | pci_save_state(pdev); | |
911 | pci_disable_device(pdev); | |
8c863944 | 912 | pci_ignore_hotplug(pdev); |
7bb6d442 BS |
913 | pci_set_power_state(pdev, PCI_D3cold); |
914 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; | |
915 | return ret; | |
916 | } | |
917 | ||
918 | static int | |
919 | nouveau_pmops_runtime_resume(struct device *dev) | |
920 | { | |
921 | struct pci_dev *pdev = to_pci_dev(dev); | |
922 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1167c6bc | 923 | struct nvif_device *device = &nouveau_drm(drm_dev)->client.device; |
7bb6d442 BS |
924 | int ret; |
925 | ||
321f5c5f BS |
926 | if (!nouveau_pmops_runtime()) { |
927 | pm_runtime_forbid(dev); | |
928 | return -EBUSY; | |
929 | } | |
7bb6d442 BS |
930 | |
931 | pci_set_power_state(pdev, PCI_D0); | |
932 | pci_restore_state(pdev); | |
933 | ret = pci_enable_device(pdev); | |
934 | if (ret) | |
935 | return ret; | |
936 | pci_set_master(pdev); | |
937 | ||
938 | ret = nouveau_do_resume(drm_dev, true); | |
cae9ff03 | 939 | |
7bb6d442 | 940 | /* do magic */ |
a01ca78c | 941 | nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); |
7bb6d442 | 942 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
0b2fe659 HG |
943 | |
944 | /* Monitors may have been connected / disconnected during suspend */ | |
945 | schedule_work(&nouveau_drm(drm_dev)->hpd_work); | |
946 | ||
7bb6d442 BS |
947 | return ret; |
948 | } | |
949 | ||
950 | static int | |
951 | nouveau_pmops_runtime_idle(struct device *dev) | |
952 | { | |
321f5c5f | 953 | if (!nouveau_pmops_runtime()) { |
7bb6d442 BS |
954 | pm_runtime_forbid(dev); |
955 | return -EBUSY; | |
956 | } | |
957 | ||
7bb6d442 BS |
958 | pm_runtime_mark_last_busy(dev); |
959 | pm_runtime_autosuspend(dev); | |
960 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
961 | return 1; | |
962 | } | |
2d8b9ccb | 963 | |
5b8a43ae | 964 | static int |
ebb945a9 BS |
965 | nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) |
966 | { | |
ebb945a9 BS |
967 | struct nouveau_drm *drm = nouveau_drm(dev); |
968 | struct nouveau_cli *cli; | |
a2896ced | 969 | char name[32], tmpname[TASK_COMM_LEN]; |
ebb945a9 BS |
970 | int ret; |
971 | ||
5addcf0a DA |
972 | /* need to bring up power immediately if opening device */ |
973 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 974 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
975 | return ret; |
976 | ||
a2896ced MS |
977 | get_task_comm(tmpname, current); |
978 | snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); | |
fa6df8c1 | 979 | |
922a8c82 LP |
980 | if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) { |
981 | ret = -ENOMEM; | |
982 | goto done; | |
983 | } | |
420b9469 | 984 | |
20d8a88e | 985 | ret = nouveau_cli_init(drm, name, cli); |
ebb945a9 | 986 | if (ret) |
20d8a88e | 987 | goto done; |
ebb945a9 | 988 | |
0ad72863 BS |
989 | cli->base.super = false; |
990 | ||
ebb945a9 BS |
991 | fpriv->driver_priv = cli; |
992 | ||
993 | mutex_lock(&drm->client.mutex); | |
994 | list_add(&cli->head, &drm->clients); | |
995 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 996 | |
20d8a88e BS |
997 | done: |
998 | if (ret && cli) { | |
999 | nouveau_cli_fini(cli); | |
1000 | kfree(cli); | |
1001 | } | |
1002 | ||
5addcf0a DA |
1003 | pm_runtime_mark_last_busy(dev->dev); |
1004 | pm_runtime_put_autosuspend(dev->dev); | |
5addcf0a | 1005 | return ret; |
ebb945a9 BS |
1006 | } |
1007 | ||
5b8a43ae | 1008 | static void |
f0e73ff3 | 1009 | nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) |
ebb945a9 BS |
1010 | { |
1011 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
1012 | struct nouveau_drm *drm = nouveau_drm(dev); | |
1013 | ||
5addcf0a DA |
1014 | pm_runtime_get_sync(dev->dev); |
1015 | ||
ac8c7930 | 1016 | mutex_lock(&cli->mutex); |
ebb945a9 BS |
1017 | if (cli->abi16) |
1018 | nouveau_abi16_fini(cli->abi16); | |
ac8c7930 | 1019 | mutex_unlock(&cli->mutex); |
ebb945a9 BS |
1020 | |
1021 | mutex_lock(&drm->client.mutex); | |
1022 | list_del(&cli->head); | |
1023 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 1024 | |
20d8a88e BS |
1025 | nouveau_cli_fini(cli); |
1026 | kfree(cli); | |
5addcf0a DA |
1027 | pm_runtime_mark_last_busy(dev->dev); |
1028 | pm_runtime_put_autosuspend(dev->dev); | |
ebb945a9 BS |
1029 | } |
1030 | ||
baa70943 | 1031 | static const struct drm_ioctl_desc |
77145f1c | 1032 | nouveau_ioctls[] = { |
f8c47144 DV |
1033 | DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
1034 | DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1035 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
1036 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW), | |
1037 | DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
1038 | DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
1039 | DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW), | |
eeaf06ac | 1040 | DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_AUTH|DRM_RENDER_ALLOW), |
f8c47144 DV |
1041 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW), |
1042 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW), | |
1043 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
1044 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
1045 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
77145f1c BS |
1046 | }; |
1047 | ||
27111a23 BS |
1048 | long |
1049 | nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
5addcf0a | 1050 | { |
27111a23 BS |
1051 | struct drm_file *filp = file->private_data; |
1052 | struct drm_device *dev = filp->minor->dev; | |
5addcf0a | 1053 | long ret; |
5addcf0a DA |
1054 | |
1055 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 1056 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
1057 | return ret; |
1058 | ||
27111a23 BS |
1059 | switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { |
1060 | case DRM_NOUVEAU_NVIF: | |
1061 | ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); | |
1062 | break; | |
1063 | default: | |
1064 | ret = drm_ioctl(file, cmd, arg); | |
1065 | break; | |
1066 | } | |
5addcf0a DA |
1067 | |
1068 | pm_runtime_mark_last_busy(dev->dev); | |
1069 | pm_runtime_put_autosuspend(dev->dev); | |
1070 | return ret; | |
1071 | } | |
27111a23 | 1072 | |
77145f1c BS |
1073 | static const struct file_operations |
1074 | nouveau_driver_fops = { | |
1075 | .owner = THIS_MODULE, | |
1076 | .open = drm_open, | |
1077 | .release = drm_release, | |
5addcf0a | 1078 | .unlocked_ioctl = nouveau_drm_ioctl, |
77145f1c BS |
1079 | .mmap = nouveau_ttm_mmap, |
1080 | .poll = drm_poll, | |
77145f1c BS |
1081 | .read = drm_read, |
1082 | #if defined(CONFIG_COMPAT) | |
1083 | .compat_ioctl = nouveau_compat_ioctl, | |
1084 | #endif | |
1085 | .llseek = noop_llseek, | |
1086 | }; | |
1087 | ||
1088 | static struct drm_driver | |
915b4d11 | 1089 | driver_stub = { |
77145f1c | 1090 | .driver_features = |
0e975980 PA |
1091 | DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | |
1092 | DRIVER_KMS_LEGACY_CONTEXT, | |
77145f1c | 1093 | |
77145f1c | 1094 | .open = nouveau_drm_open, |
77145f1c BS |
1095 | .postclose = nouveau_drm_postclose, |
1096 | .lastclose = nouveau_vga_lastclose, | |
1097 | ||
33b903e8 | 1098 | #if defined(CONFIG_DEBUG_FS) |
56c101af | 1099 | .debugfs_init = nouveau_drm_debugfs_init, |
33b903e8 MS |
1100 | #endif |
1101 | ||
51cb4b39 BS |
1102 | .enable_vblank = nouveau_display_vblank_enable, |
1103 | .disable_vblank = nouveau_display_vblank_disable, | |
d83ef853 | 1104 | .get_scanout_position = nouveau_display_scanoutpos, |
1bf6ad62 | 1105 | .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, |
77145f1c BS |
1106 | |
1107 | .ioctls = nouveau_ioctls, | |
baa70943 | 1108 | .num_ioctls = ARRAY_SIZE(nouveau_ioctls), |
77145f1c BS |
1109 | .fops = &nouveau_driver_fops, |
1110 | ||
1111 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1112 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
ab9ccb96 AP |
1113 | .gem_prime_export = drm_gem_prime_export, |
1114 | .gem_prime_import = drm_gem_prime_import, | |
1115 | .gem_prime_pin = nouveau_gem_prime_pin, | |
3aac4502 | 1116 | .gem_prime_res_obj = nouveau_gem_prime_res_obj, |
1af7c7dd | 1117 | .gem_prime_unpin = nouveau_gem_prime_unpin, |
ab9ccb96 AP |
1118 | .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, |
1119 | .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, | |
1120 | .gem_prime_vmap = nouveau_gem_prime_vmap, | |
1121 | .gem_prime_vunmap = nouveau_gem_prime_vunmap, | |
77145f1c | 1122 | |
a51e6ac4 | 1123 | .gem_free_object_unlocked = nouveau_gem_object_del, |
77145f1c BS |
1124 | .gem_open_object = nouveau_gem_object_open, |
1125 | .gem_close_object = nouveau_gem_object_close, | |
1126 | ||
1127 | .dumb_create = nouveau_display_dumb_create, | |
1128 | .dumb_map_offset = nouveau_display_dumb_map_offset, | |
77145f1c BS |
1129 | |
1130 | .name = DRIVER_NAME, | |
1131 | .desc = DRIVER_DESC, | |
1132 | #ifdef GIT_REVISION | |
1133 | .date = GIT_REVISION, | |
1134 | #else | |
1135 | .date = DRIVER_DATE, | |
1136 | #endif | |
1137 | .major = DRIVER_MAJOR, | |
1138 | .minor = DRIVER_MINOR, | |
1139 | .patchlevel = DRIVER_PATCHLEVEL, | |
1140 | }; | |
1141 | ||
94580299 BS |
1142 | static struct pci_device_id |
1143 | nouveau_drm_pci_table[] = { | |
1144 | { | |
1145 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
1146 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1147 | .class_mask = 0xff << 16, | |
1148 | }, | |
1149 | { | |
1150 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
1151 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1152 | .class_mask = 0xff << 16, | |
1153 | }, | |
1154 | {} | |
1155 | }; | |
1156 | ||
703fa264 PM |
1157 | static void nouveau_display_options(void) |
1158 | { | |
1159 | DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); | |
1160 | ||
1161 | DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); | |
1162 | DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); | |
1163 | DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); | |
1164 | DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel); | |
1165 | DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); | |
1166 | DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); | |
1167 | DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); | |
1168 | DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); | |
1169 | DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); | |
1170 | DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); | |
f3a8b664 | 1171 | DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz); |
703fa264 PM |
1172 | } |
1173 | ||
2d8b9ccb DA |
1174 | static const struct dev_pm_ops nouveau_pm_ops = { |
1175 | .suspend = nouveau_pmops_suspend, | |
1176 | .resume = nouveau_pmops_resume, | |
1177 | .freeze = nouveau_pmops_freeze, | |
1178 | .thaw = nouveau_pmops_thaw, | |
1179 | .poweroff = nouveau_pmops_freeze, | |
1180 | .restore = nouveau_pmops_resume, | |
5addcf0a DA |
1181 | .runtime_suspend = nouveau_pmops_runtime_suspend, |
1182 | .runtime_resume = nouveau_pmops_runtime_resume, | |
1183 | .runtime_idle = nouveau_pmops_runtime_idle, | |
2d8b9ccb DA |
1184 | }; |
1185 | ||
94580299 BS |
1186 | static struct pci_driver |
1187 | nouveau_drm_pci_driver = { | |
1188 | .name = "nouveau", | |
1189 | .id_table = nouveau_drm_pci_table, | |
1190 | .probe = nouveau_drm_probe, | |
1191 | .remove = nouveau_drm_remove, | |
2d8b9ccb | 1192 | .driver.pm = &nouveau_pm_ops, |
94580299 BS |
1193 | }; |
1194 | ||
8ba9ff11 | 1195 | struct drm_device * |
e396ecd1 AC |
1196 | nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, |
1197 | struct platform_device *pdev, | |
47b2505e | 1198 | struct nvkm_device **pdevice) |
420b9469 | 1199 | { |
8ba9ff11 AC |
1200 | struct drm_device *drm; |
1201 | int err; | |
420b9469 | 1202 | |
e396ecd1 | 1203 | err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, |
7974dd1b | 1204 | true, true, ~0ULL, pdevice); |
8ba9ff11 | 1205 | if (err) |
e781dc8f | 1206 | goto err_free; |
8ba9ff11 | 1207 | |
915b4d11 | 1208 | drm = drm_dev_alloc(&driver_platform, &pdev->dev); |
0f288605 TG |
1209 | if (IS_ERR(drm)) { |
1210 | err = PTR_ERR(drm); | |
8ba9ff11 | 1211 | goto err_free; |
420b9469 AC |
1212 | } |
1213 | ||
4ac0a807 TR |
1214 | err = nouveau_drm_device_init(drm); |
1215 | if (err) | |
1216 | goto err_put; | |
1217 | ||
8ba9ff11 AC |
1218 | platform_set_drvdata(pdev, drm); |
1219 | ||
1220 | return drm; | |
1221 | ||
4ac0a807 TR |
1222 | err_put: |
1223 | drm_dev_put(drm); | |
8ba9ff11 | 1224 | err_free: |
e781dc8f | 1225 | nvkm_device_del(pdevice); |
8ba9ff11 AC |
1226 | |
1227 | return ERR_PTR(err); | |
420b9469 AC |
1228 | } |
1229 | ||
94580299 BS |
1230 | static int __init |
1231 | nouveau_drm_init(void) | |
1232 | { | |
915b4d11 | 1233 | driver_pci = driver_stub; |
915b4d11 | 1234 | driver_platform = driver_stub; |
915b4d11 | 1235 | |
703fa264 PM |
1236 | nouveau_display_options(); |
1237 | ||
77145f1c | 1238 | if (nouveau_modeset == -1) { |
77145f1c BS |
1239 | if (vgacon_text_force()) |
1240 | nouveau_modeset = 0; | |
77145f1c BS |
1241 | } |
1242 | ||
1243 | if (!nouveau_modeset) | |
1244 | return 0; | |
1245 | ||
055a65d5 AC |
1246 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER |
1247 | platform_driver_register(&nouveau_platform_driver); | |
1248 | #endif | |
1249 | ||
77145f1c | 1250 | nouveau_register_dsm_handler(); |
db1a0ae2 | 1251 | nouveau_backlight_ctor(); |
10631d72 DV |
1252 | |
1253 | #ifdef CONFIG_PCI | |
1254 | return pci_register_driver(&nouveau_drm_pci_driver); | |
1255 | #else | |
1256 | return 0; | |
1257 | #endif | |
94580299 BS |
1258 | } |
1259 | ||
1260 | static void __exit | |
1261 | nouveau_drm_exit(void) | |
1262 | { | |
77145f1c BS |
1263 | if (!nouveau_modeset) |
1264 | return; | |
1265 | ||
10631d72 DV |
1266 | #ifdef CONFIG_PCI |
1267 | pci_unregister_driver(&nouveau_drm_pci_driver); | |
1268 | #endif | |
db1a0ae2 | 1269 | nouveau_backlight_dtor(); |
77145f1c | 1270 | nouveau_unregister_dsm_handler(); |
055a65d5 AC |
1271 | |
1272 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER | |
1273 | platform_driver_unregister(&nouveau_platform_driver); | |
1274 | #endif | |
94580299 BS |
1275 | } |
1276 | ||
1277 | module_init(nouveau_drm_init); | |
1278 | module_exit(nouveau_drm_exit); | |
1279 | ||
1280 | MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); | |
77145f1c BS |
1281 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1282 | MODULE_DESCRIPTION(DRIVER_DESC); | |
94580299 | 1283 | MODULE_LICENSE("GPL and additional rights"); |