drm/nouveau/kms: Fix some indenting in nouveau_dp_detect()
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_dp.c
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1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
612a9aab 25#include <drm/drm_dp_helper.h>
b01f0608 26
4dc28134 27#include "nouveau_drv.h"
b01f0608 28#include "nouveau_connector.h"
6ee73861 29#include "nouveau_encoder.h"
27a45987 30#include "nouveau_crtc.h"
6ee73861 31
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32#include <nvif/class.h>
33#include <nvif/cl5070.h>
34
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35MODULE_PARM_DESC(mst, "Enable DisplayPort multi-stream (default: enabled)");
36static int nouveau_mst = 1;
37module_param_named(mst, nouveau_mst, int, 0400);
38
6225ee05 39static void
2aa5eac5 40nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_aux *aux, u8 *dpcd)
6225ee05 41{
77145f1c 42 struct nouveau_drm *drm = nouveau_drm(dev);
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43 u8 buf[3];
44
45 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
46 return;
47
2aa5eac5 48 if (!nvkm_rdaux(aux, DP_SINK_OUI, buf, 3))
77145f1c 49 NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
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50 buf[0], buf[1], buf[2]);
51
2aa5eac5 52 if (!nvkm_rdaux(aux, DP_BRANCH_OUI, buf, 3))
77145f1c 53 NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
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54 buf[0], buf[1], buf[2]);
55
56}
57
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58int
59nouveau_dp_detect(struct nouveau_encoder *nv_encoder)
6ee73861 60{
8777c5c1 61 struct drm_device *dev = nv_encoder->base.base.dev;
77145f1c 62 struct nouveau_drm *drm = nouveau_drm(dev);
2aa5eac5 63 struct nvkm_i2c_aux *aux;
f20c665c 64 u8 dpcd[8];
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65 int ret;
66
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67 aux = nv_encoder->aux;
68 if (!aux)
8777c5c1 69 return -ENODEV;
52e0d0ec 70
f20c665c 71 ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
6ee73861 72 if (ret)
8777c5c1 73 return ret;
6ee73861 74
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75 nv_encoder->dp.link_bw = 27000 * dpcd[1];
76 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
6ee73861 77
77145f1c 78 NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
bbcd521e 79 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
77145f1c 80 NV_DEBUG(drm, "encoder: %dx%d\n",
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81 nv_encoder->dcb->dpconf.link_nr,
82 nv_encoder->dcb->dpconf.link_bw);
6ee73861 83
75a1fccf 84 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
6ee73861 85 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
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86 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
87 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
6ee73861 88
77145f1c 89 NV_DEBUG(drm, "maximum: %dx%d\n",
bbcd521e 90 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
fe224bb7 91
2aa5eac5 92 nouveau_dp_probe_oui(dev, aux, dpcd);
52aa30f2 93
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94 ret = nv50_mstm_detect(nv_encoder->dp.mstm, dpcd, nouveau_mst);
95 if (ret == 1)
96 return NOUVEAU_DP_MST;
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97 if (ret == 0)
98 return NOUVEAU_DP_SST;
99 return ret;
6ee73861 100}
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101
102/* TODO:
103 * - Use the minimum possible BPC here, once we add support for the max bpc
104 * property.
105 * - Validate the mode against downstream port caps (see
106 * drm_dp_downstream_max_clock())
107 * - Validate against the DP caps advertised by the GPU (we don't check these
108 * yet)
109 */
110enum drm_mode_status
111nv50_dp_mode_valid(struct drm_connector *connector,
112 struct nouveau_encoder *outp,
113 const struct drm_display_mode *mode,
114 unsigned *out_clock)
115{
116 const unsigned min_clock = 25000;
117 unsigned max_clock, clock;
118 enum drm_mode_status ret;
119
120 if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace)
121 return MODE_NO_INTERLACE;
122
123 max_clock = outp->dp.link_nr * outp->dp.link_bw;
124 clock = mode->clock * (connector->display_info.bpc * 3) / 10;
125
126 ret = nouveau_conn_mode_clock_valid(mode, min_clock, max_clock,
127 &clock);
128 if (out_clock)
129 *out_clock = clock;
130 return ret;
131}