[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_channel.c

/*
 * Copyright 2005-2006 Stephane Marchesin
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"
#include "nouveau_dma.h"

static int
nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_bo *pb = chan->pushbuf_bo;
	struct nouveau_gpuobj *pushbuf = NULL;
	int ret;

	if (dev_priv->card_type >= NV_50) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
					     dev_priv->vm_end, NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_AGP, &pushbuf);
		chan->pushbuf_base = pb->bo.offset;
	} else
	if (pb->bo.mem.mem_type == TTM_PL_TT) {
		ret = nouveau_gpuobj_gart_dma_new(chan, 0,
						  dev_priv->gart_info.aper_size,
						  NV_DMA_ACCESS_RO, &pushbuf,
						  NULL);
		chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
	} else
	if (dev_priv->card_type != NV_04) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
					     dev_priv->fb_available_size,
					     NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_VIDMEM, &pushbuf);
		chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
	} else {
		/* NV04 cmdbuf hack, from original ddx.. not sure of it's
		 * exact reason for existing :)  PCI access to cmdbuf in
		 * VRAM.
		 */
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     pci_resource_start(dev->pdev,
					     1),
					     dev_priv->fb_available_size,
					     NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_PCI, &pushbuf);
		chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
	}

	nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);
	nouveau_gpuobj_ref(NULL, &pushbuf);
	return 0;
}

static struct nouveau_bo *
nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
{
	struct nouveau_bo *pushbuf = NULL;
	int location, ret;

	if (nouveau_vram_pushbuf)
		location = TTM_PL_FLAG_VRAM;
	else
		location = TTM_PL_FLAG_TT;

	ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
			     true, &pushbuf);
	if (ret) {
		NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
		return NULL;
	}

	ret = nouveau_bo_pin(pushbuf, location);
	if (ret) {
		NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
		nouveau_bo_ref(NULL, &pushbuf);
		return NULL;
	}

	return pushbuf;
}

/* allocates and initializes a fifo for user space consumption */
int
nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
		      struct drm_file *file_priv,
		      uint32_t vram_handle, uint32_t tt_handle)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_channel *chan;
	int channel, user;
	int ret;

	/*
	 * Alright, here is the full story
	 * Nvidia cards have multiple hw fifo contexts (praise them for that,
	 * no complicated crash-prone context switches)
	 * We allocate a new context for each app and let it write to it
	 * directly (woo, full userspace command submission !)
	 * When there are no more contexts, you lost
	 */
	for (channel = 0; channel < pfifo->channels; channel++) {
		if (dev_priv->fifos[channel] == NULL)
			break;
	}

	/* no more fifos. you lost. */
	if (channel == pfifo->channels)
		return -EINVAL;

	dev_priv->fifos[channel] = kzalloc(sizeof(struct nouveau_channel),
					   GFP_KERNEL);
	if (!dev_priv->fifos[channel])
		return -ENOMEM;
	chan = dev_priv->fifos[channel];
	INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
	INIT_LIST_HEAD(&chan->fence.pending);
	chan->dev = dev;
	chan->id = channel;
	chan->file_priv = file_priv;
	chan->vram_handle = vram_handle;
	chan->gart_handle = tt_handle;

	NV_INFO(dev, "Allocating FIFO number %d\n", channel);

	/* Allocate DMA push buffer */
	chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
	if (!chan->pushbuf_bo) {
		ret = -ENOMEM;
		NV_ERROR(dev, "pushbuf %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	nouveau_dma_pre_init(chan);

	/* Locate channel's user control regs */
	if (dev_priv->card_type < NV_40)
		user = NV03_USER(channel);
	else
	if (dev_priv->card_type < NV_50)
		user = NV40_USER(channel);
	else
		user = NV50_USER(channel);

	chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
								PAGE_SIZE);
	if (!chan->user) {
		NV_ERROR(dev, "ioremap of regs failed.\n");
		nouveau_channel_free(chan);
		return -ENOMEM;
	}
	chan->user_put = 0x40;
	chan->user_get = 0x44;

	/* Allocate space for per-channel fixed notifier memory */
	ret = nouveau_notifier_init_channel(chan);
	if (ret) {
		NV_ERROR(dev, "ntfy %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	/* Setup channel's default objects */
	ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
	if (ret) {
		NV_ERROR(dev, "gpuobj %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	/* Create a dma object for the push buffer */
	ret = nouveau_channel_pushbuf_ctxdma_init(chan);
	if (ret) {
		NV_ERROR(dev, "pbctxdma %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	/* disable the fifo caches */
	pfifo->reassign(dev, false);

	/* Create a graphics context for new channel */
	ret = pgraph->create_context(chan);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	/* Construct inital RAMFC for new channel */
	ret = pfifo->create_context(chan);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	pfifo->reassign(dev, true);

	ret = nouveau_dma_init(chan);
	if (!ret)
		ret = nouveau_fence_channel_init(chan);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	nouveau_debugfs_channel_init(chan);

	NV_INFO(dev, "%s: initialised FIFO %d\n", __func__, channel);
	*chan_ret = chan;
	return 0;
}

/* stops a fifo */
void
nouveau_channel_free(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	unsigned long flags;
	int ret;

	NV_INFO(dev, "%s: freeing fifo %d\n", __func__, chan->id);

	nouveau_debugfs_channel_fini(chan);

	/* Give outstanding push buffers a chance to complete */
	nouveau_fence_update(chan);
	if (chan->fence.sequence != chan->fence.sequence_ack) {
		struct nouveau_fence *fence = NULL;

		ret = nouveau_fence_new(chan, &fence, true);
		if (ret == 0) {
			ret = nouveau_fence_wait(fence, NULL, false, false);
			nouveau_fence_unref((void *)&fence);
		}

		if (ret)
			NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
	}

	/* Ensure all outstanding fences are signaled.  They should be if the
	 * above attempts at idling were OK, but if we failed this'll tell TTM
	 * we're done with the buffers.
	 */
	nouveau_fence_channel_fini(chan);

	/* This will prevent pfifo from switching channels. */
	pfifo->reassign(dev, false);

	/* We want to give pgraph a chance to idle and get rid of all potential
	 * errors. We need to do this before the lock, otherwise the irq handler
	 * is unable to process them.
	 */
	if (pgraph->channel(dev) == chan)
		nouveau_wait_for_idle(dev);

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);

	pgraph->fifo_access(dev, false);
	if (pgraph->channel(dev) == chan)
		pgraph->unload_context(dev);
	pgraph->destroy_context(chan);
	pgraph->fifo_access(dev, true);

	if (pfifo->channel_id(dev) == chan->id) {
		pfifo->disable(dev);
		pfifo->unload_context(dev);
		pfifo->enable(dev);
	}
	pfifo->destroy_context(chan);

	pfifo->reassign(dev, true);

	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	/* Release the channel's resources */
	nouveau_gpuobj_ref(NULL, &chan->pushbuf);
	if (chan->pushbuf_bo) {
		nouveau_bo_unmap(chan->pushbuf_bo);
		nouveau_bo_unpin(chan->pushbuf_bo);
		nouveau_bo_ref(NULL, &chan->pushbuf_bo);
	}
	nouveau_gpuobj_channel_takedown(chan);
	nouveau_notifier_takedown_channel(chan);
	if (chan->user)
		iounmap(chan->user);

	dev_priv->fifos[chan->id] = NULL;
	kfree(chan);
}

/* cleans up all the fifos from file_priv */
void
nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	int i;

	NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
	for (i = 0; i < engine->fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->fifos[i];

		if (chan && chan->file_priv == file_priv)
			nouveau_channel_free(chan);
	}
}

int
nouveau_channel_owner(struct drm_device *dev, struct drm_file *file_priv,
		      int channel)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;

	if (channel >= engine->fifo.channels)
		return 0;
	if (dev_priv->fifos[channel] == NULL)
		return 0;

	return (dev_priv->fifos[channel]->file_priv == file_priv);
}

/***********************************
 * ioctls wrapping the functions
 ***********************************/

static int
nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_nouveau_channel_alloc *init = data;
	struct nouveau_channel *chan;
	int ret;

	if (dev_priv->engine.graph.accel_blocked)
		return -ENODEV;

	if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
		return -EINVAL;

	ret = nouveau_channel_alloc(dev, &chan, file_priv,
				    init->fb_ctxdma_handle,
				    init->tt_ctxdma_handle);
	if (ret)
		return ret;
	init->channel  = chan->id;

	if (chan->dma.ib_max)
		init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
					NOUVEAU_GEM_DOMAIN_GART;
	else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
		init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
	else
		init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;

	init->subchan[0].handle = NvM2MF;
	if (dev_priv->card_type < NV_50)
		init->subchan[0].grclass = 0x0039;
	else
		init->subchan[0].grclass = 0x5039;
	init->subchan[1].handle = NvSw;
	init->subchan[1].grclass = NV_SW;
	init->nr_subchan = 2;

	/* Named memory object area */
	ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
				    &init->notifier_handle);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	return 0;
}

static int
nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	struct drm_nouveau_channel_free *cfree = data;
	struct nouveau_channel *chan;

	NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);

	nouveau_channel_free(chan);
	return 0;
}

/***********************************
 * finally, the ioctl table
 ***********************************/

struct drm_ioctl_desc nouveau_ioctls[] = {
	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
};

int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005-2006 Stephane Marchesin
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include "drmP.h"
	26	#include "drm.h"
	27	#include "nouveau_drv.h"
	28	#include "nouveau_drm.h"
	29	#include "nouveau_dma.h"
	30
	31	static int
	32	nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
	33	{
	34	struct drm_device *dev = chan->dev;
	35	struct drm_nouveau_private *dev_priv = dev->dev_private;
	36	struct nouveau_bo *pb = chan->pushbuf_bo;
	37	struct nouveau_gpuobj *pushbuf = NULL;
6ee73861 BS	38	int ret;
6ee73861 BS	39
d87897d4 BS	40	if (dev_priv->card_type >= NV_50) {
	41	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
	42	dev_priv->vm_end, NV_DMA_ACCESS_RO,
	43	NV_DMA_TARGET_AGP, &pushbuf);
	44	chan->pushbuf_base = pb->bo.offset;
	45	} else
6ee73861 BS	46	if (pb->bo.mem.mem_type == TTM_PL_TT) {
	47	ret = nouveau_gpuobj_gart_dma_new(chan, 0,
	48	dev_priv->gart_info.aper_size,
	49	NV_DMA_ACCESS_RO, &pushbuf,
	50	NULL);
d961db75	51	chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
6ee73861 BS	52	} else
	53	if (dev_priv->card_type != NV_04) {
	54	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
	55	dev_priv->fb_available_size,
	56	NV_DMA_ACCESS_RO,
	57	NV_DMA_TARGET_VIDMEM, &pushbuf);
d961db75	58	chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
6ee73861 BS	59	} else {
	60	/* NV04 cmdbuf hack, from original ddx.. not sure of it's
	61	* exact reason for existing :) PCI access to cmdbuf in
	62	* VRAM.
	63	*/
	64	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
01d73a69 JC	65	pci_resource_start(dev->pdev,
01d73a69 JC	66	1),
6ee73861 BS	67	dev_priv->fb_available_size,
	68	NV_DMA_ACCESS_RO,
	69	NV_DMA_TARGET_PCI, &pushbuf);
d961db75	70	chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
6ee73861 BS	71	}
6ee73861 BS	72
a8eaebc6 BS	73	nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);
a8eaebc6 BS	74	nouveau_gpuobj_ref(NULL, &pushbuf);
6ee73861 BS	75	return 0;
	76	}
	77
	78	static struct nouveau_bo *
	79	nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
	80	{
	81	struct nouveau_bo *pushbuf = NULL;
	82	int location, ret;
	83
	84	if (nouveau_vram_pushbuf)
	85	location = TTM_PL_FLAG_VRAM;
	86	else
	87	location = TTM_PL_FLAG_TT;
	88
	89	ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
	90	true, &pushbuf);
	91	if (ret) {
	92	NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
	93	return NULL;
	94	}
	95
	96	ret = nouveau_bo_pin(pushbuf, location);
	97	if (ret) {
	98	NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
	99	nouveau_bo_ref(NULL, &pushbuf);
	100	return NULL;
	101	}
	102
	103	return pushbuf;
	104	}
	105
	106	/* allocates and initializes a fifo for user space consumption */
	107	int
	108	nouveau_channel_alloc(struct drm_device dev, struct nouveau_channel *chan_ret,
	109	struct drm_file *file_priv,
	110	uint32_t vram_handle, uint32_t tt_handle)
	111	{
	112	struct drm_nouveau_private *dev_priv = dev->dev_private;
	113	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	114	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	115	struct nouveau_channel *chan;
	116	int channel, user;
	117	int ret;
	118
	119	/*
	120	* Alright, here is the full story
	121	* Nvidia cards have multiple hw fifo contexts (praise them for that,
	122	* no complicated crash-prone context switches)
	123	* We allocate a new context for each app and let it write to it
	124	* directly (woo, full userspace command submission !)
	125	* When there are no more contexts, you lost
	126	*/
	127	for (channel = 0; channel < pfifo->channels; channel++) {
	128	if (dev_priv->fifos[channel] == NULL)
	129	break;
	130	}
	131
	132	/* no more fifos. you lost. */
	133	if (channel == pfifo->channels)
	134	return -EINVAL;
	135
	136	dev_priv->fifos[channel] = kzalloc(sizeof(struct nouveau_channel),
	137	GFP_KERNEL);
	138	if (!dev_priv->fifos[channel])
139	return -ENOMEM;
6ee73861 BS	140	chan = dev_priv->fifos[channel];
	141	INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
	142	INIT_LIST_HEAD(&chan->fence.pending);
	143	chan->dev = dev;
	144	chan->id = channel;
	145	chan->file_priv = file_priv;
	146	chan->vram_handle = vram_handle;
	147	chan->gart_handle = tt_handle;
	148
	149	NV_INFO(dev, "Allocating FIFO number %d\n", channel);
	150
	151	/* Allocate DMA push buffer */
	152	chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
	153	if (!chan->pushbuf_bo) {
	154	ret = -ENOMEM;
	155	NV_ERROR(dev, "pushbuf %d\n", ret);
	156	nouveau_channel_free(chan);
	157	return ret;
	158	}
	159
75c99da6 BS	160	nouveau_dma_pre_init(chan);
75c99da6 BS	161
6ee73861 BS	162	/* Locate channel's user control regs */
	163	if (dev_priv->card_type < NV_40)
	164	user = NV03_USER(channel);
	165	else
	166	if (dev_priv->card_type < NV_50)
	167	user = NV40_USER(channel);
	168	else
	169	user = NV50_USER(channel);
	170
	171	chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
	172	PAGE_SIZE);
	173	if (!chan->user) {
	174	NV_ERROR(dev, "ioremap of regs failed.\n");
	175	nouveau_channel_free(chan);
	176	return -ENOMEM;
	177	}
	178	chan->user_put = 0x40;
	179	chan->user_get = 0x44;
	180
	181	/* Allocate space for per-channel fixed notifier memory */
	182	ret = nouveau_notifier_init_channel(chan);
	183	if (ret) {
	184	NV_ERROR(dev, "ntfy %d\n", ret);
	185	nouveau_channel_free(chan);
	186	return ret;
	187	}
	188
	189	/* Setup channel's default objects */
	190	ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
	191	if (ret) {
	192	NV_ERROR(dev, "gpuobj %d\n", ret);
	193	nouveau_channel_free(chan);
	194	return ret;
	195	}
	196
	197	/* Create a dma object for the push buffer */
	198	ret = nouveau_channel_pushbuf_ctxdma_init(chan);
	199	if (ret) {
	200	NV_ERROR(dev, "pbctxdma %d\n", ret);
	201	nouveau_channel_free(chan);
	202	return ret;
	203	}
	204
	205	/* disable the fifo caches */
	206	pfifo->reassign(dev, false);
	207
	208	/* Create a graphics context for new channel */
	209	ret = pgraph->create_context(chan);
	210	if (ret) {
	211	nouveau_channel_free(chan);
	212	return ret;
	213	}
	214
	215	/* Construct inital RAMFC for new channel */
	216	ret = pfifo->create_context(chan);
	217	if (ret) {
	218	nouveau_channel_free(chan);
	219	return ret;
	220	}
	221
	222	pfifo->reassign(dev, true);
	223
	224	ret = nouveau_dma_init(chan);
	225	if (!ret)
2730723b	226	ret = nouveau_fence_channel_init(chan);
6ee73861 BS	227	if (ret) {
	228	nouveau_channel_free(chan);
	229	return ret;
	230	}
	231
	232	nouveau_debugfs_channel_init(chan);
	233
	234	NV_INFO(dev, "%s: initialised FIFO %d\n", __func__, channel);
	235	*chan_ret = chan;
	236	return 0;
	237	}
	238
6ee73861 BS	239	/* stops a fifo */
	240	void
	241	nouveau_channel_free(struct nouveau_channel *chan)
	242	{
	243	struct drm_device *dev = chan->dev;
	244	struct drm_nouveau_private *dev_priv = dev->dev_private;
	245	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	246	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	247	unsigned long flags;
	248	int ret;
	249
	250	NV_INFO(dev, "%s: freeing fifo %d\n", __func__, chan->id);
	251
	252	nouveau_debugfs_channel_fini(chan);
	253
	254	/* Give outstanding push buffers a chance to complete */
6ee73861	255	nouveau_fence_update(chan);
6ee73861 BS	256	if (chan->fence.sequence != chan->fence.sequence_ack) {
	257	struct nouveau_fence *fence = NULL;
	258
	259	ret = nouveau_fence_new(chan, &fence, true);
	260	if (ret == 0) {
	261	ret = nouveau_fence_wait(fence, NULL, false, false);
	262	nouveau_fence_unref((void *)&fence);
	263	}
	264
	265	if (ret)
	266	NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
	267	}
	268
	269	/* Ensure all outstanding fences are signaled. They should be if the
	270	* above attempts at idling were OK, but if we failed this'll tell TTM
	271	* we're done with the buffers.
	272	*/
2730723b	273	nouveau_fence_channel_fini(chan);
6ee73861	274
ff9e5279	275	/* This will prevent pfifo from switching channels. */
6ee73861 BS	276	pfifo->reassign(dev, false);
6ee73861 BS	277
ff9e5279 MM	278	/* We want to give pgraph a chance to idle and get rid of all potential
	279	* errors. We need to do this before the lock, otherwise the irq handler
	280	* is unable to process them.
	281	*/
	282	if (pgraph->channel(dev) == chan)
	283	nouveau_wait_for_idle(dev);
	284
	285	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	286
a51a3bf5 MM	287	pgraph->fifo_access(dev, false);
a51a3bf5 MM	288	if (pgraph->channel(dev) == chan)
6ee73861	289	pgraph->unload_context(dev);
6ee73861	290	pgraph->destroy_context(chan);
a51a3bf5	291	pgraph->fifo_access(dev, true);
6ee73861 BS	292
	293	if (pfifo->channel_id(dev) == chan->id) {
	294	pfifo->disable(dev);
	295	pfifo->unload_context(dev);
	296	pfifo->enable(dev);
	297	}
	298	pfifo->destroy_context(chan);
	299
	300	pfifo->reassign(dev, true);
	301
ff9e5279 MM	302	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
ff9e5279 MM	303
6ee73861	304	/* Release the channel's resources */
a8eaebc6	305	nouveau_gpuobj_ref(NULL, &chan->pushbuf);
6ee73861	306	if (chan->pushbuf_bo) {
9d59e8a1	307	nouveau_bo_unmap(chan->pushbuf_bo);
6ee73861 BS	308	nouveau_bo_unpin(chan->pushbuf_bo);
	309	nouveau_bo_ref(NULL, &chan->pushbuf_bo);
	310	}
	311	nouveau_gpuobj_channel_takedown(chan);
	312	nouveau_notifier_takedown_channel(chan);
	313	if (chan->user)
	314	iounmap(chan->user);
	315
	316	dev_priv->fifos[chan->id] = NULL;
6ee73861 BS	317	kfree(chan);
	318	}
	319
	320	/* cleans up all the fifos from file_priv */
	321	void
	322	nouveau_channel_cleanup(struct drm_device dev, struct drm_file file_priv)
	323	{
	324	struct drm_nouveau_private *dev_priv = dev->dev_private;
	325	struct nouveau_engine *engine = &dev_priv->engine;
	326	int i;
	327
	328	NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
	329	for (i = 0; i < engine->fifo.channels; i++) {
	330	struct nouveau_channel *chan = dev_priv->fifos[i];
	331
	332	if (chan && chan->file_priv == file_priv)
	333	nouveau_channel_free(chan);
	334	}
	335	}
	336
	337	int
	338	nouveau_channel_owner(struct drm_device dev, struct drm_file file_priv,
	339	int channel)
	340	{
	341	struct drm_nouveau_private *dev_priv = dev->dev_private;
	342	struct nouveau_engine *engine = &dev_priv->engine;
	343
	344	if (channel >= engine->fifo.channels)
	345	return 0;
	346	if (dev_priv->fifos[channel] == NULL)
	347	return 0;
	348
	349	return (dev_priv->fifos[channel]->file_priv == file_priv);
	350	}
	351
	352	/***********************************
	353	* ioctls wrapping the functions
	354	***********************************/
	355
	356	static int
	357	nouveau_ioctl_fifo_alloc(struct drm_device dev, void data,
	358	struct drm_file *file_priv)
	359	{
	360	struct drm_nouveau_private *dev_priv = dev->dev_private;
	361	struct drm_nouveau_channel_alloc *init = data;
	362	struct nouveau_channel *chan;
	363	int ret;
	364
6ee73861 BS	365	if (dev_priv->engine.graph.accel_blocked)
	366	return -ENODEV;
	367
	368	if (init->fb_ctxdma_handle == ~0 \|\| init->tt_ctxdma_handle == ~0)
	369	return -EINVAL;
	370
	371	ret = nouveau_channel_alloc(dev, &chan, file_priv,
	372	init->fb_ctxdma_handle,
	373	init->tt_ctxdma_handle);
	374	if (ret)
	375	return ret;
	376	init->channel = chan->id;
	377
a1606a95 BS	378	if (chan->dma.ib_max)
	379	init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM \|
	380	NOUVEAU_GEM_DOMAIN_GART;
	381	else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
	382	init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
	383	else
	384	init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
	385
6ee73861 BS	386	init->subchan[0].handle = NvM2MF;
	387	if (dev_priv->card_type < NV_50)
	388	init->subchan[0].grclass = 0x0039;
	389	else
	390	init->subchan[0].grclass = 0x5039;
f03a314b FJ	391	init->subchan[1].handle = NvSw;
	392	init->subchan[1].grclass = NV_SW;
	393	init->nr_subchan = 2;
6ee73861 BS	394
	395	/* Named memory object area */
	396	ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
	397	&init->notifier_handle);
	398	if (ret) {
	399	nouveau_channel_free(chan);
	400	return ret;
	401	}
	402
	403	return 0;
	404	}
	405
	406	static int
	407	nouveau_ioctl_fifo_free(struct drm_device dev, void data,
	408	struct drm_file *file_priv)
	409	{
	410	struct drm_nouveau_channel_free *cfree = data;
	411	struct nouveau_channel *chan;
	412
6ee73861 BS	413	NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);
	414
	415	nouveau_channel_free(chan);
	416	return 0;
	417	}
	418
	419	/***********************************
	420	* finally, the ioctl table
	421	***********************************/
	422
	423	struct drm_ioctl_desc nouveau_ioctls[] = {
1b2f1489 DA	424	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
	425	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	426	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
	427	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
	428	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
	429	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
	430	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
	431	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
	432	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
	433	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
	434	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
	435	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
6ee73861 BS	436	};
	437
	438	int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);