[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_channel.c

/*
 * Copyright 2005-2006 Stephane Marchesin
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"
#include "nouveau_dma.h"

static int
nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_bo *pb = chan->pushbuf_bo;
	struct nouveau_gpuobj *pushbuf = NULL;
	uint32_t start = pb->bo.mem.mm_node->start << PAGE_SHIFT;
	int ret;

	if (pb->bo.mem.mem_type == TTM_PL_TT) {
		ret = nouveau_gpuobj_gart_dma_new(chan, 0,
						  dev_priv->gart_info.aper_size,
						  NV_DMA_ACCESS_RO, &pushbuf,
						  NULL);
		chan->pushbuf_base = start;
	} else
	if (dev_priv->card_type != NV_04) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
					     dev_priv->fb_available_size,
					     NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_VIDMEM, &pushbuf);
		chan->pushbuf_base = start;
	} else {
		/* NV04 cmdbuf hack, from original ddx.. not sure of it's
		 * exact reason for existing :)  PCI access to cmdbuf in
		 * VRAM.
		 */
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     drm_get_resource_start(dev, 1),
					     dev_priv->fb_available_size,
					     NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_PCI, &pushbuf);
		chan->pushbuf_base = start;
	}

	ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf);
	if (ret) {
		NV_ERROR(dev, "Error referencing pushbuf ctxdma: %d\n", ret);
		if (pushbuf != dev_priv->gart_info.sg_ctxdma)
			nouveau_gpuobj_del(dev, &pushbuf);
		return ret;
	}

	return 0;
}

static struct nouveau_bo *
nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
{
	struct nouveau_bo *pushbuf = NULL;
	int location, ret;

	if (nouveau_vram_pushbuf)
		location = TTM_PL_FLAG_VRAM;
	else
		location = TTM_PL_FLAG_TT;

	ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
			     true, &pushbuf);
	if (ret) {
		NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
		return NULL;
	}

	ret = nouveau_bo_pin(pushbuf, location);
	if (ret) {
		NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
		nouveau_bo_ref(NULL, &pushbuf);
		return NULL;
	}

	return pushbuf;
}

/* allocates and initializes a fifo for user space consumption */
int
nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
		      struct drm_file *file_priv,
		      uint32_t vram_handle, uint32_t tt_handle)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_channel *chan;
	int channel, user;
	int ret;

	/*
	 * Alright, here is the full story
	 * Nvidia cards have multiple hw fifo contexts (praise them for that,
	 * no complicated crash-prone context switches)
	 * We allocate a new context for each app and let it write to it
	 * directly (woo, full userspace command submission !)
	 * When there are no more contexts, you lost
	 */
	for (channel = 0; channel < pfifo->channels; channel++) {
		if (dev_priv->fifos[channel] == NULL)
			break;
	}

	/* no more fifos. you lost. */
	if (channel == pfifo->channels)
		return -EINVAL;

	dev_priv->fifos[channel] = kzalloc(sizeof(struct nouveau_channel),
					   GFP_KERNEL);
	if (!dev_priv->fifos[channel])
		return -ENOMEM;
	dev_priv->fifo_alloc_count++;
	chan = dev_priv->fifos[channel];
	INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
	INIT_LIST_HEAD(&chan->fence.pending);
	chan->dev = dev;
	chan->id = channel;
	chan->file_priv = file_priv;
	chan->vram_handle = vram_handle;
	chan->gart_handle = tt_handle;

	NV_INFO(dev, "Allocating FIFO number %d\n", channel);

	/* Allocate DMA push buffer */
	chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
	if (!chan->pushbuf_bo) {
		ret = -ENOMEM;
		NV_ERROR(dev, "pushbuf %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	nouveau_dma_pre_init(chan);

	/* Locate channel's user control regs */
	if (dev_priv->card_type < NV_40)
		user = NV03_USER(channel);
	else
	if (dev_priv->card_type < NV_50)
		user = NV40_USER(channel);
	else
		user = NV50_USER(channel);

	chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
								PAGE_SIZE);
	if (!chan->user) {
		NV_ERROR(dev, "ioremap of regs failed.\n");
		nouveau_channel_free(chan);
		return -ENOMEM;
	}
	chan->user_put = 0x40;
	chan->user_get = 0x44;

	/* Allocate space for per-channel fixed notifier memory */
	ret = nouveau_notifier_init_channel(chan);
	if (ret) {
		NV_ERROR(dev, "ntfy %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	/* Setup channel's default objects */
	ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
	if (ret) {
		NV_ERROR(dev, "gpuobj %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	/* Create a dma object for the push buffer */
	ret = nouveau_channel_pushbuf_ctxdma_init(chan);
	if (ret) {
		NV_ERROR(dev, "pbctxdma %d\n", ret);
		nouveau_channel_free(chan);
		return ret;
	}

	/* disable the fifo caches */
	pfifo->reassign(dev, false);

	/* Create a graphics context for new channel */
	ret = pgraph->create_context(chan);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	/* Construct inital RAMFC for new channel */
	ret = pfifo->create_context(chan);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	pfifo->reassign(dev, true);

	ret = nouveau_dma_init(chan);
	if (!ret)
		ret = nouveau_fence_init(chan);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	nouveau_debugfs_channel_init(chan);

	NV_INFO(dev, "%s: initialised FIFO %d\n", __func__, channel);
	*chan_ret = chan;
	return 0;
}

/* stops a fifo */
void
nouveau_channel_free(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	unsigned long flags;
	int ret;

	NV_INFO(dev, "%s: freeing fifo %d\n", __func__, chan->id);

	nouveau_debugfs_channel_fini(chan);

	/* Give outstanding push buffers a chance to complete */
	spin_lock_irqsave(&chan->fence.lock, flags);
	nouveau_fence_update(chan);
	spin_unlock_irqrestore(&chan->fence.lock, flags);
	if (chan->fence.sequence != chan->fence.sequence_ack) {
		struct nouveau_fence *fence = NULL;

		ret = nouveau_fence_new(chan, &fence, true);
		if (ret == 0) {
			ret = nouveau_fence_wait(fence, NULL, false, false);
			nouveau_fence_unref((void *)&fence);
		}

		if (ret)
			NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
	}

	/* Ensure all outstanding fences are signaled.  They should be if the
	 * above attempts at idling were OK, but if we failed this'll tell TTM
	 * we're done with the buffers.
	 */
	nouveau_fence_fini(chan);

	/* Ensure the channel is no longer active on the GPU */
	pfifo->reassign(dev, false);

	pgraph->fifo_access(dev, false);
	if (pgraph->channel(dev) == chan)
		pgraph->unload_context(dev);
	pgraph->destroy_context(chan);
	pgraph->fifo_access(dev, true);

	if (pfifo->channel_id(dev) == chan->id) {
		pfifo->disable(dev);
		pfifo->unload_context(dev);
		pfifo->enable(dev);
	}
	pfifo->destroy_context(chan);

	pfifo->reassign(dev, true);

	/* Release the channel's resources */
	nouveau_gpuobj_ref_del(dev, &chan->pushbuf);
	if (chan->pushbuf_bo) {
		nouveau_bo_unpin(chan->pushbuf_bo);
		nouveau_bo_ref(NULL, &chan->pushbuf_bo);
	}
	nouveau_gpuobj_channel_takedown(chan);
	nouveau_notifier_takedown_channel(chan);
	if (chan->user)
		iounmap(chan->user);

	dev_priv->fifos[chan->id] = NULL;
	dev_priv->fifo_alloc_count--;
	kfree(chan);
}

/* cleans up all the fifos from file_priv */
void
nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	int i;

	NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
	for (i = 0; i < engine->fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->fifos[i];

		if (chan && chan->file_priv == file_priv)
			nouveau_channel_free(chan);
	}
}

int
nouveau_channel_owner(struct drm_device *dev, struct drm_file *file_priv,
		      int channel)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;

	if (channel >= engine->fifo.channels)
		return 0;
	if (dev_priv->fifos[channel] == NULL)
		return 0;

	return (dev_priv->fifos[channel]->file_priv == file_priv);
}

/***********************************
 * ioctls wrapping the functions
 ***********************************/

static int
nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_nouveau_channel_alloc *init = data;
	struct nouveau_channel *chan;
	int ret;

	NOUVEAU_CHECK_INITIALISED_WITH_RETURN;

	if (dev_priv->engine.graph.accel_blocked)
		return -ENODEV;

	if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
		return -EINVAL;

	ret = nouveau_channel_alloc(dev, &chan, file_priv,
				    init->fb_ctxdma_handle,
				    init->tt_ctxdma_handle);
	if (ret)
		return ret;
	init->channel  = chan->id;

	init->subchan[0].handle = NvM2MF;
	if (dev_priv->card_type < NV_50)
		init->subchan[0].grclass = 0x0039;
	else
		init->subchan[0].grclass = 0x5039;
	init->subchan[1].handle = NvSw;
	init->subchan[1].grclass = NV_SW;
	init->nr_subchan = 2;

	/* Named memory object area */
	ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
				    &init->notifier_handle);
	if (ret) {
		nouveau_channel_free(chan);
		return ret;
	}

	return 0;
}

static int
nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	struct drm_nouveau_channel_free *cfree = data;
	struct nouveau_channel *chan;

	NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
	NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);

	nouveau_channel_free(chan);
	return 0;
}

/***********************************
 * finally, the ioctl table
 ***********************************/

struct drm_ioctl_desc nouveau_ioctls[] = {
	DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL, nouveau_gem_ioctl_pushbuf_call, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PIN, nouveau_gem_ioctl_pin, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_UNPIN, nouveau_gem_ioctl_unpin, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL2, nouveau_gem_ioctl_pushbuf_call2, DRM_AUTH),
};

int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005-2006 Stephane Marchesin
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include "drmP.h"
	26	#include "drm.h"
	27	#include "nouveau_drv.h"
	28	#include "nouveau_drm.h"
	29	#include "nouveau_dma.h"
	30
	31	static int
	32	nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
	33	{
	34	struct drm_device *dev = chan->dev;
	35	struct drm_nouveau_private *dev_priv = dev->dev_private;
	36	struct nouveau_bo *pb = chan->pushbuf_bo;
	37	struct nouveau_gpuobj *pushbuf = NULL;
	38	uint32_t start = pb->bo.mem.mm_node->start << PAGE_SHIFT;
	39	int ret;
	40
	41	if (pb->bo.mem.mem_type == TTM_PL_TT) {
	42	ret = nouveau_gpuobj_gart_dma_new(chan, 0,
	43	dev_priv->gart_info.aper_size,
	44	NV_DMA_ACCESS_RO, &pushbuf,
	45	NULL);
	46	chan->pushbuf_base = start;
	47	} else
	48	if (dev_priv->card_type != NV_04) {
	49	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
	50	dev_priv->fb_available_size,
	51	NV_DMA_ACCESS_RO,
	52	NV_DMA_TARGET_VIDMEM, &pushbuf);
	53	chan->pushbuf_base = start;
	54	} else {
	55	/* NV04 cmdbuf hack, from original ddx.. not sure of it's
	56	* exact reason for existing :) PCI access to cmdbuf in
	57	* VRAM.
	58	*/
	59	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
	60	drm_get_resource_start(dev, 1),
	61	dev_priv->fb_available_size,
	62	NV_DMA_ACCESS_RO,
	63	NV_DMA_TARGET_PCI, &pushbuf);
	64	chan->pushbuf_base = start;
65	}
66
67	ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf);
68	if (ret) {
69	NV_ERROR(dev, "Error referencing pushbuf ctxdma: %d\n", ret);
70	if (pushbuf != dev_priv->gart_info.sg_ctxdma)
71	nouveau_gpuobj_del(dev, &pushbuf);
72	return ret;
73	}
74
75	return 0;
76	}
77
78	static struct nouveau_bo *
79	nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
80	{
81	struct nouveau_bo *pushbuf = NULL;
82	int location, ret;
83
84	if (nouveau_vram_pushbuf)
85	location = TTM_PL_FLAG_VRAM;
86	else
87	location = TTM_PL_FLAG_TT;
88
89	ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
90	true, &pushbuf);
91	if (ret) {
92	NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
93	return NULL;
94	}
95
96	ret = nouveau_bo_pin(pushbuf, location);
97	if (ret) {
98	NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
99	nouveau_bo_ref(NULL, &pushbuf);
100	return NULL;
101	}
102
103	return pushbuf;
104	}
105
106	/* allocates and initializes a fifo for user space consumption */
107	int
108	nouveau_channel_alloc(struct drm_device dev, struct nouveau_channel *chan_ret,
109	struct drm_file *file_priv,
110	uint32_t vram_handle, uint32_t tt_handle)
111	{
112	struct drm_nouveau_private *dev_priv = dev->dev_private;
113	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
114	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
115	struct nouveau_channel *chan;
116	int channel, user;
117	int ret;
118
119	/*
120	* Alright, here is the full story
121	* Nvidia cards have multiple hw fifo contexts (praise them for that,
122	* no complicated crash-prone context switches)
123	* We allocate a new context for each app and let it write to it
124	* directly (woo, full userspace command submission !)
125	* When there are no more contexts, you lost
126	*/
127	for (channel = 0; channel < pfifo->channels; channel++) {
128	if (dev_priv->fifos[channel] == NULL)
129	break;
130	}
131
132	/* no more fifos. you lost. */
133	if (channel == pfifo->channels)
134	return -EINVAL;
135
136	dev_priv->fifos[channel] = kzalloc(sizeof(struct nouveau_channel),
137	GFP_KERNEL);
138	if (!dev_priv->fifos[channel])
139	return -ENOMEM;
140	dev_priv->fifo_alloc_count++;
141	chan = dev_priv->fifos[channel];
142	INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
143	INIT_LIST_HEAD(&chan->fence.pending);
144	chan->dev = dev;
145	chan->id = channel;
146	chan->file_priv = file_priv;
147	chan->vram_handle = vram_handle;
148	chan->gart_handle = tt_handle;
149
150	NV_INFO(dev, "Allocating FIFO number %d\n", channel);
151
152	/* Allocate DMA push buffer */
153	chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
154	if (!chan->pushbuf_bo) {
155	ret = -ENOMEM;
156	NV_ERROR(dev, "pushbuf %d\n", ret);
157	nouveau_channel_free(chan);
158	return ret;
159	}
160
75c99da6 BS	161	nouveau_dma_pre_init(chan);
75c99da6 BS	162
6ee73861 BS	163	/* Locate channel's user control regs */
	164	if (dev_priv->card_type < NV_40)
	165	user = NV03_USER(channel);
	166	else
	167	if (dev_priv->card_type < NV_50)
	168	user = NV40_USER(channel);
	169	else
	170	user = NV50_USER(channel);
	171
	172	chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
	173	PAGE_SIZE);
	174	if (!chan->user) {
	175	NV_ERROR(dev, "ioremap of regs failed.\n");
	176	nouveau_channel_free(chan);
	177	return -ENOMEM;
	178	}
	179	chan->user_put = 0x40;
	180	chan->user_get = 0x44;
	181
	182	/* Allocate space for per-channel fixed notifier memory */
	183	ret = nouveau_notifier_init_channel(chan);
	184	if (ret) {
	185	NV_ERROR(dev, "ntfy %d\n", ret);
	186	nouveau_channel_free(chan);
	187	return ret;
	188	}
	189
	190	/* Setup channel's default objects */
	191	ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
	192	if (ret) {
	193	NV_ERROR(dev, "gpuobj %d\n", ret);
	194	nouveau_channel_free(chan);
	195	return ret;
	196	}
	197
	198	/* Create a dma object for the push buffer */
	199	ret = nouveau_channel_pushbuf_ctxdma_init(chan);
	200	if (ret) {
	201	NV_ERROR(dev, "pbctxdma %d\n", ret);
	202	nouveau_channel_free(chan);
	203	return ret;
	204	}
	205
	206	/* disable the fifo caches */
	207	pfifo->reassign(dev, false);
	208
	209	/* Create a graphics context for new channel */
	210	ret = pgraph->create_context(chan);
	211	if (ret) {
	212	nouveau_channel_free(chan);
	213	return ret;
	214	}
	215
	216	/* Construct inital RAMFC for new channel */
	217	ret = pfifo->create_context(chan);
	218	if (ret) {
	219	nouveau_channel_free(chan);
	220	return ret;
	221	}
	222
	223	pfifo->reassign(dev, true);
	224
	225	ret = nouveau_dma_init(chan);
	226	if (!ret)
227	ret = nouveau_fence_init(chan);
228	if (ret) {
229	nouveau_channel_free(chan);
230	return ret;
231	}
232
233	nouveau_debugfs_channel_init(chan);
234
235	NV_INFO(dev, "%s: initialised FIFO %d\n", __func__, channel);
236	*chan_ret = chan;
237	return 0;
238	}
239
6ee73861 BS	240	/* stops a fifo */
	241	void
	242	nouveau_channel_free(struct nouveau_channel *chan)
	243	{
	244	struct drm_device *dev = chan->dev;
	245	struct drm_nouveau_private *dev_priv = dev->dev_private;
	246	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	247	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	248	unsigned long flags;
	249	int ret;
	250
	251	NV_INFO(dev, "%s: freeing fifo %d\n", __func__, chan->id);
	252
	253	nouveau_debugfs_channel_fini(chan);
	254
	255	/* Give outstanding push buffers a chance to complete */
	256	spin_lock_irqsave(&chan->fence.lock, flags);
	257	nouveau_fence_update(chan);
	258	spin_unlock_irqrestore(&chan->fence.lock, flags);
	259	if (chan->fence.sequence != chan->fence.sequence_ack) {
	260	struct nouveau_fence *fence = NULL;
	261
	262	ret = nouveau_fence_new(chan, &fence, true);
	263	if (ret == 0) {
	264	ret = nouveau_fence_wait(fence, NULL, false, false);
	265	nouveau_fence_unref((void *)&fence);
	266	}
	267
	268	if (ret)
	269	NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
	270	}
	271
	272	/* Ensure all outstanding fences are signaled. They should be if the
	273	* above attempts at idling were OK, but if we failed this'll tell TTM
	274	* we're done with the buffers.
	275	*/
	276	nouveau_fence_fini(chan);
	277
	278	/* Ensure the channel is no longer active on the GPU */
	279	pfifo->reassign(dev, false);
	280
a51a3bf5 MM	281	pgraph->fifo_access(dev, false);
a51a3bf5 MM	282	if (pgraph->channel(dev) == chan)
6ee73861	283	pgraph->unload_context(dev);
6ee73861	284	pgraph->destroy_context(chan);
a51a3bf5	285	pgraph->fifo_access(dev, true);
6ee73861 BS	286
	287	if (pfifo->channel_id(dev) == chan->id) {
	288	pfifo->disable(dev);
	289	pfifo->unload_context(dev);
	290	pfifo->enable(dev);
	291	}
	292	pfifo->destroy_context(chan);
	293
	294	pfifo->reassign(dev, true);
	295
	296	/* Release the channel's resources */
	297	nouveau_gpuobj_ref_del(dev, &chan->pushbuf);
	298	if (chan->pushbuf_bo) {
	299	nouveau_bo_unpin(chan->pushbuf_bo);
	300	nouveau_bo_ref(NULL, &chan->pushbuf_bo);
	301	}
	302	nouveau_gpuobj_channel_takedown(chan);
	303	nouveau_notifier_takedown_channel(chan);
	304	if (chan->user)
	305	iounmap(chan->user);
	306
	307	dev_priv->fifos[chan->id] = NULL;
	308	dev_priv->fifo_alloc_count--;
	309	kfree(chan);
	310	}
	311
	312	/* cleans up all the fifos from file_priv */
	313	void
	314	nouveau_channel_cleanup(struct drm_device dev, struct drm_file file_priv)
	315	{
	316	struct drm_nouveau_private *dev_priv = dev->dev_private;
	317	struct nouveau_engine *engine = &dev_priv->engine;
	318	int i;
	319
	320	NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
	321	for (i = 0; i < engine->fifo.channels; i++) {
	322	struct nouveau_channel *chan = dev_priv->fifos[i];
	323
	324	if (chan && chan->file_priv == file_priv)
	325	nouveau_channel_free(chan);
	326	}
	327	}
	328
	329	int
	330	nouveau_channel_owner(struct drm_device dev, struct drm_file file_priv,
	331	int channel)
	332	{
	333	struct drm_nouveau_private *dev_priv = dev->dev_private;
	334	struct nouveau_engine *engine = &dev_priv->engine;
	335
	336	if (channel >= engine->fifo.channels)
	337	return 0;
	338	if (dev_priv->fifos[channel] == NULL)
	339	return 0;
	340
	341	return (dev_priv->fifos[channel]->file_priv == file_priv);
	342	}
	343
	344	/***********************************
	345	* ioctls wrapping the functions
	346	***********************************/
	347
	348	static int
	349	nouveau_ioctl_fifo_alloc(struct drm_device dev, void data,
350	struct drm_file *file_priv)
351	{
352	struct drm_nouveau_private *dev_priv = dev->dev_private;
353	struct drm_nouveau_channel_alloc *init = data;
354	struct nouveau_channel *chan;
355	int ret;
356
357	NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
358
359	if (dev_priv->engine.graph.accel_blocked)
360	return -ENODEV;
361
362	if (init->fb_ctxdma_handle == ~0 \|\| init->tt_ctxdma_handle == ~0)
363	return -EINVAL;
364
365	ret = nouveau_channel_alloc(dev, &chan, file_priv,
366	init->fb_ctxdma_handle,
367	init->tt_ctxdma_handle);
368	if (ret)
369	return ret;
370	init->channel = chan->id;
371
372	init->subchan[0].handle = NvM2MF;
373	if (dev_priv->card_type < NV_50)
374	init->subchan[0].grclass = 0x0039;
375	else
376	init->subchan[0].grclass = 0x5039;
f03a314b FJ	377	init->subchan[1].handle = NvSw;
	378	init->subchan[1].grclass = NV_SW;
	379	init->nr_subchan = 2;
6ee73861 BS	380
	381	/* Named memory object area */
	382	ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
	383	&init->notifier_handle);
	384	if (ret) {
	385	nouveau_channel_free(chan);
	386	return ret;
	387	}
	388
	389	return 0;
	390	}
	391
	392	static int
	393	nouveau_ioctl_fifo_free(struct drm_device dev, void data,
	394	struct drm_file *file_priv)
	395	{
	396	struct drm_nouveau_channel_free *cfree = data;
	397	struct nouveau_channel *chan;
	398
	399	NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
	400	NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);
	401
	402	nouveau_channel_free(chan);
	403	return 0;
	404	}
	405
	406	/***********************************
	407	* finally, the ioctl table
	408	***********************************/
	409
	410	struct drm_ioctl_desc nouveau_ioctls[] = {
	411	DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH),
	412	DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
	413	DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	414	DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
	415	DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
	416	DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
	417	DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
	418	DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
	419	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
	420	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
	421	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL, nouveau_gem_ioctl_pushbuf_call, DRM_AUTH),
	422	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PIN, nouveau_gem_ioctl_pin, DRM_AUTH),
	423	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_UNPIN, nouveau_gem_ioctl_unpin, DRM_AUTH),
	424	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
	425	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
	426	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
	427	DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL2, nouveau_gem_ioctl_pushbuf_call2, DRM_AUTH),
	428	};
	429
	430	int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);