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Merge branch 'merge' of git://git.secretlab.ca/git/linux-2.6
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
31
32#include "nouveau_drm.h"
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35
a510604d
MM		 36#include <linux/log2.h>
37
6ee73861
BS		 38static void
39nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
40{
41 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
a0af9add 42 struct drm_device *dev = dev_priv->dev;
6ee73861
BS		 43 struct nouveau_bo *nvbo = nouveau_bo(bo);
44
45 ttm_bo_kunmap(&nvbo->kmap);
46
47 if (unlikely(nvbo->gem))
48 DRM_ERROR("bo %p still attached to GEM object\n", bo);
49
a0af9add
FJ		 50 if (nvbo->tile)
51 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
52
6ee73861
BS		 53 spin_lock(&dev_priv->ttm.bo_list_lock);
54 list_del(&nvbo->head);
55 spin_unlock(&dev_priv->ttm.bo_list_lock);
56 kfree(nvbo);
57}
58
a0af9add
FJ		 59static void
60nouveau_bo_fixup_align(struct drm_device *dev,
61 uint32_t tile_mode, uint32_t tile_flags,
62 int *align, int *size)
63{
64 struct drm_nouveau_private *dev_priv = dev->dev_private;
65
66 /*
67 * Some of the tile_flags have a periodic structure of N*4096 bytes,
eb1dba0e
MM		 68 * align to to that as well as the page size. Align the size to the
69 * appropriate boundaries. This does imply that sizes are rounded up
70 * 3-7 pages, so be aware of this and do not waste memory by allocating
71 * many small buffers.
a0af9add
FJ		 72 */
73 if (dev_priv->card_type == NV_50) {
a510604d
MM		 74 uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15;
75 int i;
76
a0af9add
FJ		 77 switch (tile_flags) {
78 case 0x1800:
79 case 0x2800:
80 case 0x4800:
81 case 0x7a00:
a510604d 82 if (is_power_of_2(block_size)) {
a510604d
MM		 83 for (i = 1; i < 10; i++) {
84 *align = 12 * i * block_size;
85 if (!(*align % 65536))
86 break;
87 }
a0af9add 88 } else {
a510604d
MM		 89 for (i = 1; i < 10; i++) {
90 *align = 8 * i * block_size;
91 if (!(*align % 65536))
92 break;
93 }
a0af9add 94 }
eb1dba0e 95 *size = roundup(*size, *align);
a0af9add
FJ		 96 break;
97 default:
98 break;
99 }
100
101 } else {
102 if (tile_mode) {
103 if (dev_priv->chipset >= 0x40) {
104 *align = 65536;
105 *size = roundup(*size, 64 * tile_mode);
106
107 } else if (dev_priv->chipset >= 0x30) {
108 *align = 32768;
109 *size = roundup(*size, 64 * tile_mode);
110
111 } else if (dev_priv->chipset >= 0x20) {
112 *align = 16384;
113 *size = roundup(*size, 64 * tile_mode);
114
115 } else if (dev_priv->chipset >= 0x10) {
116 *align = 16384;
117 *size = roundup(*size, 32 * tile_mode);
118 }
119 }
120 }
121
1c7059e4
MM		 122 /* ALIGN works only on powers of two. */
123 *size = roundup(*size, PAGE_SIZE);
a0af9add
FJ		 124
125 if (dev_priv->card_type == NV_50) {
1c7059e4 126 *size = roundup(*size, 65536);
a0af9add
FJ		 127 *align = max(65536, *align);
128 }
129}
130
6ee73861
BS		 131int
132nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
133 int size, int align, uint32_t flags, uint32_t tile_mode,
134 uint32_t tile_flags, bool no_vm, bool mappable,
135 struct nouveau_bo **pnvbo)
136{
137 struct drm_nouveau_private *dev_priv = dev->dev_private;
138 struct nouveau_bo *nvbo;
8dea4a19 139 int ret = 0;
6ee73861
BS		 140
141 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
142 if (!nvbo)
143 return -ENOMEM;
144 INIT_LIST_HEAD(&nvbo->head);
145 INIT_LIST_HEAD(&nvbo->entry);
146 nvbo->mappable = mappable;
147 nvbo->no_vm = no_vm;
148 nvbo->tile_mode = tile_mode;
149 nvbo->tile_flags = tile_flags;
150
a0af9add 151 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
6ee73861
BS		 152 align >>= PAGE_SHIFT;
153
6ee73861
BS		 154 nvbo->placement.fpfn = 0;
155 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
8dea4a19 156 nouveau_bo_placement_set(nvbo, flags);
6ee73861
BS		 157
158 nvbo->channel = chan;
6ee73861
BS		 159 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
160 ttm_bo_type_device, &nvbo->placement, align, 0,
161 false, NULL, size, nouveau_bo_del_ttm);
162 nvbo->channel = NULL;
163 if (ret) {
164 /* ttm will call nouveau_bo_del_ttm if it fails.. */
165 return ret;
166 }
167
168 spin_lock(&dev_priv->ttm.bo_list_lock);
169 list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
170 spin_unlock(&dev_priv->ttm.bo_list_lock);
171 *pnvbo = nvbo;
172 return 0;
173}
174
175void
176nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype)
177{
178 int n = 0;
179
180 if (memtype & TTM_PL_FLAG_VRAM)
181 nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING;
182 if (memtype & TTM_PL_FLAG_TT)
183 nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
184 if (memtype & TTM_PL_FLAG_SYSTEM)
185 nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
186 nvbo->placement.placement = nvbo->placements;
187 nvbo->placement.busy_placement = nvbo->placements;
188 nvbo->placement.num_placement = n;
189 nvbo->placement.num_busy_placement = n;
37cb3e08
BS		 190
191 if (nvbo->pin_refcnt) {
192 while (n--)
193 nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT;
194 }
6ee73861
BS		 195}
196
197int
198nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
199{
200 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
201 struct ttm_buffer_object *bo = &nvbo->bo;
202 int ret, i;
203
204 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
205 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
206 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
207 1 << bo->mem.mem_type, memtype);
208 return -EINVAL;
209 }
210
211 if (nvbo->pin_refcnt++)
212 return 0;
213
214 ret = ttm_bo_reserve(bo, false, false, false, 0);
215 if (ret)
216 goto out;
217
218 nouveau_bo_placement_set(nvbo, memtype);
219 for (i = 0; i < nvbo->placement.num_placement; i++)
220 nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
221
222 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
223 if (ret == 0) {
224 switch (bo->mem.mem_type) {
225 case TTM_PL_VRAM:
226 dev_priv->fb_aper_free -= bo->mem.size;
227 break;
228 case TTM_PL_TT:
229 dev_priv->gart_info.aper_free -= bo->mem.size;
230 break;
231 default:
232 break;
233 }
234 }
235 ttm_bo_unreserve(bo);
236out:
237 if (unlikely(ret))
238 nvbo->pin_refcnt--;
239 return ret;
240}
241
242int
243nouveau_bo_unpin(struct nouveau_bo *nvbo)
244{
245 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
246 struct ttm_buffer_object *bo = &nvbo->bo;
247 int ret, i;
248
249 if (--nvbo->pin_refcnt)
250 return 0;
251
252 ret = ttm_bo_reserve(bo, false, false, false, 0);
253 if (ret)
254 return ret;
255
256 for (i = 0; i < nvbo->placement.num_placement; i++)
257 nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
258
259 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
260 if (ret == 0) {
261 switch (bo->mem.mem_type) {
262 case TTM_PL_VRAM:
263 dev_priv->fb_aper_free += bo->mem.size;
264 break;
265 case TTM_PL_TT:
266 dev_priv->gart_info.aper_free += bo->mem.size;
267 break;
268 default:
269 break;
270 }
271 }
272
273 ttm_bo_unreserve(bo);
274 return ret;
275}
276
277int
278nouveau_bo_map(struct nouveau_bo *nvbo)
279{
280 int ret;
281
282 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
283 if (ret)
284 return ret;
285
286 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
287 ttm_bo_unreserve(&nvbo->bo);
288 return ret;
289}
290
291void
292nouveau_bo_unmap(struct nouveau_bo *nvbo)
293{
294 ttm_bo_kunmap(&nvbo->kmap);
295}
296
297u16
298nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
299{
300 bool is_iomem;
301 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
302 mem = &mem[index];
303 if (is_iomem)
304 return ioread16_native((void __force __iomem *)mem);
305 else
306 return *mem;
307}
308
309void
310nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
311{
312 bool is_iomem;
313 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
314 mem = &mem[index];
315 if (is_iomem)
316 iowrite16_native(val, (void __force __iomem *)mem);
317 else
318 *mem = val;
319}
320
321u32
322nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
323{
324 bool is_iomem;
325 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
326 mem = &mem[index];
327 if (is_iomem)
328 return ioread32_native((void __force __iomem *)mem);
329 else
330 return *mem;
331}
332
333void
334nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
335{
336 bool is_iomem;
337 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
338 mem = &mem[index];
339 if (is_iomem)
340 iowrite32_native(val, (void __force __iomem *)mem);
341 else
342 *mem = val;
343}
344
345static struct ttm_backend *
346nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
347{
348 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
349 struct drm_device *dev = dev_priv->dev;
350
351 switch (dev_priv->gart_info.type) {
b694dfb2 352#if __OS_HAS_AGP
6ee73861
BS		 353 case NOUVEAU_GART_AGP:
354 return ttm_agp_backend_init(bdev, dev->agp->bridge);
b694dfb2 355#endif
6ee73861
BS		 356 case NOUVEAU_GART_SGDMA:
357 return nouveau_sgdma_init_ttm(dev);
358 default:
359 NV_ERROR(dev, "Unknown GART type %d\n",
360 dev_priv->gart_info.type);
361 break;
362 }
363
364 return NULL;
365}
366
367static int
368nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
369{
370 /* We'll do this from user space. */
371 return 0;
372}
373
374static int
375nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
376 struct ttm_mem_type_manager *man)
377{
378 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
379 struct drm_device *dev = dev_priv->dev;
380
381 switch (type) {
382 case TTM_PL_SYSTEM:
383 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
384 man->available_caching = TTM_PL_MASK_CACHING;
385 man->default_caching = TTM_PL_FLAG_CACHED;
386 break;
387 case TTM_PL_VRAM:
388 man->flags = TTM_MEMTYPE_FLAG_FIXED |
389 TTM_MEMTYPE_FLAG_MAPPABLE |
390 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP;
391 man->available_caching = TTM_PL_FLAG_UNCACHED |
392 TTM_PL_FLAG_WC;
393 man->default_caching = TTM_PL_FLAG_WC;
394
395 man->io_addr = NULL;
396 man->io_offset = drm_get_resource_start(dev, 1);
397 man->io_size = drm_get_resource_len(dev, 1);
398 if (man->io_size > nouveau_mem_fb_amount(dev))
399 man->io_size = nouveau_mem_fb_amount(dev);
400
401 man->gpu_offset = dev_priv->vm_vram_base;
402 break;
403 case TTM_PL_TT:
404 switch (dev_priv->gart_info.type) {
405 case NOUVEAU_GART_AGP:
406 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
407 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP;
408 man->available_caching = TTM_PL_FLAG_UNCACHED;
409 man->default_caching = TTM_PL_FLAG_UNCACHED;
410 break;
411 case NOUVEAU_GART_SGDMA:
412 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
413 TTM_MEMTYPE_FLAG_CMA;
414 man->available_caching = TTM_PL_MASK_CACHING;
415 man->default_caching = TTM_PL_FLAG_CACHED;
416 break;
417 default:
418 NV_ERROR(dev, "Unknown GART type: %d\n",
419 dev_priv->gart_info.type);
420 return -EINVAL;
421 }
422
423 man->io_offset = dev_priv->gart_info.aper_base;
424 man->io_size = dev_priv->gart_info.aper_size;
425 man->io_addr = NULL;
426 man->gpu_offset = dev_priv->vm_gart_base;
427 break;
428 default:
429 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
430 return -EINVAL;
431 }
432 return 0;
433}
434
435static void
436nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
437{
438 struct nouveau_bo *nvbo = nouveau_bo(bo);
439
440 switch (bo->mem.mem_type) {
22fbd538 441 case TTM_PL_VRAM:
965cf68e 442 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT);
22fbd538 443 break;
6ee73861
BS		 444 default:
445 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM);
446 break;
447 }
22fbd538
FJ		 448
449 *pl = nvbo->placement;
6ee73861
BS		 450}
451
452
453/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
454 * TTM_PL_{VRAM,TT} directly.
455 */
a0af9add 456
6ee73861
BS		 457static int
458nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
459 struct nouveau_bo *nvbo, bool evict, bool no_wait,
460 struct ttm_mem_reg *new_mem)
461{
462 struct nouveau_fence *fence = NULL;
463 int ret;
464
465 ret = nouveau_fence_new(chan, &fence, true);
466 if (ret)
467 return ret;
468
469 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
470 evict, no_wait, new_mem);
e147eae8
BS		 471 if (nvbo->channel && nvbo->channel != chan)
472 ret = nouveau_fence_wait(fence, NULL, false, false);
6ee73861
BS		 473 nouveau_fence_unref((void *)&fence);
474 return ret;
475}
476
477static inline uint32_t
478nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
479 struct ttm_mem_reg *mem)
480{
481 if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) {
482 if (mem->mem_type == TTM_PL_TT)
483 return NvDmaGART;
484 return NvDmaVRAM;
485 }
486
487 if (mem->mem_type == TTM_PL_TT)
488 return chan->gart_handle;
489 return chan->vram_handle;
490}
491
492static int
a0af9add
FJ		 493nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
494 int no_wait, struct ttm_mem_reg *new_mem)
6ee73861
BS		 495{
496 struct nouveau_bo *nvbo = nouveau_bo(bo);
497 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
a0af9add 498 struct ttm_mem_reg *old_mem = &bo->mem;
6ee73861
BS		 499 struct nouveau_channel *chan;
500 uint64_t src_offset, dst_offset;
501 uint32_t page_count;
502 int ret;
503
504 chan = nvbo->channel;
0735f62e 505 if (!chan || nvbo->tile_flags || nvbo->no_vm)
6ee73861 506 chan = dev_priv->channel;
6ee73861
BS		 507
508 src_offset = old_mem->mm_node->start << PAGE_SHIFT;
509 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
510 if (chan != dev_priv->channel) {
511 if (old_mem->mem_type == TTM_PL_TT)
512 src_offset += dev_priv->vm_gart_base;
513 else
514 src_offset += dev_priv->vm_vram_base;
515
516 if (new_mem->mem_type == TTM_PL_TT)
517 dst_offset += dev_priv->vm_gart_base;
518 else
519 dst_offset += dev_priv->vm_vram_base;
520 }
521
522 ret = RING_SPACE(chan, 3);
523 if (ret)
524 return ret;
525 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
526 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem));
527 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem));
528
529 if (dev_priv->card_type >= NV_50) {
530 ret = RING_SPACE(chan, 4);
531 if (ret)
532 return ret;
533 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
534 OUT_RING(chan, 1);
535 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
536 OUT_RING(chan, 1);
537 }
538
539 page_count = new_mem->num_pages;
540 while (page_count) {
541 int line_count = (page_count > 2047) ? 2047 : page_count;
542
543 if (dev_priv->card_type >= NV_50) {
544 ret = RING_SPACE(chan, 3);
545 if (ret)
546 return ret;
547 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
548 OUT_RING(chan, upper_32_bits(src_offset));
549 OUT_RING(chan, upper_32_bits(dst_offset));
550 }
551 ret = RING_SPACE(chan, 11);
552 if (ret)
553 return ret;
554 BEGIN_RING(chan, NvSubM2MF,
555 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
556 OUT_RING(chan, lower_32_bits(src_offset));
557 OUT_RING(chan, lower_32_bits(dst_offset));
558 OUT_RING(chan, PAGE_SIZE); /* src_pitch */
559 OUT_RING(chan, PAGE_SIZE); /* dst_pitch */
560 OUT_RING(chan, PAGE_SIZE); /* line_length */
561 OUT_RING(chan, line_count);
562 OUT_RING(chan, (1<<8)|(1<<0));
563 OUT_RING(chan, 0);
564 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
565 OUT_RING(chan, 0);
566
567 page_count -= line_count;
568 src_offset += (PAGE_SIZE * line_count);
569 dst_offset += (PAGE_SIZE * line_count);
570 }
571
572 return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait, new_mem);
573}
574
575static int
576nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
577 bool no_wait, struct ttm_mem_reg *new_mem)
578{
579 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
580 struct ttm_placement placement;
581 struct ttm_mem_reg tmp_mem;
582 int ret;
583
584 placement.fpfn = placement.lpfn = 0;
585 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 586 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS		 587
588 tmp_mem = *new_mem;
589 tmp_mem.mm_node = NULL;
590 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait);
591 if (ret)
592 return ret;
593
594 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
595 if (ret)
596 goto out;
597
a0af9add 598 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem);
6ee73861
BS		 599 if (ret)
600 goto out;
601
602 ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem);
603out:
604 if (tmp_mem.mm_node) {
605 spin_lock(&bo->bdev->glob->lru_lock);
606 drm_mm_put_block(tmp_mem.mm_node);
607 spin_unlock(&bo->bdev->glob->lru_lock);
608 }
609
610 return ret;
611}
612
613static int
614nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
615 bool no_wait, struct ttm_mem_reg *new_mem)
616{
617 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
618 struct ttm_placement placement;
619 struct ttm_mem_reg tmp_mem;
620 int ret;
621
622 placement.fpfn = placement.lpfn = 0;
623 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 624 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS		 625
626 tmp_mem = *new_mem;
627 tmp_mem.mm_node = NULL;
628 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait);
629 if (ret)
630 return ret;
631
632 ret = ttm_bo_move_ttm(bo, evict, no_wait, &tmp_mem);
633 if (ret)
634 goto out;
635
27f691a6 636 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
6ee73861
BS		 637 if (ret)
638 goto out;
639
640out:
641 if (tmp_mem.mm_node) {
642 spin_lock(&bo->bdev->glob->lru_lock);
643 drm_mm_put_block(tmp_mem.mm_node);
644 spin_unlock(&bo->bdev->glob->lru_lock);
645 }
646
647 return ret;
648}
649
650static int
a0af9add
FJ		 651nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
652 struct nouveau_tile_reg **new_tile)
6ee73861
BS		 653{
654 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
6ee73861 655 struct drm_device *dev = dev_priv->dev;
a0af9add
FJ		 656 struct nouveau_bo *nvbo = nouveau_bo(bo);
657 uint64_t offset;
6ee73861
BS		 658 int ret;
659
a0af9add
FJ		 660 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
661 /* Nothing to do. */
662 *new_tile = NULL;
663 return 0;
664 }
665
666 offset = new_mem->mm_node->start << PAGE_SHIFT;
6ee73861 667
a0af9add 668 if (dev_priv->card_type == NV_50) {
6ee73861
BS		 669 ret = nv50_mem_vm_bind_linear(dev,
670 offset + dev_priv->vm_vram_base,
671 new_mem->size, nvbo->tile_flags,
672 offset);
673 if (ret)
674 return ret;
a0af9add
FJ		 675
676 } else if (dev_priv->card_type >= NV_10) {
677 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
678 nvbo->tile_mode);
6ee73861
BS		 679 }
680
a0af9add
FJ		 681 return 0;
682}
683
684static void
685nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
686 struct nouveau_tile_reg *new_tile,
687 struct nouveau_tile_reg **old_tile)
688{
689 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
690 struct drm_device *dev = dev_priv->dev;
691
692 if (dev_priv->card_type >= NV_10 &&
693 dev_priv->card_type < NV_50) {
694 if (*old_tile)
695 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
696
697 *old_tile = new_tile;
698 }
699}
700
701static int
702nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
703 bool no_wait, struct ttm_mem_reg *new_mem)
704{
705 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
706 struct nouveau_bo *nvbo = nouveau_bo(bo);
707 struct ttm_mem_reg *old_mem = &bo->mem;
708 struct nouveau_tile_reg *new_tile = NULL;
709 int ret = 0;
710
711 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
712 if (ret)
713 return ret;
714
715 /* Software copy if the card isn't up and running yet. */
0735f62e 716 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
a0af9add
FJ		 717 !dev_priv->channel) {
718 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
719 goto out;
720 }
6ee73861 721
a0af9add 722 /* Fake bo copy. */
6ee73861
BS		 723 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
724 BUG_ON(bo->mem.mm_node != NULL);
725 bo->mem = *new_mem;
726 new_mem->mm_node = NULL;
a0af9add 727 goto out;
6ee73861
BS		 728 }
729
a0af9add
FJ		 730 /* Hardware assisted copy. */
731 if (new_mem->mem_type == TTM_PL_SYSTEM)
732 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem);
733 else if (old_mem->mem_type == TTM_PL_SYSTEM)
734 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem);
735 else
736 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
6ee73861 737
a0af9add
FJ		 738 if (!ret)
739 goto out;
740
741 /* Fallback to software copy. */
742 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
743
744out:
745 if (ret)
746 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
747 else
748 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
749
750 return ret;
6ee73861
BS		 751}
752
753static int
754nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
755{
756 return 0;
757}
758
759struct ttm_bo_driver nouveau_bo_driver = {
760 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
761 .invalidate_caches = nouveau_bo_invalidate_caches,
762 .init_mem_type = nouveau_bo_init_mem_type,
763 .evict_flags = nouveau_bo_evict_flags,
764 .move = nouveau_bo_move,
765 .verify_access = nouveau_bo_verify_access,
766 .sync_obj_signaled = nouveau_fence_signalled,
767 .sync_obj_wait = nouveau_fence_wait,
768 .sync_obj_flush = nouveau_fence_flush,
769 .sync_obj_unref = nouveau_fence_unref,
770 .sync_obj_ref = nouveau_fence_ref,
771};
772
Linux 6.x block layer and io_uring tree(s)