drm/nouveau/ttm: untangle code to support accelerated buffer moves
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
CommitLineData
6ee73861
BS
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
b1e5f172 31#include "ttm/ttm_page_alloc.h"
6ee73861
BS
32
33#include "nouveau_drm.h"
34#include "nouveau_drv.h"
35#include "nouveau_dma.h"
f869ef88
BS
36#include "nouveau_mm.h"
37#include "nouveau_vm.h"
d375e7d5 38#include "nouveau_fence.h"
d1b167e1 39#include "nouveau_ramht.h"
6ee73861 40
a510604d 41#include <linux/log2.h>
5a0e3ad6 42#include <linux/slab.h>
a510604d 43
6ee73861
BS
44static void
45nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
46{
47 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
a0af9add 48 struct drm_device *dev = dev_priv->dev;
6ee73861
BS
49 struct nouveau_bo *nvbo = nouveau_bo(bo);
50
6ee73861
BS
51 if (unlikely(nvbo->gem))
52 DRM_ERROR("bo %p still attached to GEM object\n", bo);
53
a5cf68b0 54 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
6ee73861
BS
55 kfree(nvbo);
56}
57
a0af9add 58static void
db5c8e29 59nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
f91bac5b 60 int *align, int *size)
a0af9add 61{
bfd83aca 62 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
a0af9add 63
573a2a37 64 if (dev_priv->card_type < NV_50) {
bfd83aca 65 if (nvbo->tile_mode) {
a0af9add
FJ
66 if (dev_priv->chipset >= 0x40) {
67 *align = 65536;
bfd83aca 68 *size = roundup(*size, 64 * nvbo->tile_mode);
a0af9add
FJ
69
70 } else if (dev_priv->chipset >= 0x30) {
71 *align = 32768;
bfd83aca 72 *size = roundup(*size, 64 * nvbo->tile_mode);
a0af9add
FJ
73
74 } else if (dev_priv->chipset >= 0x20) {
75 *align = 16384;
bfd83aca 76 *size = roundup(*size, 64 * nvbo->tile_mode);
a0af9add
FJ
77
78 } else if (dev_priv->chipset >= 0x10) {
79 *align = 16384;
bfd83aca 80 *size = roundup(*size, 32 * nvbo->tile_mode);
a0af9add
FJ
81 }
82 }
bfd83aca 83 } else {
f91bac5b
BS
84 *size = roundup(*size, (1 << nvbo->page_shift));
85 *align = max((1 << nvbo->page_shift), *align);
a0af9add
FJ
86 }
87
1c7059e4 88 *size = roundup(*size, PAGE_SIZE);
a0af9add
FJ
89}
90
6ee73861 91int
7375c95b
BS
92nouveau_bo_new(struct drm_device *dev, int size, int align,
93 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
22b33e8e 94 struct sg_table *sg,
7375c95b 95 struct nouveau_bo **pnvbo)
6ee73861
BS
96{
97 struct drm_nouveau_private *dev_priv = dev->dev_private;
98 struct nouveau_bo *nvbo;
57de4ba9 99 size_t acc_size;
f91bac5b 100 int ret;
22b33e8e
DA
101 int type = ttm_bo_type_device;
102
103 if (sg)
104 type = ttm_bo_type_sg;
6ee73861
BS
105
106 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
107 if (!nvbo)
108 return -ENOMEM;
109 INIT_LIST_HEAD(&nvbo->head);
110 INIT_LIST_HEAD(&nvbo->entry);
fd2871af 111 INIT_LIST_HEAD(&nvbo->vma_list);
6ee73861
BS
112 nvbo->tile_mode = tile_mode;
113 nvbo->tile_flags = tile_flags;
699ddfd9 114 nvbo->bo.bdev = &dev_priv->ttm.bdev;
6ee73861 115
f91bac5b
BS
116 nvbo->page_shift = 12;
117 if (dev_priv->bar1_vm) {
118 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
119 nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
120 }
121
122 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
fd2871af
BS
123 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
124 nouveau_bo_placement_set(nvbo, flags, 0);
6ee73861 125
57de4ba9
JG
126 acc_size = ttm_bo_dma_acc_size(&dev_priv->ttm.bdev, size,
127 sizeof(struct nouveau_bo));
128
6ee73861 129 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
22b33e8e
DA
130 type, &nvbo->placement,
131 align >> PAGE_SHIFT, 0, false, NULL, acc_size, sg,
fd2871af 132 nouveau_bo_del_ttm);
6ee73861
BS
133 if (ret) {
134 /* ttm will call nouveau_bo_del_ttm if it fails.. */
135 return ret;
136 }
137
6ee73861
BS
138 *pnvbo = nvbo;
139 return 0;
140}
141
78ad0f7b
FJ
142static void
143set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
144{
145 *n = 0;
146
147 if (type & TTM_PL_FLAG_VRAM)
148 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
149 if (type & TTM_PL_FLAG_TT)
150 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
151 if (type & TTM_PL_FLAG_SYSTEM)
152 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
153}
154
699ddfd9
FJ
155static void
156set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
157{
158 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
812f219a 159 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
699ddfd9
FJ
160
161 if (dev_priv->card_type == NV_10 &&
812f219a 162 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
4beb116a 163 nvbo->bo.mem.num_pages < vram_pages / 4) {
699ddfd9
FJ
164 /*
165 * Make sure that the color and depth buffers are handled
166 * by independent memory controller units. Up to a 9x
167 * speed up when alpha-blending and depth-test are enabled
168 * at the same time.
169 */
699ddfd9
FJ
170 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
171 nvbo->placement.fpfn = vram_pages / 2;
172 nvbo->placement.lpfn = ~0;
173 } else {
174 nvbo->placement.fpfn = 0;
175 nvbo->placement.lpfn = vram_pages / 2;
176 }
177 }
178}
179
6ee73861 180void
78ad0f7b 181nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
6ee73861 182{
78ad0f7b
FJ
183 struct ttm_placement *pl = &nvbo->placement;
184 uint32_t flags = TTM_PL_MASK_CACHING |
185 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
186
187 pl->placement = nvbo->placements;
188 set_placement_list(nvbo->placements, &pl->num_placement,
189 type, flags);
190
191 pl->busy_placement = nvbo->busy_placements;
192 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
193 type | busy, flags);
699ddfd9
FJ
194
195 set_placement_range(nvbo, type);
6ee73861
BS
196}
197
198int
199nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
200{
201 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
202 struct ttm_buffer_object *bo = &nvbo->bo;
78ad0f7b 203 int ret;
6ee73861
BS
204
205 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
206 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
207 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
208 1 << bo->mem.mem_type, memtype);
209 return -EINVAL;
210 }
211
212 if (nvbo->pin_refcnt++)
213 return 0;
214
215 ret = ttm_bo_reserve(bo, false, false, false, 0);
216 if (ret)
217 goto out;
218
78ad0f7b 219 nouveau_bo_placement_set(nvbo, memtype, 0);
6ee73861 220
7a45d764 221 ret = nouveau_bo_validate(nvbo, false, false, false);
6ee73861
BS
222 if (ret == 0) {
223 switch (bo->mem.mem_type) {
224 case TTM_PL_VRAM:
225 dev_priv->fb_aper_free -= bo->mem.size;
226 break;
227 case TTM_PL_TT:
228 dev_priv->gart_info.aper_free -= bo->mem.size;
229 break;
230 default:
231 break;
232 }
233 }
234 ttm_bo_unreserve(bo);
235out:
236 if (unlikely(ret))
237 nvbo->pin_refcnt--;
238 return ret;
239}
240
241int
242nouveau_bo_unpin(struct nouveau_bo *nvbo)
243{
244 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
245 struct ttm_buffer_object *bo = &nvbo->bo;
78ad0f7b 246 int ret;
6ee73861
BS
247
248 if (--nvbo->pin_refcnt)
249 return 0;
250
251 ret = ttm_bo_reserve(bo, false, false, false, 0);
252 if (ret)
253 return ret;
254
78ad0f7b 255 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
6ee73861 256
7a45d764 257 ret = nouveau_bo_validate(nvbo, false, false, false);
6ee73861
BS
258 if (ret == 0) {
259 switch (bo->mem.mem_type) {
260 case TTM_PL_VRAM:
261 dev_priv->fb_aper_free += bo->mem.size;
262 break;
263 case TTM_PL_TT:
264 dev_priv->gart_info.aper_free += bo->mem.size;
265 break;
266 default:
267 break;
268 }
269 }
270
271 ttm_bo_unreserve(bo);
272 return ret;
273}
274
275int
276nouveau_bo_map(struct nouveau_bo *nvbo)
277{
278 int ret;
279
280 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
281 if (ret)
282 return ret;
283
284 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
285 ttm_bo_unreserve(&nvbo->bo);
286 return ret;
287}
288
289void
290nouveau_bo_unmap(struct nouveau_bo *nvbo)
291{
9d59e8a1
BS
292 if (nvbo)
293 ttm_bo_kunmap(&nvbo->kmap);
6ee73861
BS
294}
295
7a45d764
BS
296int
297nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
298 bool no_wait_reserve, bool no_wait_gpu)
299{
300 int ret;
301
302 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
303 no_wait_reserve, no_wait_gpu);
304 if (ret)
305 return ret;
306
307 return 0;
308}
309
6ee73861
BS
310u16
311nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
312{
313 bool is_iomem;
314 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
315 mem = &mem[index];
316 if (is_iomem)
317 return ioread16_native((void __force __iomem *)mem);
318 else
319 return *mem;
320}
321
322void
323nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
324{
325 bool is_iomem;
326 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
327 mem = &mem[index];
328 if (is_iomem)
329 iowrite16_native(val, (void __force __iomem *)mem);
330 else
331 *mem = val;
332}
333
334u32
335nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
336{
337 bool is_iomem;
338 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
339 mem = &mem[index];
340 if (is_iomem)
341 return ioread32_native((void __force __iomem *)mem);
342 else
343 return *mem;
344}
345
346void
347nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
348{
349 bool is_iomem;
350 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
351 mem = &mem[index];
352 if (is_iomem)
353 iowrite32_native(val, (void __force __iomem *)mem);
354 else
355 *mem = val;
356}
357
649bf3ca
JG
358static struct ttm_tt *
359nouveau_ttm_tt_create(struct ttm_bo_device *bdev,
360 unsigned long size, uint32_t page_flags,
361 struct page *dummy_read_page)
6ee73861
BS
362{
363 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
364 struct drm_device *dev = dev_priv->dev;
365
366 switch (dev_priv->gart_info.type) {
b694dfb2 367#if __OS_HAS_AGP
6ee73861 368 case NOUVEAU_GART_AGP:
649bf3ca
JG
369 return ttm_agp_tt_create(bdev, dev->agp->bridge,
370 size, page_flags, dummy_read_page);
b694dfb2 371#endif
58e6c7a9
BS
372 case NOUVEAU_GART_PDMA:
373 case NOUVEAU_GART_HW:
649bf3ca
JG
374 return nouveau_sgdma_create_ttm(bdev, size, page_flags,
375 dummy_read_page);
6ee73861
BS
376 default:
377 NV_ERROR(dev, "Unknown GART type %d\n",
378 dev_priv->gart_info.type);
379 break;
380 }
381
382 return NULL;
383}
384
385static int
386nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
387{
388 /* We'll do this from user space. */
389 return 0;
390}
391
392static int
393nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
394 struct ttm_mem_type_manager *man)
395{
396 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
397 struct drm_device *dev = dev_priv->dev;
398
399 switch (type) {
400 case TTM_PL_SYSTEM:
401 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
402 man->available_caching = TTM_PL_MASK_CACHING;
403 man->default_caching = TTM_PL_FLAG_CACHED;
404 break;
405 case TTM_PL_VRAM:
8984e046 406 if (dev_priv->card_type >= NV_50) {
573a2a37 407 man->func = &nouveau_vram_manager;
f869ef88
BS
408 man->io_reserve_fastpath = false;
409 man->use_io_reserve_lru = true;
410 } else {
573a2a37 411 man->func = &ttm_bo_manager_func;
f869ef88 412 }
6ee73861 413 man->flags = TTM_MEMTYPE_FLAG_FIXED |
f32f02fd 414 TTM_MEMTYPE_FLAG_MAPPABLE;
6ee73861
BS
415 man->available_caching = TTM_PL_FLAG_UNCACHED |
416 TTM_PL_FLAG_WC;
417 man->default_caching = TTM_PL_FLAG_WC;
6ee73861
BS
418 break;
419 case TTM_PL_TT:
26c0c9e3
BS
420 if (dev_priv->card_type >= NV_50)
421 man->func = &nouveau_gart_manager;
422 else
423 man->func = &ttm_bo_manager_func;
6ee73861
BS
424 switch (dev_priv->gart_info.type) {
425 case NOUVEAU_GART_AGP:
f32f02fd 426 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
a3d487ea
FJ
427 man->available_caching = TTM_PL_FLAG_UNCACHED |
428 TTM_PL_FLAG_WC;
429 man->default_caching = TTM_PL_FLAG_WC;
6ee73861 430 break;
58e6c7a9
BS
431 case NOUVEAU_GART_PDMA:
432 case NOUVEAU_GART_HW:
6ee73861
BS
433 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
434 TTM_MEMTYPE_FLAG_CMA;
435 man->available_caching = TTM_PL_MASK_CACHING;
436 man->default_caching = TTM_PL_FLAG_CACHED;
437 break;
438 default:
439 NV_ERROR(dev, "Unknown GART type: %d\n",
440 dev_priv->gart_info.type);
441 return -EINVAL;
442 }
6ee73861
BS
443 break;
444 default:
445 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
446 return -EINVAL;
447 }
448 return 0;
449}
450
451static void
452nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
453{
454 struct nouveau_bo *nvbo = nouveau_bo(bo);
455
456 switch (bo->mem.mem_type) {
22fbd538 457 case TTM_PL_VRAM:
78ad0f7b
FJ
458 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
459 TTM_PL_FLAG_SYSTEM);
22fbd538 460 break;
6ee73861 461 default:
78ad0f7b 462 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
6ee73861
BS
463 break;
464 }
22fbd538
FJ
465
466 *pl = nvbo->placement;
6ee73861
BS
467}
468
469
470/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
471 * TTM_PL_{VRAM,TT} directly.
472 */
a0af9add 473
6ee73861
BS
474static int
475nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
9d87fa21
JG
476 struct nouveau_bo *nvbo, bool evict,
477 bool no_wait_reserve, bool no_wait_gpu,
6ee73861
BS
478 struct ttm_mem_reg *new_mem)
479{
480 struct nouveau_fence *fence = NULL;
481 int ret;
482
d375e7d5 483 ret = nouveau_fence_new(chan, &fence);
6ee73861
BS
484 if (ret)
485 return ret;
486
64798817 487 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
311ab694 488 no_wait_reserve, no_wait_gpu, new_mem);
382d62e5 489 nouveau_fence_unref(&fence);
6ee73861
BS
490 return ret;
491}
492
c6b7e895
BS
493static int
494nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
495 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
496{
497 struct nouveau_mem *node = old_mem->mm_node;
498 int ret = RING_SPACE(chan, 10);
499 if (ret == 0) {
6d597027 500 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
c6b7e895
BS
501 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
502 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
503 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
504 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
505 OUT_RING (chan, PAGE_SIZE);
506 OUT_RING (chan, PAGE_SIZE);
507 OUT_RING (chan, PAGE_SIZE);
508 OUT_RING (chan, new_mem->num_pages);
6d597027 509 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
c6b7e895
BS
510 }
511 return ret;
512}
513
d1b167e1
BS
514static int
515nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
516{
517 int ret = RING_SPACE(chan, 2);
518 if (ret == 0) {
519 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
520 OUT_RING (chan, handle);
521 }
522 return ret;
523}
524
183720b8
BS
525static int
526nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
527 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
528{
d2f96666
BS
529 struct nouveau_mem *node = old_mem->mm_node;
530 u64 src_offset = node->vma[0].offset;
531 u64 dst_offset = node->vma[1].offset;
183720b8
BS
532 u32 page_count = new_mem->num_pages;
533 int ret;
534
183720b8
BS
535 page_count = new_mem->num_pages;
536 while (page_count) {
537 int line_count = (page_count > 2047) ? 2047 : page_count;
538
539 ret = RING_SPACE(chan, 12);
540 if (ret)
541 return ret;
542
d1b167e1 543 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
183720b8
BS
544 OUT_RING (chan, upper_32_bits(dst_offset));
545 OUT_RING (chan, lower_32_bits(dst_offset));
d1b167e1 546 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
183720b8
BS
547 OUT_RING (chan, upper_32_bits(src_offset));
548 OUT_RING (chan, lower_32_bits(src_offset));
549 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
550 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
551 OUT_RING (chan, PAGE_SIZE); /* line_length */
552 OUT_RING (chan, line_count);
d1b167e1 553 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
183720b8
BS
554 OUT_RING (chan, 0x00100110);
555
556 page_count -= line_count;
557 src_offset += (PAGE_SIZE * line_count);
558 dst_offset += (PAGE_SIZE * line_count);
559 }
560
561 return 0;
562}
563
d1b167e1
BS
564static int
565nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
566{
567 int ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
568 &chan->m2mf_ntfy);
569 if (ret == 0) {
570 ret = RING_SPACE(chan, 6);
571 if (ret == 0) {
572 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
573 OUT_RING (chan, handle);
574 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
575 OUT_RING (chan, NvNotify0);
576 OUT_RING (chan, NvDmaFB);
577 OUT_RING (chan, NvDmaFB);
578 } else {
579 nouveau_ramht_remove(chan, NvNotify0);
580 }
581 }
582
583 return ret;
584}
585
6ee73861 586static int
f1ab0cc9
BS
587nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
588 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
6ee73861 589{
d2f96666 590 struct nouveau_mem *node = old_mem->mm_node;
f1ab0cc9
BS
591 struct nouveau_bo *nvbo = nouveau_bo(bo);
592 u64 length = (new_mem->num_pages << PAGE_SHIFT);
d2f96666
BS
593 u64 src_offset = node->vma[0].offset;
594 u64 dst_offset = node->vma[1].offset;
6ee73861
BS
595 int ret;
596
f1ab0cc9
BS
597 while (length) {
598 u32 amount, stride, height;
599
5220b3c1
BS
600 amount = min(length, (u64)(4 * 1024 * 1024));
601 stride = 16 * 4;
f1ab0cc9
BS
602 height = amount / stride;
603
f13b3263
FJ
604 if (new_mem->mem_type == TTM_PL_VRAM &&
605 nouveau_bo_tile_layout(nvbo)) {
f1ab0cc9
BS
606 ret = RING_SPACE(chan, 8);
607 if (ret)
608 return ret;
609
d1b167e1 610 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
f1ab0cc9 611 OUT_RING (chan, 0);
5220b3c1 612 OUT_RING (chan, 0);
f1ab0cc9
BS
613 OUT_RING (chan, stride);
614 OUT_RING (chan, height);
615 OUT_RING (chan, 1);
616 OUT_RING (chan, 0);
617 OUT_RING (chan, 0);
618 } else {
619 ret = RING_SPACE(chan, 2);
620 if (ret)
621 return ret;
622
d1b167e1 623 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
f1ab0cc9
BS
624 OUT_RING (chan, 1);
625 }
f13b3263
FJ
626 if (old_mem->mem_type == TTM_PL_VRAM &&
627 nouveau_bo_tile_layout(nvbo)) {
f1ab0cc9
BS
628 ret = RING_SPACE(chan, 8);
629 if (ret)
630 return ret;
631
d1b167e1 632 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
f1ab0cc9 633 OUT_RING (chan, 0);
5220b3c1 634 OUT_RING (chan, 0);
f1ab0cc9
BS
635 OUT_RING (chan, stride);
636 OUT_RING (chan, height);
637 OUT_RING (chan, 1);
638 OUT_RING (chan, 0);
639 OUT_RING (chan, 0);
640 } else {
641 ret = RING_SPACE(chan, 2);
642 if (ret)
643 return ret;
644
d1b167e1 645 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
f1ab0cc9
BS
646 OUT_RING (chan, 1);
647 }
648
649 ret = RING_SPACE(chan, 14);
6ee73861
BS
650 if (ret)
651 return ret;
f1ab0cc9 652
d1b167e1 653 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
f1ab0cc9
BS
654 OUT_RING (chan, upper_32_bits(src_offset));
655 OUT_RING (chan, upper_32_bits(dst_offset));
d1b167e1 656 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
f1ab0cc9
BS
657 OUT_RING (chan, lower_32_bits(src_offset));
658 OUT_RING (chan, lower_32_bits(dst_offset));
659 OUT_RING (chan, stride);
660 OUT_RING (chan, stride);
661 OUT_RING (chan, stride);
662 OUT_RING (chan, height);
663 OUT_RING (chan, 0x00000101);
664 OUT_RING (chan, 0x00000000);
d1b167e1 665 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
f1ab0cc9
BS
666 OUT_RING (chan, 0);
667
668 length -= amount;
669 src_offset += amount;
670 dst_offset += amount;
6ee73861
BS
671 }
672
f1ab0cc9
BS
673 return 0;
674}
675
d1b167e1
BS
676static int
677nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
678{
679 int ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
680 &chan->m2mf_ntfy);
681 if (ret == 0) {
682 ret = RING_SPACE(chan, 4);
683 if (ret == 0) {
684 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
685 OUT_RING (chan, handle);
686 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
687 OUT_RING (chan, NvNotify0);
688 }
689 }
690
691 return ret;
692}
693
a6704788
BS
694static inline uint32_t
695nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
696 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
697{
698 if (mem->mem_type == TTM_PL_TT)
699 return chan->gart_handle;
700 return chan->vram_handle;
701}
702
f1ab0cc9
BS
703static int
704nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
705 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
706{
d961db75
BS
707 u32 src_offset = old_mem->start << PAGE_SHIFT;
708 u32 dst_offset = new_mem->start << PAGE_SHIFT;
f1ab0cc9
BS
709 u32 page_count = new_mem->num_pages;
710 int ret;
711
712 ret = RING_SPACE(chan, 3);
713 if (ret)
714 return ret;
715
d1b167e1 716 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
f1ab0cc9
BS
717 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
718 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
719
6ee73861
BS
720 page_count = new_mem->num_pages;
721 while (page_count) {
722 int line_count = (page_count > 2047) ? 2047 : page_count;
723
6ee73861
BS
724 ret = RING_SPACE(chan, 11);
725 if (ret)
726 return ret;
f1ab0cc9 727
d1b167e1 728 BEGIN_NV04(chan, NvSubCopy,
6ee73861 729 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
f1ab0cc9
BS
730 OUT_RING (chan, src_offset);
731 OUT_RING (chan, dst_offset);
732 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
733 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
734 OUT_RING (chan, PAGE_SIZE); /* line_length */
735 OUT_RING (chan, line_count);
736 OUT_RING (chan, 0x00000101);
737 OUT_RING (chan, 0x00000000);
d1b167e1 738 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
f1ab0cc9 739 OUT_RING (chan, 0);
6ee73861
BS
740
741 page_count -= line_count;
742 src_offset += (PAGE_SIZE * line_count);
743 dst_offset += (PAGE_SIZE * line_count);
744 }
745
f1ab0cc9
BS
746 return 0;
747}
748
d2f96666
BS
749static int
750nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
751 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
752{
753 struct nouveau_mem *node = mem->mm_node;
754 int ret;
755
756 ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
757 node->page_shift, NV_MEM_ACCESS_RO, vma);
758 if (ret)
759 return ret;
760
761 if (mem->mem_type == TTM_PL_VRAM)
762 nouveau_vm_map(vma, node);
763 else
f7b24c42 764 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
d2f96666
BS
765
766 return 0;
767}
768
f1ab0cc9
BS
769static int
770nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
771 bool no_wait_reserve, bool no_wait_gpu,
772 struct ttm_mem_reg *new_mem)
773{
774 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
accf9496 775 struct nouveau_channel *chan = chan = dev_priv->channel;
f1ab0cc9 776 struct nouveau_bo *nvbo = nouveau_bo(bo);
3425df48 777 struct ttm_mem_reg *old_mem = &bo->mem;
f1ab0cc9
BS
778 int ret;
779
accf9496 780 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
f1ab0cc9 781
d2f96666
BS
782 /* create temporary vmas for the transfer and attach them to the
783 * old nouveau_mem node, these will get cleaned up after ttm has
784 * destroyed the ttm_mem_reg
3425df48 785 */
26c0c9e3 786 if (dev_priv->card_type >= NV_50) {
d5f42394 787 struct nouveau_mem *node = old_mem->mm_node;
3425df48 788
d2f96666
BS
789 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
790 if (ret)
791 goto out;
792
793 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
794 if (ret)
795 goto out;
3425df48
BS
796 }
797
d1b167e1 798 ret = dev_priv->ttm.move(chan, bo, &bo->mem, new_mem);
6a6b73f2
BS
799 if (ret == 0) {
800 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
801 no_wait_reserve,
802 no_wait_gpu, new_mem);
803 }
f1ab0cc9 804
3425df48 805out:
accf9496 806 mutex_unlock(&chan->mutex);
6a6b73f2 807 return ret;
6ee73861
BS
808}
809
d1b167e1
BS
810void
811nouveau_bo_move_init(struct nouveau_channel *chan)
812{
813 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
814 static const struct {
815 const char *name;
816 u32 oclass;
817 int (*exec)(struct nouveau_channel *,
818 struct ttm_buffer_object *,
819 struct ttm_mem_reg *, struct ttm_mem_reg *);
820 int (*init)(struct nouveau_channel *, u32 handle);
821 } _methods[] = {
822 { "COPY", 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
823 { "M2MF", 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
824 { "M2MF", 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
825 { "M2MF", 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
826 {}
827 }, *mthd = _methods;
828 const char *name = "CPU";
829 int ret;
830
831 do {
832 ret = nouveau_gpuobj_gr_new(chan, mthd->oclass, mthd->oclass);
833 if (ret == 0) {
834 ret = mthd->init(chan, mthd->oclass);
835 if (ret == 0) {
836 dev_priv->ttm.move = mthd->exec;
837 name = mthd->name;
838 break;
839 }
840 }
841 } while ((++mthd)->exec);
842
843 NV_INFO(chan->dev, "MM: using %s for buffer copies\n", name);
844}
845
6ee73861
BS
846static int
847nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG
848 bool no_wait_reserve, bool no_wait_gpu,
849 struct ttm_mem_reg *new_mem)
6ee73861
BS
850{
851 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
852 struct ttm_placement placement;
853 struct ttm_mem_reg tmp_mem;
854 int ret;
855
856 placement.fpfn = placement.lpfn = 0;
857 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 858 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS
859
860 tmp_mem = *new_mem;
861 tmp_mem.mm_node = NULL;
9d87fa21 862 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
6ee73861
BS
863 if (ret)
864 return ret;
865
866 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
867 if (ret)
868 goto out;
869
9d87fa21 870 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
6ee73861
BS
871 if (ret)
872 goto out;
873
b8884da6 874 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861 875out:
42311ff9 876 ttm_bo_mem_put(bo, &tmp_mem);
6ee73861
BS
877 return ret;
878}
879
880static int
881nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG
882 bool no_wait_reserve, bool no_wait_gpu,
883 struct ttm_mem_reg *new_mem)
6ee73861
BS
884{
885 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
886 struct ttm_placement placement;
887 struct ttm_mem_reg tmp_mem;
888 int ret;
889
890 placement.fpfn = placement.lpfn = 0;
891 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 892 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS
893
894 tmp_mem = *new_mem;
895 tmp_mem.mm_node = NULL;
9d87fa21 896 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
6ee73861
BS
897 if (ret)
898 return ret;
899
b8884da6 900 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
6ee73861
BS
901 if (ret)
902 goto out;
903
b8884da6 904 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861
BS
905 if (ret)
906 goto out;
907
908out:
42311ff9 909 ttm_bo_mem_put(bo, &tmp_mem);
6ee73861
BS
910 return ret;
911}
912
a4154bbf
BS
913static void
914nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
915{
a4154bbf 916 struct nouveau_bo *nvbo = nouveau_bo(bo);
fd2871af
BS
917 struct nouveau_vma *vma;
918
9f1feed2
BS
919 /* ttm can now (stupidly) pass the driver bos it didn't create... */
920 if (bo->destroy != nouveau_bo_del_ttm)
921 return;
922
fd2871af 923 list_for_each_entry(vma, &nvbo->vma_list, head) {
dc97b340 924 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
fd2871af
BS
925 nouveau_vm_map(vma, new_mem->mm_node);
926 } else
dc97b340 927 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
fd2871af 928 nvbo->page_shift == vma->vm->spg_shift) {
22b33e8e
DA
929 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
930 nouveau_vm_map_sg_table(vma, 0, new_mem->
931 num_pages << PAGE_SHIFT,
932 new_mem->mm_node);
933 else
934 nouveau_vm_map_sg(vma, 0, new_mem->
935 num_pages << PAGE_SHIFT,
936 new_mem->mm_node);
fd2871af
BS
937 } else {
938 nouveau_vm_unmap(vma);
939 }
a4154bbf
BS
940 }
941}
942
6ee73861 943static int
a0af9add
FJ
944nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
945 struct nouveau_tile_reg **new_tile)
6ee73861
BS
946{
947 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
6ee73861 948 struct drm_device *dev = dev_priv->dev;
a0af9add 949 struct nouveau_bo *nvbo = nouveau_bo(bo);
a4154bbf 950 u64 offset = new_mem->start << PAGE_SHIFT;
6ee73861 951
a4154bbf
BS
952 *new_tile = NULL;
953 if (new_mem->mem_type != TTM_PL_VRAM)
a0af9add 954 return 0;
a0af9add 955
a4154bbf 956 if (dev_priv->card_type >= NV_10) {
a0af9add 957 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
a5cf68b0
FJ
958 nvbo->tile_mode,
959 nvbo->tile_flags);
6ee73861
BS
960 }
961
a0af9add
FJ
962 return 0;
963}
964
965static void
966nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
967 struct nouveau_tile_reg *new_tile,
968 struct nouveau_tile_reg **old_tile)
969{
970 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
971 struct drm_device *dev = dev_priv->dev;
972
a4154bbf
BS
973 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
974 *old_tile = new_tile;
a0af9add
FJ
975}
976
977static int
978nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG
979 bool no_wait_reserve, bool no_wait_gpu,
980 struct ttm_mem_reg *new_mem)
a0af9add
FJ
981{
982 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
983 struct nouveau_bo *nvbo = nouveau_bo(bo);
984 struct ttm_mem_reg *old_mem = &bo->mem;
985 struct nouveau_tile_reg *new_tile = NULL;
986 int ret = 0;
987
a4154bbf
BS
988 if (dev_priv->card_type < NV_50) {
989 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
990 if (ret)
991 return ret;
992 }
a0af9add 993
a0af9add 994 /* Fake bo copy. */
6ee73861
BS
995 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
996 BUG_ON(bo->mem.mm_node != NULL);
997 bo->mem = *new_mem;
998 new_mem->mm_node = NULL;
a0af9add 999 goto out;
6ee73861
BS
1000 }
1001
d1b167e1
BS
1002 /* CPU copy if we have no accelerated method available */
1003 if (!dev_priv->ttm.move) {
b8a6a804
BS
1004 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1005 goto out;
1006 }
1007
a0af9add
FJ
1008 /* Hardware assisted copy. */
1009 if (new_mem->mem_type == TTM_PL_SYSTEM)
9d87fa21 1010 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add 1011 else if (old_mem->mem_type == TTM_PL_SYSTEM)
9d87fa21 1012 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add 1013 else
9d87fa21 1014 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861 1015
a0af9add
FJ
1016 if (!ret)
1017 goto out;
1018
1019 /* Fallback to software copy. */
9d87fa21 1020 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add
FJ
1021
1022out:
a4154bbf
BS
1023 if (dev_priv->card_type < NV_50) {
1024 if (ret)
1025 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1026 else
1027 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1028 }
a0af9add
FJ
1029
1030 return ret;
6ee73861
BS
1031}
1032
1033static int
1034nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1035{
1036 return 0;
1037}
1038
f32f02fd
JG
1039static int
1040nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1041{
1042 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1043 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
1044 struct drm_device *dev = dev_priv->dev;
f869ef88 1045 int ret;
f32f02fd
JG
1046
1047 mem->bus.addr = NULL;
1048 mem->bus.offset = 0;
1049 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1050 mem->bus.base = 0;
1051 mem->bus.is_iomem = false;
1052 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1053 return -EINVAL;
1054 switch (mem->mem_type) {
1055 case TTM_PL_SYSTEM:
1056 /* System memory */
1057 return 0;
1058 case TTM_PL_TT:
1059#if __OS_HAS_AGP
1060 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
d961db75 1061 mem->bus.offset = mem->start << PAGE_SHIFT;
f32f02fd
JG
1062 mem->bus.base = dev_priv->gart_info.aper_base;
1063 mem->bus.is_iomem = true;
1064 }
1065#endif
1066 break;
1067 case TTM_PL_VRAM:
f869ef88 1068 {
d5f42394 1069 struct nouveau_mem *node = mem->mm_node;
8984e046 1070 u8 page_shift;
f869ef88
BS
1071
1072 if (!dev_priv->bar1_vm) {
1073 mem->bus.offset = mem->start << PAGE_SHIFT;
1074 mem->bus.base = pci_resource_start(dev->pdev, 1);
1075 mem->bus.is_iomem = true;
1076 break;
1077 }
1078
2e9733ff 1079 if (dev_priv->card_type >= NV_C0)
d5f42394 1080 page_shift = node->page_shift;
8984e046
BS
1081 else
1082 page_shift = 12;
1083
4c74eb7f 1084 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
8984e046 1085 page_shift, NV_MEM_ACCESS_RW,
d5f42394 1086 &node->bar_vma);
f869ef88
BS
1087 if (ret)
1088 return ret;
1089
d5f42394 1090 nouveau_vm_map(&node->bar_vma, node);
f869ef88 1091 if (ret) {
d5f42394 1092 nouveau_vm_put(&node->bar_vma);
f869ef88
BS
1093 return ret;
1094 }
1095
d5f42394 1096 mem->bus.offset = node->bar_vma.offset;
8984e046
BS
1097 if (dev_priv->card_type == NV_50) /*XXX*/
1098 mem->bus.offset -= 0x0020000000ULL;
01d73a69 1099 mem->bus.base = pci_resource_start(dev->pdev, 1);
f32f02fd 1100 mem->bus.is_iomem = true;
f869ef88 1101 }
f32f02fd
JG
1102 break;
1103 default:
1104 return -EINVAL;
1105 }
1106 return 0;
1107}
1108
1109static void
1110nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1111{
f869ef88 1112 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
d5f42394 1113 struct nouveau_mem *node = mem->mm_node;
f869ef88
BS
1114
1115 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
1116 return;
1117
d5f42394 1118 if (!node->bar_vma.node)
f869ef88
BS
1119 return;
1120
d5f42394
BS
1121 nouveau_vm_unmap(&node->bar_vma);
1122 nouveau_vm_put(&node->bar_vma);
f32f02fd
JG
1123}
1124
1125static int
1126nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1127{
e1429b4c
BS
1128 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1129 struct nouveau_bo *nvbo = nouveau_bo(bo);
1130
1131 /* as long as the bo isn't in vram, and isn't tiled, we've got
1132 * nothing to do here.
1133 */
1134 if (bo->mem.mem_type != TTM_PL_VRAM) {
f13b3263
FJ
1135 if (dev_priv->card_type < NV_50 ||
1136 !nouveau_bo_tile_layout(nvbo))
e1429b4c
BS
1137 return 0;
1138 }
1139
1140 /* make sure bo is in mappable vram */
d961db75 1141 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
e1429b4c
BS
1142 return 0;
1143
1144
1145 nvbo->placement.fpfn = 0;
1146 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
c284815d 1147 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
7a45d764 1148 return nouveau_bo_validate(nvbo, false, true, false);
f32f02fd
JG
1149}
1150
3230cfc3
KRW
1151static int
1152nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1153{
8e7e7052 1154 struct ttm_dma_tt *ttm_dma = (void *)ttm;
3230cfc3
KRW
1155 struct drm_nouveau_private *dev_priv;
1156 struct drm_device *dev;
1157 unsigned i;
1158 int r;
22b33e8e 1159 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
3230cfc3
KRW
1160
1161 if (ttm->state != tt_unpopulated)
1162 return 0;
1163
22b33e8e
DA
1164 if (slave && ttm->sg) {
1165 /* make userspace faulting work */
1166 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1167 ttm_dma->dma_address, ttm->num_pages);
1168 ttm->state = tt_unbound;
1169 return 0;
1170 }
1171
3230cfc3
KRW
1172 dev_priv = nouveau_bdev(ttm->bdev);
1173 dev = dev_priv->dev;
1174
dea7e0ac
JG
1175#if __OS_HAS_AGP
1176 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1177 return ttm_agp_tt_populate(ttm);
1178 }
1179#endif
1180
3230cfc3
KRW
1181#ifdef CONFIG_SWIOTLB
1182 if (swiotlb_nr_tbl()) {
8e7e7052 1183 return ttm_dma_populate((void *)ttm, dev->dev);
3230cfc3
KRW
1184 }
1185#endif
1186
1187 r = ttm_pool_populate(ttm);
1188 if (r) {
1189 return r;
1190 }
1191
1192 for (i = 0; i < ttm->num_pages; i++) {
8e7e7052 1193 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
3230cfc3
KRW
1194 0, PAGE_SIZE,
1195 PCI_DMA_BIDIRECTIONAL);
8e7e7052 1196 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
3230cfc3 1197 while (--i) {
8e7e7052 1198 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
3230cfc3 1199 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
8e7e7052 1200 ttm_dma->dma_address[i] = 0;
3230cfc3
KRW
1201 }
1202 ttm_pool_unpopulate(ttm);
1203 return -EFAULT;
1204 }
1205 }
1206 return 0;
1207}
1208
1209static void
1210nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1211{
8e7e7052 1212 struct ttm_dma_tt *ttm_dma = (void *)ttm;
3230cfc3
KRW
1213 struct drm_nouveau_private *dev_priv;
1214 struct drm_device *dev;
1215 unsigned i;
22b33e8e
DA
1216 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1217
1218 if (slave)
1219 return;
3230cfc3
KRW
1220
1221 dev_priv = nouveau_bdev(ttm->bdev);
1222 dev = dev_priv->dev;
1223
dea7e0ac
JG
1224#if __OS_HAS_AGP
1225 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1226 ttm_agp_tt_unpopulate(ttm);
1227 return;
1228 }
1229#endif
1230
3230cfc3
KRW
1231#ifdef CONFIG_SWIOTLB
1232 if (swiotlb_nr_tbl()) {
8e7e7052 1233 ttm_dma_unpopulate((void *)ttm, dev->dev);
3230cfc3
KRW
1234 return;
1235 }
1236#endif
1237
1238 for (i = 0; i < ttm->num_pages; i++) {
8e7e7052
JG
1239 if (ttm_dma->dma_address[i]) {
1240 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
3230cfc3
KRW
1241 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1242 }
1243 }
1244
1245 ttm_pool_unpopulate(ttm);
1246}
1247
875ac34a
BS
1248void
1249nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1250{
1251 struct nouveau_fence *old_fence = NULL;
1252
1253 if (likely(fence))
1254 nouveau_fence_ref(fence);
1255
1256 spin_lock(&nvbo->bo.bdev->fence_lock);
1257 old_fence = nvbo->bo.sync_obj;
1258 nvbo->bo.sync_obj = fence;
1259 spin_unlock(&nvbo->bo.bdev->fence_lock);
1260
1261 nouveau_fence_unref(&old_fence);
1262}
1263
1264static void
1265nouveau_bo_fence_unref(void **sync_obj)
1266{
1267 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1268}
1269
1270static void *
1271nouveau_bo_fence_ref(void *sync_obj)
1272{
1273 return nouveau_fence_ref(sync_obj);
1274}
1275
1276static bool
1277nouveau_bo_fence_signalled(void *sync_obj, void *sync_arg)
1278{
d375e7d5 1279 return nouveau_fence_done(sync_obj);
875ac34a
BS
1280}
1281
1282static int
1283nouveau_bo_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
1284{
1285 return nouveau_fence_wait(sync_obj, lazy, intr);
1286}
1287
1288static int
1289nouveau_bo_fence_flush(void *sync_obj, void *sync_arg)
1290{
1291 return 0;
1292}
1293
6ee73861 1294struct ttm_bo_driver nouveau_bo_driver = {
649bf3ca 1295 .ttm_tt_create = &nouveau_ttm_tt_create,
3230cfc3
KRW
1296 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1297 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
6ee73861
BS
1298 .invalidate_caches = nouveau_bo_invalidate_caches,
1299 .init_mem_type = nouveau_bo_init_mem_type,
1300 .evict_flags = nouveau_bo_evict_flags,
a4154bbf 1301 .move_notify = nouveau_bo_move_ntfy,
6ee73861
BS
1302 .move = nouveau_bo_move,
1303 .verify_access = nouveau_bo_verify_access,
875ac34a
BS
1304 .sync_obj_signaled = nouveau_bo_fence_signalled,
1305 .sync_obj_wait = nouveau_bo_fence_wait,
1306 .sync_obj_flush = nouveau_bo_fence_flush,
1307 .sync_obj_unref = nouveau_bo_fence_unref,
1308 .sync_obj_ref = nouveau_bo_fence_ref,
f32f02fd
JG
1309 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1310 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1311 .io_mem_free = &nouveau_ttm_io_mem_free,
6ee73861
BS
1312};
1313
fd2871af
BS
1314struct nouveau_vma *
1315nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1316{
1317 struct nouveau_vma *vma;
1318 list_for_each_entry(vma, &nvbo->vma_list, head) {
1319 if (vma->vm == vm)
1320 return vma;
1321 }
1322
1323 return NULL;
1324}
1325
1326int
1327nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1328 struct nouveau_vma *vma)
1329{
1330 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1331 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1332 int ret;
1333
1334 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1335 NV_MEM_ACCESS_RW, vma);
1336 if (ret)
1337 return ret;
1338
1339 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1340 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
22b33e8e
DA
1341 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1342 if (node->sg)
1343 nouveau_vm_map_sg_table(vma, 0, size, node);
1344 else
1345 nouveau_vm_map_sg(vma, 0, size, node);
1346 }
fd2871af
BS
1347
1348 list_add_tail(&vma->head, &nvbo->vma_list);
2fd3db6f 1349 vma->refcount = 1;
fd2871af
BS
1350 return 0;
1351}
1352
1353void
1354nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1355{
1356 if (vma->node) {
1357 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1358 spin_lock(&nvbo->bo.bdev->fence_lock);
1717c0e2 1359 ttm_bo_wait(&nvbo->bo, false, false, false);
fd2871af
BS
1360 spin_unlock(&nvbo->bo.bdev->fence_lock);
1361 nouveau_vm_unmap(vma);
1362 }
1363
1364 nouveau_vm_put(vma);
1365 list_del(&vma->head);
1366 }
1367}