Commit | Line | Data |
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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
fdb751ef | 30 | #include <linux/dma-mapping.h> |
3e2b756b | 31 | #include <linux/swiotlb.h> |
6ee73861 | 32 | |
ebb945a9 | 33 | #include "nouveau_drm.h" |
6ee73861 | 34 | #include "nouveau_dma.h" |
d375e7d5 | 35 | #include "nouveau_fence.h" |
6ee73861 | 36 | |
ebb945a9 BS |
37 | #include "nouveau_bo.h" |
38 | #include "nouveau_ttm.h" | |
39 | #include "nouveau_gem.h" | |
a510604d | 40 | |
bc9e7b9a BS |
41 | /* |
42 | * NV10-NV40 tiling helpers | |
43 | */ | |
44 | ||
45 | static void | |
ebb945a9 BS |
46 | nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, |
47 | u32 addr, u32 size, u32 pitch, u32 flags) | |
bc9e7b9a | 48 | { |
77145f1c | 49 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 50 | int i = reg - drm->tile.reg; |
c85ee6ca BS |
51 | struct nvkm_device *device = nvxx_device(&drm->device); |
52 | struct nvkm_fb *fb = device->fb; | |
b1e4553c | 53 | struct nvkm_fb_tile *tile = &fb->tile.region[i]; |
bc9e7b9a | 54 | |
ebb945a9 | 55 | nouveau_fence_unref(®->fence); |
bc9e7b9a BS |
56 | |
57 | if (tile->pitch) | |
03c8952f | 58 | nvkm_fb_tile_fini(fb, i, tile); |
bc9e7b9a BS |
59 | |
60 | if (pitch) | |
03c8952f | 61 | nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); |
bc9e7b9a | 62 | |
03c8952f | 63 | nvkm_fb_tile_prog(fb, i, tile); |
bc9e7b9a BS |
64 | } |
65 | ||
ebb945a9 | 66 | static struct nouveau_drm_tile * |
bc9e7b9a BS |
67 | nv10_bo_get_tile_region(struct drm_device *dev, int i) |
68 | { | |
77145f1c | 69 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 70 | struct nouveau_drm_tile *tile = &drm->tile.reg[i]; |
bc9e7b9a | 71 | |
ebb945a9 | 72 | spin_lock(&drm->tile.lock); |
bc9e7b9a BS |
73 | |
74 | if (!tile->used && | |
75 | (!tile->fence || nouveau_fence_done(tile->fence))) | |
76 | tile->used = true; | |
77 | else | |
78 | tile = NULL; | |
79 | ||
ebb945a9 | 80 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
81 | return tile; |
82 | } | |
83 | ||
84 | static void | |
ebb945a9 | 85 | nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, |
f2c24b83 | 86 | struct fence *fence) |
bc9e7b9a | 87 | { |
77145f1c | 88 | struct nouveau_drm *drm = nouveau_drm(dev); |
bc9e7b9a BS |
89 | |
90 | if (tile) { | |
ebb945a9 | 91 | spin_lock(&drm->tile.lock); |
809e9447 | 92 | tile->fence = (struct nouveau_fence *)fence_get(fence); |
bc9e7b9a | 93 | tile->used = false; |
ebb945a9 | 94 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
95 | } |
96 | } | |
97 | ||
ebb945a9 BS |
98 | static struct nouveau_drm_tile * |
99 | nv10_bo_set_tiling(struct drm_device *dev, u32 addr, | |
100 | u32 size, u32 pitch, u32 flags) | |
bc9e7b9a | 101 | { |
77145f1c | 102 | struct nouveau_drm *drm = nouveau_drm(dev); |
b1e4553c | 103 | struct nvkm_fb *fb = nvxx_fb(&drm->device); |
ebb945a9 | 104 | struct nouveau_drm_tile *tile, *found = NULL; |
bc9e7b9a BS |
105 | int i; |
106 | ||
b1e4553c | 107 | for (i = 0; i < fb->tile.regions; i++) { |
bc9e7b9a BS |
108 | tile = nv10_bo_get_tile_region(dev, i); |
109 | ||
110 | if (pitch && !found) { | |
111 | found = tile; | |
112 | continue; | |
113 | ||
b1e4553c | 114 | } else if (tile && fb->tile.region[i].pitch) { |
bc9e7b9a BS |
115 | /* Kill an unused tile region. */ |
116 | nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); | |
117 | } | |
118 | ||
119 | nv10_bo_put_tile_region(dev, tile, NULL); | |
120 | } | |
121 | ||
122 | if (found) | |
123 | nv10_bo_update_tile_region(dev, found, addr, size, | |
124 | pitch, flags); | |
125 | return found; | |
126 | } | |
127 | ||
6ee73861 BS |
128 | static void |
129 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
130 | { | |
ebb945a9 BS |
131 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
132 | struct drm_device *dev = drm->dev; | |
6ee73861 BS |
133 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
134 | ||
55fb74ad | 135 | if (unlikely(nvbo->gem.filp)) |
6ee73861 | 136 | DRM_ERROR("bo %p still attached to GEM object\n", bo); |
4f385599 | 137 | WARN_ON(nvbo->pin_refcnt > 0); |
bc9e7b9a | 138 | nv10_bo_put_tile_region(dev, nvbo->tile, NULL); |
6ee73861 BS |
139 | kfree(nvbo); |
140 | } | |
141 | ||
a0af9add | 142 | static void |
db5c8e29 | 143 | nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, |
f91bac5b | 144 | int *align, int *size) |
a0af9add | 145 | { |
ebb945a9 | 146 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
967e7bde | 147 | struct nvif_device *device = &drm->device; |
a0af9add | 148 | |
967e7bde | 149 | if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { |
bfd83aca | 150 | if (nvbo->tile_mode) { |
967e7bde | 151 | if (device->info.chipset >= 0x40) { |
a0af9add | 152 | *align = 65536; |
bfd83aca | 153 | *size = roundup(*size, 64 * nvbo->tile_mode); |
a0af9add | 154 | |
967e7bde | 155 | } else if (device->info.chipset >= 0x30) { |
a0af9add | 156 | *align = 32768; |
bfd83aca | 157 | *size = roundup(*size, 64 * nvbo->tile_mode); |
a0af9add | 158 | |
967e7bde | 159 | } else if (device->info.chipset >= 0x20) { |
a0af9add | 160 | *align = 16384; |
bfd83aca | 161 | *size = roundup(*size, 64 * nvbo->tile_mode); |
a0af9add | 162 | |
967e7bde | 163 | } else if (device->info.chipset >= 0x10) { |
a0af9add | 164 | *align = 16384; |
bfd83aca | 165 | *size = roundup(*size, 32 * nvbo->tile_mode); |
a0af9add FJ |
166 | } |
167 | } | |
bfd83aca | 168 | } else { |
f91bac5b BS |
169 | *size = roundup(*size, (1 << nvbo->page_shift)); |
170 | *align = max((1 << nvbo->page_shift), *align); | |
a0af9add FJ |
171 | } |
172 | ||
1c7059e4 | 173 | *size = roundup(*size, PAGE_SIZE); |
a0af9add FJ |
174 | } |
175 | ||
6ee73861 | 176 | int |
7375c95b BS |
177 | nouveau_bo_new(struct drm_device *dev, int size, int align, |
178 | uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, | |
bb6178b0 | 179 | struct sg_table *sg, struct reservation_object *robj, |
7375c95b | 180 | struct nouveau_bo **pnvbo) |
6ee73861 | 181 | { |
77145f1c | 182 | struct nouveau_drm *drm = nouveau_drm(dev); |
6ee73861 | 183 | struct nouveau_bo *nvbo; |
57de4ba9 | 184 | size_t acc_size; |
f91bac5b | 185 | int ret; |
22b33e8e | 186 | int type = ttm_bo_type_device; |
35095f75 ML |
187 | int lpg_shift = 12; |
188 | int max_size; | |
189 | ||
3ee6f5b5 | 190 | if (drm->client.vm) |
5ce3bf3c | 191 | lpg_shift = drm->client.vm->mmu->lpg_shift; |
35095f75 | 192 | max_size = INT_MAX & ~((1 << lpg_shift) - 1); |
0108bc80 ML |
193 | |
194 | if (size <= 0 || size > max_size) { | |
fa2bade9 | 195 | NV_WARN(drm, "skipped size %x\n", (u32)size); |
0108bc80 ML |
196 | return -EINVAL; |
197 | } | |
22b33e8e DA |
198 | |
199 | if (sg) | |
200 | type = ttm_bo_type_sg; | |
6ee73861 BS |
201 | |
202 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
203 | if (!nvbo) | |
204 | return -ENOMEM; | |
205 | INIT_LIST_HEAD(&nvbo->head); | |
206 | INIT_LIST_HEAD(&nvbo->entry); | |
fd2871af | 207 | INIT_LIST_HEAD(&nvbo->vma_list); |
6ee73861 BS |
208 | nvbo->tile_mode = tile_mode; |
209 | nvbo->tile_flags = tile_flags; | |
ebb945a9 | 210 | nvbo->bo.bdev = &drm->ttm.bdev; |
6ee73861 | 211 | |
26c9e8ef | 212 | if (!nvxx_device(&drm->device)->func->cpu_coherent) |
c3a0c771 AC |
213 | nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; |
214 | ||
f91bac5b | 215 | nvbo->page_shift = 12; |
3ee6f5b5 | 216 | if (drm->client.vm) { |
f91bac5b | 217 | if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) |
5ce3bf3c | 218 | nvbo->page_shift = drm->client.vm->mmu->lpg_shift; |
f91bac5b BS |
219 | } |
220 | ||
221 | nouveau_bo_fixup_align(nvbo, flags, &align, &size); | |
fd2871af BS |
222 | nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; |
223 | nouveau_bo_placement_set(nvbo, flags, 0); | |
6ee73861 | 224 | |
ebb945a9 | 225 | acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, |
57de4ba9 JG |
226 | sizeof(struct nouveau_bo)); |
227 | ||
ebb945a9 | 228 | ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, |
22b33e8e | 229 | type, &nvbo->placement, |
0b91c4a1 | 230 | align >> PAGE_SHIFT, false, NULL, acc_size, sg, |
bb6178b0 | 231 | robj, nouveau_bo_del_ttm); |
6ee73861 BS |
232 | if (ret) { |
233 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
234 | return ret; | |
235 | } | |
236 | ||
6ee73861 BS |
237 | *pnvbo = nvbo; |
238 | return 0; | |
239 | } | |
240 | ||
78ad0f7b | 241 | static void |
f1217ed0 | 242 | set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) |
78ad0f7b FJ |
243 | { |
244 | *n = 0; | |
245 | ||
246 | if (type & TTM_PL_FLAG_VRAM) | |
f1217ed0 | 247 | pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; |
78ad0f7b | 248 | if (type & TTM_PL_FLAG_TT) |
f1217ed0 | 249 | pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; |
78ad0f7b | 250 | if (type & TTM_PL_FLAG_SYSTEM) |
f1217ed0 | 251 | pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; |
78ad0f7b FJ |
252 | } |
253 | ||
699ddfd9 FJ |
254 | static void |
255 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) | |
256 | { | |
ebb945a9 | 257 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
f392ec4b | 258 | u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT; |
f1217ed0 | 259 | unsigned i, fpfn, lpfn; |
699ddfd9 | 260 | |
967e7bde | 261 | if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && |
812f219a | 262 | nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) && |
4beb116a | 263 | nvbo->bo.mem.num_pages < vram_pages / 4) { |
699ddfd9 FJ |
264 | /* |
265 | * Make sure that the color and depth buffers are handled | |
266 | * by independent memory controller units. Up to a 9x | |
267 | * speed up when alpha-blending and depth-test are enabled | |
268 | * at the same time. | |
269 | */ | |
699ddfd9 | 270 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { |
f1217ed0 CK |
271 | fpfn = vram_pages / 2; |
272 | lpfn = ~0; | |
699ddfd9 | 273 | } else { |
f1217ed0 CK |
274 | fpfn = 0; |
275 | lpfn = vram_pages / 2; | |
276 | } | |
277 | for (i = 0; i < nvbo->placement.num_placement; ++i) { | |
278 | nvbo->placements[i].fpfn = fpfn; | |
279 | nvbo->placements[i].lpfn = lpfn; | |
280 | } | |
281 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { | |
282 | nvbo->busy_placements[i].fpfn = fpfn; | |
283 | nvbo->busy_placements[i].lpfn = lpfn; | |
699ddfd9 FJ |
284 | } |
285 | } | |
286 | } | |
287 | ||
6ee73861 | 288 | void |
78ad0f7b | 289 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
6ee73861 | 290 | { |
78ad0f7b | 291 | struct ttm_placement *pl = &nvbo->placement; |
c3a0c771 AC |
292 | uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : |
293 | TTM_PL_MASK_CACHING) | | |
294 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); | |
78ad0f7b FJ |
295 | |
296 | pl->placement = nvbo->placements; | |
297 | set_placement_list(nvbo->placements, &pl->num_placement, | |
298 | type, flags); | |
299 | ||
300 | pl->busy_placement = nvbo->busy_placements; | |
301 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, | |
302 | type | busy, flags); | |
699ddfd9 FJ |
303 | |
304 | set_placement_range(nvbo, type); | |
6ee73861 BS |
305 | } |
306 | ||
307 | int | |
ad76b3f7 | 308 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) |
6ee73861 | 309 | { |
ebb945a9 | 310 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 311 | struct ttm_buffer_object *bo = &nvbo->bo; |
ad76b3f7 | 312 | bool force = false, evict = false; |
78ad0f7b | 313 | int ret; |
6ee73861 | 314 | |
ee3939e0 | 315 | ret = ttm_bo_reserve(bo, false, false, false, NULL); |
0ae6d7bc | 316 | if (ret) |
50ab2e52 | 317 | return ret; |
0ae6d7bc | 318 | |
ad76b3f7 BS |
319 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA && |
320 | memtype == TTM_PL_FLAG_VRAM && contig) { | |
321 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { | |
322 | if (bo->mem.mem_type == TTM_PL_VRAM) { | |
be83cd4e | 323 | struct nvkm_mem *mem = bo->mem.mm_node; |
ad76b3f7 BS |
324 | if (!list_is_singular(&mem->regions)) |
325 | evict = true; | |
326 | } | |
327 | nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG; | |
328 | force = true; | |
329 | } | |
6ee73861 BS |
330 | } |
331 | ||
ad76b3f7 BS |
332 | if (nvbo->pin_refcnt) { |
333 | if (!(memtype & (1 << bo->mem.mem_type)) || evict) { | |
334 | NV_ERROR(drm, "bo %p pinned elsewhere: " | |
335 | "0x%08x vs 0x%08x\n", bo, | |
336 | 1 << bo->mem.mem_type, memtype); | |
337 | ret = -EBUSY; | |
338 | } | |
339 | nvbo->pin_refcnt++; | |
50ab2e52 | 340 | goto out; |
ad76b3f7 BS |
341 | } |
342 | ||
343 | if (evict) { | |
344 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); | |
345 | ret = nouveau_bo_validate(nvbo, false, false); | |
346 | if (ret) | |
347 | goto out; | |
348 | } | |
6ee73861 | 349 | |
ad76b3f7 | 350 | nvbo->pin_refcnt++; |
78ad0f7b | 351 | nouveau_bo_placement_set(nvbo, memtype, 0); |
6ee73861 | 352 | |
50ab2e52 BS |
353 | /* drop pin_refcnt temporarily, so we don't trip the assertion |
354 | * in nouveau_bo_move() that makes sure we're not trying to | |
355 | * move a pinned buffer | |
356 | */ | |
357 | nvbo->pin_refcnt--; | |
97a875cb | 358 | ret = nouveau_bo_validate(nvbo, false, false); |
6aac6ced BS |
359 | if (ret) |
360 | goto out; | |
50ab2e52 | 361 | nvbo->pin_refcnt++; |
6aac6ced BS |
362 | |
363 | switch (bo->mem.mem_type) { | |
364 | case TTM_PL_VRAM: | |
365 | drm->gem.vram_available -= bo->mem.size; | |
366 | break; | |
367 | case TTM_PL_TT: | |
368 | drm->gem.gart_available -= bo->mem.size; | |
369 | break; | |
370 | default: | |
371 | break; | |
6ee73861 | 372 | } |
5be5a15a | 373 | |
6ee73861 | 374 | out: |
ad76b3f7 BS |
375 | if (force && ret) |
376 | nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG; | |
0ae6d7bc | 377 | ttm_bo_unreserve(bo); |
6ee73861 BS |
378 | return ret; |
379 | } | |
380 | ||
381 | int | |
382 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
383 | { | |
ebb945a9 | 384 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 385 | struct ttm_buffer_object *bo = &nvbo->bo; |
4f385599 | 386 | int ret, ref; |
6ee73861 | 387 | |
ee3939e0 | 388 | ret = ttm_bo_reserve(bo, false, false, false, NULL); |
6ee73861 BS |
389 | if (ret) |
390 | return ret; | |
391 | ||
4f385599 ML |
392 | ref = --nvbo->pin_refcnt; |
393 | WARN_ON_ONCE(ref < 0); | |
394 | if (ref) | |
0ae6d7bc DV |
395 | goto out; |
396 | ||
78ad0f7b | 397 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
6ee73861 | 398 | |
97a875cb | 399 | ret = nouveau_bo_validate(nvbo, false, false); |
6ee73861 BS |
400 | if (ret == 0) { |
401 | switch (bo->mem.mem_type) { | |
402 | case TTM_PL_VRAM: | |
ebb945a9 | 403 | drm->gem.vram_available += bo->mem.size; |
6ee73861 BS |
404 | break; |
405 | case TTM_PL_TT: | |
ebb945a9 | 406 | drm->gem.gart_available += bo->mem.size; |
6ee73861 BS |
407 | break; |
408 | default: | |
409 | break; | |
410 | } | |
411 | } | |
412 | ||
0ae6d7bc | 413 | out: |
6ee73861 BS |
414 | ttm_bo_unreserve(bo); |
415 | return ret; | |
416 | } | |
417 | ||
418 | int | |
419 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
420 | { | |
421 | int ret; | |
422 | ||
ee3939e0 | 423 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL); |
6ee73861 BS |
424 | if (ret) |
425 | return ret; | |
426 | ||
c3a0c771 AC |
427 | /* |
428 | * TTM buffers allocated using the DMA API already have a mapping, let's | |
429 | * use it instead. | |
430 | */ | |
431 | if (!nvbo->force_coherent) | |
432 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, | |
433 | &nvbo->kmap); | |
434 | ||
6ee73861 BS |
435 | ttm_bo_unreserve(&nvbo->bo); |
436 | return ret; | |
437 | } | |
438 | ||
439 | void | |
440 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
441 | { | |
c3a0c771 AC |
442 | if (!nvbo) |
443 | return; | |
444 | ||
445 | /* | |
446 | * TTM buffers allocated using the DMA API already had a coherent | |
447 | * mapping which we used, no need to unmap. | |
448 | */ | |
449 | if (!nvbo->force_coherent) | |
9d59e8a1 | 450 | ttm_bo_kunmap(&nvbo->kmap); |
6ee73861 BS |
451 | } |
452 | ||
b22870ba AC |
453 | void |
454 | nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) | |
455 | { | |
456 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); | |
be83cd4e | 457 | struct nvkm_device *device = nvxx_device(&drm->device); |
b22870ba AC |
458 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
459 | int i; | |
460 | ||
461 | if (!ttm_dma) | |
462 | return; | |
463 | ||
464 | /* Don't waste time looping if the object is coherent */ | |
465 | if (nvbo->force_coherent) | |
466 | return; | |
467 | ||
468 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) | |
26c9e8ef BS |
469 | dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i], |
470 | PAGE_SIZE, DMA_TO_DEVICE); | |
b22870ba AC |
471 | } |
472 | ||
473 | void | |
474 | nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) | |
475 | { | |
476 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); | |
be83cd4e | 477 | struct nvkm_device *device = nvxx_device(&drm->device); |
b22870ba AC |
478 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
479 | int i; | |
480 | ||
481 | if (!ttm_dma) | |
482 | return; | |
483 | ||
484 | /* Don't waste time looping if the object is coherent */ | |
485 | if (nvbo->force_coherent) | |
486 | return; | |
487 | ||
488 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) | |
26c9e8ef BS |
489 | dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i], |
490 | PAGE_SIZE, DMA_FROM_DEVICE); | |
b22870ba AC |
491 | } |
492 | ||
7a45d764 BS |
493 | int |
494 | nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, | |
97a875cb | 495 | bool no_wait_gpu) |
7a45d764 BS |
496 | { |
497 | int ret; | |
498 | ||
97a875cb ML |
499 | ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, |
500 | interruptible, no_wait_gpu); | |
7a45d764 BS |
501 | if (ret) |
502 | return ret; | |
503 | ||
b22870ba AC |
504 | nouveau_bo_sync_for_device(nvbo); |
505 | ||
7a45d764 BS |
506 | return 0; |
507 | } | |
508 | ||
c3a0c771 AC |
509 | static inline void * |
510 | _nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz) | |
511 | { | |
512 | struct ttm_dma_tt *dma_tt; | |
513 | u8 *m = mem; | |
514 | ||
515 | index *= sz; | |
516 | ||
517 | if (m) { | |
518 | /* kmap'd address, return the corresponding offset */ | |
519 | m += index; | |
520 | } else { | |
521 | /* DMA-API mapping, lookup the right address */ | |
522 | dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm; | |
523 | m = dma_tt->cpu_address[index / PAGE_SIZE]; | |
524 | m += index % PAGE_SIZE; | |
525 | } | |
526 | ||
527 | return m; | |
528 | } | |
529 | #define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m)) | |
530 | ||
6ee73861 BS |
531 | void |
532 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
533 | { | |
534 | bool is_iomem; | |
535 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 AC |
536 | |
537 | mem = nouveau_bo_mem_index(nvbo, index, mem); | |
538 | ||
6ee73861 BS |
539 | if (is_iomem) |
540 | iowrite16_native(val, (void __force __iomem *)mem); | |
541 | else | |
542 | *mem = val; | |
543 | } | |
544 | ||
545 | u32 | |
546 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
547 | { | |
548 | bool is_iomem; | |
549 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 AC |
550 | |
551 | mem = nouveau_bo_mem_index(nvbo, index, mem); | |
552 | ||
6ee73861 BS |
553 | if (is_iomem) |
554 | return ioread32_native((void __force __iomem *)mem); | |
555 | else | |
556 | return *mem; | |
557 | } | |
558 | ||
559 | void | |
560 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
561 | { | |
562 | bool is_iomem; | |
563 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 AC |
564 | |
565 | mem = nouveau_bo_mem_index(nvbo, index, mem); | |
566 | ||
6ee73861 BS |
567 | if (is_iomem) |
568 | iowrite32_native(val, (void __force __iomem *)mem); | |
569 | else | |
570 | *mem = val; | |
571 | } | |
572 | ||
649bf3ca | 573 | static struct ttm_tt * |
ebb945a9 BS |
574 | nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, |
575 | uint32_t page_flags, struct page *dummy_read) | |
6ee73861 | 576 | { |
a7fb8a23 | 577 | #if IS_ENABLED(CONFIG_AGP) |
ebb945a9 | 578 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
6ee73861 | 579 | |
340b0e7c BS |
580 | if (drm->agp.bridge) { |
581 | return ttm_agp_tt_create(bdev, drm->agp.bridge, size, | |
ebb945a9 | 582 | page_flags, dummy_read); |
6ee73861 | 583 | } |
df1b4b91 | 584 | #endif |
6ee73861 | 585 | |
ebb945a9 | 586 | return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read); |
6ee73861 BS |
587 | } |
588 | ||
589 | static int | |
590 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
591 | { | |
592 | /* We'll do this from user space. */ | |
593 | return 0; | |
594 | } | |
595 | ||
596 | static int | |
597 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
598 | struct ttm_mem_type_manager *man) | |
599 | { | |
ebb945a9 | 600 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
6ee73861 BS |
601 | |
602 | switch (type) { | |
603 | case TTM_PL_SYSTEM: | |
604 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
605 | man->available_caching = TTM_PL_MASK_CACHING; | |
606 | man->default_caching = TTM_PL_FLAG_CACHED; | |
607 | break; | |
608 | case TTM_PL_VRAM: | |
e2a4e78c AC |
609 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
610 | TTM_MEMTYPE_FLAG_MAPPABLE; | |
611 | man->available_caching = TTM_PL_FLAG_UNCACHED | | |
612 | TTM_PL_FLAG_WC; | |
613 | man->default_caching = TTM_PL_FLAG_WC; | |
614 | ||
967e7bde | 615 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
e2a4e78c | 616 | /* Some BARs do not support being ioremapped WC */ |
989aa5b7 | 617 | if (nvxx_bar(&drm->device)->iomap_uncached) { |
e2a4e78c AC |
618 | man->available_caching = TTM_PL_FLAG_UNCACHED; |
619 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
620 | } | |
621 | ||
573a2a37 | 622 | man->func = &nouveau_vram_manager; |
f869ef88 BS |
623 | man->io_reserve_fastpath = false; |
624 | man->use_io_reserve_lru = true; | |
625 | } else { | |
573a2a37 | 626 | man->func = &ttm_bo_manager_func; |
f869ef88 | 627 | } |
6ee73861 BS |
628 | break; |
629 | case TTM_PL_TT: | |
967e7bde | 630 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) |
26c0c9e3 | 631 | man->func = &nouveau_gart_manager; |
3863c9bc | 632 | else |
340b0e7c | 633 | if (!drm->agp.bridge) |
3863c9bc | 634 | man->func = &nv04_gart_manager; |
26c0c9e3 BS |
635 | else |
636 | man->func = &ttm_bo_manager_func; | |
ebb945a9 | 637 | |
340b0e7c | 638 | if (drm->agp.bridge) { |
f32f02fd | 639 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
a3d487ea FJ |
640 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
641 | TTM_PL_FLAG_WC; | |
642 | man->default_caching = TTM_PL_FLAG_WC; | |
ebb945a9 | 643 | } else { |
6ee73861 BS |
644 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | |
645 | TTM_MEMTYPE_FLAG_CMA; | |
646 | man->available_caching = TTM_PL_MASK_CACHING; | |
647 | man->default_caching = TTM_PL_FLAG_CACHED; | |
6ee73861 | 648 | } |
ebb945a9 | 649 | |
6ee73861 BS |
650 | break; |
651 | default: | |
6ee73861 BS |
652 | return -EINVAL; |
653 | } | |
654 | return 0; | |
655 | } | |
656 | ||
657 | static void | |
658 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
659 | { | |
660 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
661 | ||
662 | switch (bo->mem.mem_type) { | |
22fbd538 | 663 | case TTM_PL_VRAM: |
78ad0f7b FJ |
664 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
665 | TTM_PL_FLAG_SYSTEM); | |
22fbd538 | 666 | break; |
6ee73861 | 667 | default: |
78ad0f7b | 668 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
6ee73861 BS |
669 | break; |
670 | } | |
22fbd538 FJ |
671 | |
672 | *pl = nvbo->placement; | |
6ee73861 BS |
673 | } |
674 | ||
675 | ||
49981046 BS |
676 | static int |
677 | nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
678 | { | |
679 | int ret = RING_SPACE(chan, 2); | |
680 | if (ret == 0) { | |
681 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
00fc6f6f | 682 | OUT_RING (chan, handle & 0x0000ffff); |
49981046 BS |
683 | FIRE_RING (chan); |
684 | } | |
685 | return ret; | |
686 | } | |
687 | ||
c6b7e895 BS |
688 | static int |
689 | nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
690 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
691 | { | |
be83cd4e | 692 | struct nvkm_mem *node = old_mem->mm_node; |
c6b7e895 BS |
693 | int ret = RING_SPACE(chan, 10); |
694 | if (ret == 0) { | |
6d597027 | 695 | BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); |
c6b7e895 BS |
696 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); |
697 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); | |
698 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); | |
699 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); | |
700 | OUT_RING (chan, PAGE_SIZE); | |
701 | OUT_RING (chan, PAGE_SIZE); | |
702 | OUT_RING (chan, PAGE_SIZE); | |
703 | OUT_RING (chan, new_mem->num_pages); | |
6d597027 | 704 | BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); |
c6b7e895 BS |
705 | } |
706 | return ret; | |
707 | } | |
708 | ||
d1b167e1 BS |
709 | static int |
710 | nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
711 | { | |
712 | int ret = RING_SPACE(chan, 2); | |
713 | if (ret == 0) { | |
714 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
715 | OUT_RING (chan, handle); | |
716 | } | |
717 | return ret; | |
718 | } | |
719 | ||
1a46098e BS |
720 | static int |
721 | nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
722 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
723 | { | |
be83cd4e | 724 | struct nvkm_mem *node = old_mem->mm_node; |
1a46098e BS |
725 | u64 src_offset = node->vma[0].offset; |
726 | u64 dst_offset = node->vma[1].offset; | |
727 | u32 page_count = new_mem->num_pages; | |
728 | int ret; | |
729 | ||
730 | page_count = new_mem->num_pages; | |
731 | while (page_count) { | |
732 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
733 | ||
734 | ret = RING_SPACE(chan, 11); | |
735 | if (ret) | |
736 | return ret; | |
737 | ||
738 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); | |
739 | OUT_RING (chan, upper_32_bits(src_offset)); | |
740 | OUT_RING (chan, lower_32_bits(src_offset)); | |
741 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
742 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
743 | OUT_RING (chan, PAGE_SIZE); | |
744 | OUT_RING (chan, PAGE_SIZE); | |
745 | OUT_RING (chan, PAGE_SIZE); | |
746 | OUT_RING (chan, line_count); | |
747 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); | |
748 | OUT_RING (chan, 0x00000110); | |
749 | ||
750 | page_count -= line_count; | |
751 | src_offset += (PAGE_SIZE * line_count); | |
752 | dst_offset += (PAGE_SIZE * line_count); | |
753 | } | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
183720b8 BS |
758 | static int |
759 | nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
760 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
761 | { | |
be83cd4e | 762 | struct nvkm_mem *node = old_mem->mm_node; |
d2f96666 BS |
763 | u64 src_offset = node->vma[0].offset; |
764 | u64 dst_offset = node->vma[1].offset; | |
183720b8 BS |
765 | u32 page_count = new_mem->num_pages; |
766 | int ret; | |
767 | ||
183720b8 BS |
768 | page_count = new_mem->num_pages; |
769 | while (page_count) { | |
770 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
771 | ||
772 | ret = RING_SPACE(chan, 12); | |
773 | if (ret) | |
774 | return ret; | |
775 | ||
d1b167e1 | 776 | BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); |
183720b8 BS |
777 | OUT_RING (chan, upper_32_bits(dst_offset)); |
778 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
d1b167e1 | 779 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); |
183720b8 BS |
780 | OUT_RING (chan, upper_32_bits(src_offset)); |
781 | OUT_RING (chan, lower_32_bits(src_offset)); | |
782 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
783 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
784 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
785 | OUT_RING (chan, line_count); | |
d1b167e1 | 786 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); |
183720b8 BS |
787 | OUT_RING (chan, 0x00100110); |
788 | ||
789 | page_count -= line_count; | |
790 | src_offset += (PAGE_SIZE * line_count); | |
791 | dst_offset += (PAGE_SIZE * line_count); | |
792 | } | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
fdf53241 BS |
797 | static int |
798 | nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
799 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
800 | { | |
be83cd4e | 801 | struct nvkm_mem *node = old_mem->mm_node; |
fdf53241 BS |
802 | u64 src_offset = node->vma[0].offset; |
803 | u64 dst_offset = node->vma[1].offset; | |
804 | u32 page_count = new_mem->num_pages; | |
805 | int ret; | |
806 | ||
807 | page_count = new_mem->num_pages; | |
808 | while (page_count) { | |
809 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
810 | ||
811 | ret = RING_SPACE(chan, 11); | |
812 | if (ret) | |
813 | return ret; | |
814 | ||
815 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); | |
816 | OUT_RING (chan, upper_32_bits(src_offset)); | |
817 | OUT_RING (chan, lower_32_bits(src_offset)); | |
818 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
819 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
820 | OUT_RING (chan, PAGE_SIZE); | |
821 | OUT_RING (chan, PAGE_SIZE); | |
822 | OUT_RING (chan, PAGE_SIZE); | |
823 | OUT_RING (chan, line_count); | |
824 | BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); | |
825 | OUT_RING (chan, 0x00000110); | |
826 | ||
827 | page_count -= line_count; | |
828 | src_offset += (PAGE_SIZE * line_count); | |
829 | dst_offset += (PAGE_SIZE * line_count); | |
830 | } | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
5490e5df BS |
835 | static int |
836 | nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
837 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
838 | { | |
be83cd4e | 839 | struct nvkm_mem *node = old_mem->mm_node; |
5490e5df BS |
840 | int ret = RING_SPACE(chan, 7); |
841 | if (ret == 0) { | |
842 | BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); | |
843 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); | |
844 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); | |
845 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); | |
846 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); | |
847 | OUT_RING (chan, 0x00000000 /* COPY */); | |
848 | OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); | |
849 | } | |
850 | return ret; | |
851 | } | |
852 | ||
4c193d25 BS |
853 | static int |
854 | nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
855 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
856 | { | |
be83cd4e | 857 | struct nvkm_mem *node = old_mem->mm_node; |
4c193d25 BS |
858 | int ret = RING_SPACE(chan, 7); |
859 | if (ret == 0) { | |
860 | BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); | |
861 | OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); | |
862 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); | |
863 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); | |
864 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); | |
865 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); | |
866 | OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); | |
867 | } | |
868 | return ret; | |
869 | } | |
870 | ||
d1b167e1 BS |
871 | static int |
872 | nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
873 | { | |
ebb945a9 | 874 | int ret = RING_SPACE(chan, 6); |
d1b167e1 | 875 | if (ret == 0) { |
ebb945a9 BS |
876 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
877 | OUT_RING (chan, handle); | |
878 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); | |
f45f55c4 BS |
879 | OUT_RING (chan, chan->drm->ntfy.handle); |
880 | OUT_RING (chan, chan->vram.handle); | |
881 | OUT_RING (chan, chan->vram.handle); | |
d1b167e1 BS |
882 | } |
883 | ||
884 | return ret; | |
885 | } | |
886 | ||
6ee73861 | 887 | static int |
f1ab0cc9 BS |
888 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
889 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
6ee73861 | 890 | { |
be83cd4e | 891 | struct nvkm_mem *node = old_mem->mm_node; |
f1ab0cc9 | 892 | u64 length = (new_mem->num_pages << PAGE_SHIFT); |
d2f96666 BS |
893 | u64 src_offset = node->vma[0].offset; |
894 | u64 dst_offset = node->vma[1].offset; | |
ce8f7699 | 895 | int src_tiled = !!node->memtype; |
be83cd4e | 896 | int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype; |
6ee73861 BS |
897 | int ret; |
898 | ||
f1ab0cc9 BS |
899 | while (length) { |
900 | u32 amount, stride, height; | |
901 | ||
ce8f7699 ML |
902 | ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); |
903 | if (ret) | |
904 | return ret; | |
905 | ||
5220b3c1 BS |
906 | amount = min(length, (u64)(4 * 1024 * 1024)); |
907 | stride = 16 * 4; | |
f1ab0cc9 BS |
908 | height = amount / stride; |
909 | ||
ce8f7699 | 910 | if (src_tiled) { |
d1b167e1 | 911 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); |
f1ab0cc9 | 912 | OUT_RING (chan, 0); |
5220b3c1 | 913 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
914 | OUT_RING (chan, stride); |
915 | OUT_RING (chan, height); | |
916 | OUT_RING (chan, 1); | |
917 | OUT_RING (chan, 0); | |
918 | OUT_RING (chan, 0); | |
919 | } else { | |
d1b167e1 | 920 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); |
f1ab0cc9 BS |
921 | OUT_RING (chan, 1); |
922 | } | |
ce8f7699 | 923 | if (dst_tiled) { |
d1b167e1 | 924 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); |
f1ab0cc9 | 925 | OUT_RING (chan, 0); |
5220b3c1 | 926 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
927 | OUT_RING (chan, stride); |
928 | OUT_RING (chan, height); | |
929 | OUT_RING (chan, 1); | |
930 | OUT_RING (chan, 0); | |
931 | OUT_RING (chan, 0); | |
932 | } else { | |
d1b167e1 | 933 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); |
f1ab0cc9 BS |
934 | OUT_RING (chan, 1); |
935 | } | |
936 | ||
d1b167e1 | 937 | BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); |
f1ab0cc9 BS |
938 | OUT_RING (chan, upper_32_bits(src_offset)); |
939 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
d1b167e1 | 940 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); |
f1ab0cc9 BS |
941 | OUT_RING (chan, lower_32_bits(src_offset)); |
942 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
943 | OUT_RING (chan, stride); | |
944 | OUT_RING (chan, stride); | |
945 | OUT_RING (chan, stride); | |
946 | OUT_RING (chan, height); | |
947 | OUT_RING (chan, 0x00000101); | |
948 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 949 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 BS |
950 | OUT_RING (chan, 0); |
951 | ||
952 | length -= amount; | |
953 | src_offset += amount; | |
954 | dst_offset += amount; | |
6ee73861 BS |
955 | } |
956 | ||
f1ab0cc9 BS |
957 | return 0; |
958 | } | |
959 | ||
d1b167e1 BS |
960 | static int |
961 | nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
962 | { | |
ebb945a9 | 963 | int ret = RING_SPACE(chan, 4); |
d1b167e1 | 964 | if (ret == 0) { |
ebb945a9 BS |
965 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
966 | OUT_RING (chan, handle); | |
967 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); | |
f45f55c4 | 968 | OUT_RING (chan, chan->drm->ntfy.handle); |
d1b167e1 BS |
969 | } |
970 | ||
971 | return ret; | |
972 | } | |
973 | ||
a6704788 BS |
974 | static inline uint32_t |
975 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, | |
976 | struct nouveau_channel *chan, struct ttm_mem_reg *mem) | |
977 | { | |
978 | if (mem->mem_type == TTM_PL_TT) | |
ebb945a9 | 979 | return NvDmaTT; |
f45f55c4 | 980 | return chan->vram.handle; |
a6704788 BS |
981 | } |
982 | ||
f1ab0cc9 BS |
983 | static int |
984 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
985 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
986 | { | |
d961db75 BS |
987 | u32 src_offset = old_mem->start << PAGE_SHIFT; |
988 | u32 dst_offset = new_mem->start << PAGE_SHIFT; | |
f1ab0cc9 BS |
989 | u32 page_count = new_mem->num_pages; |
990 | int ret; | |
991 | ||
992 | ret = RING_SPACE(chan, 3); | |
993 | if (ret) | |
994 | return ret; | |
995 | ||
d1b167e1 | 996 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); |
f1ab0cc9 BS |
997 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); |
998 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
999 | ||
6ee73861 BS |
1000 | page_count = new_mem->num_pages; |
1001 | while (page_count) { | |
1002 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
1003 | ||
6ee73861 BS |
1004 | ret = RING_SPACE(chan, 11); |
1005 | if (ret) | |
1006 | return ret; | |
f1ab0cc9 | 1007 | |
d1b167e1 | 1008 | BEGIN_NV04(chan, NvSubCopy, |
6ee73861 | 1009 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); |
f1ab0cc9 BS |
1010 | OUT_RING (chan, src_offset); |
1011 | OUT_RING (chan, dst_offset); | |
1012 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
1013 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
1014 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
1015 | OUT_RING (chan, line_count); | |
1016 | OUT_RING (chan, 0x00000101); | |
1017 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 1018 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 | 1019 | OUT_RING (chan, 0); |
6ee73861 BS |
1020 | |
1021 | page_count -= line_count; | |
1022 | src_offset += (PAGE_SIZE * line_count); | |
1023 | dst_offset += (PAGE_SIZE * line_count); | |
1024 | } | |
1025 | ||
f1ab0cc9 BS |
1026 | return 0; |
1027 | } | |
1028 | ||
d2f96666 | 1029 | static int |
3c57d85d BS |
1030 | nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, |
1031 | struct ttm_mem_reg *mem) | |
d2f96666 | 1032 | { |
be83cd4e BS |
1033 | struct nvkm_mem *old_node = bo->mem.mm_node; |
1034 | struct nvkm_mem *new_node = mem->mm_node; | |
3c57d85d | 1035 | u64 size = (u64)mem->num_pages << PAGE_SHIFT; |
d2f96666 BS |
1036 | int ret; |
1037 | ||
be83cd4e BS |
1038 | ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift, |
1039 | NV_MEM_ACCESS_RW, &old_node->vma[0]); | |
d2f96666 BS |
1040 | if (ret) |
1041 | return ret; | |
1042 | ||
be83cd4e BS |
1043 | ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift, |
1044 | NV_MEM_ACCESS_RW, &old_node->vma[1]); | |
3c57d85d | 1045 | if (ret) { |
be83cd4e | 1046 | nvkm_vm_put(&old_node->vma[0]); |
3c57d85d BS |
1047 | return ret; |
1048 | } | |
1049 | ||
be83cd4e BS |
1050 | nvkm_vm_map(&old_node->vma[0], old_node); |
1051 | nvkm_vm_map(&old_node->vma[1], new_node); | |
d2f96666 BS |
1052 | return 0; |
1053 | } | |
1054 | ||
f1ab0cc9 BS |
1055 | static int |
1056 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |
97a875cb | 1057 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
f1ab0cc9 | 1058 | { |
ebb945a9 | 1059 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1934a2ad | 1060 | struct nouveau_channel *chan = drm->ttm.chan; |
a01ca78c | 1061 | struct nouveau_cli *cli = (void *)chan->user.client; |
35b8141b | 1062 | struct nouveau_fence *fence; |
f1ab0cc9 BS |
1063 | int ret; |
1064 | ||
d2f96666 | 1065 | /* create temporary vmas for the transfer and attach them to the |
be83cd4e | 1066 | * old nvkm_mem node, these will get cleaned up after ttm has |
d2f96666 | 1067 | * destroyed the ttm_mem_reg |
3425df48 | 1068 | */ |
967e7bde | 1069 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
3c57d85d | 1070 | ret = nouveau_bo_move_prep(drm, bo, new_mem); |
d2f96666 | 1071 | if (ret) |
3c57d85d | 1072 | return ret; |
3425df48 BS |
1073 | } |
1074 | ||
0ad72863 | 1075 | mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); |
e3be4c23 | 1076 | ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); |
6a6b73f2 | 1077 | if (ret == 0) { |
35b8141b BS |
1078 | ret = drm->ttm.move(chan, bo, &bo->mem, new_mem); |
1079 | if (ret == 0) { | |
1080 | ret = nouveau_fence_new(chan, false, &fence); | |
1081 | if (ret == 0) { | |
f2c24b83 ML |
1082 | ret = ttm_bo_move_accel_cleanup(bo, |
1083 | &fence->base, | |
35b8141b BS |
1084 | evict, |
1085 | no_wait_gpu, | |
1086 | new_mem); | |
1087 | nouveau_fence_unref(&fence); | |
1088 | } | |
1089 | } | |
6a6b73f2 | 1090 | } |
0ad72863 | 1091 | mutex_unlock(&cli->mutex); |
6a6b73f2 | 1092 | return ret; |
6ee73861 BS |
1093 | } |
1094 | ||
d1b167e1 | 1095 | void |
49981046 | 1096 | nouveau_bo_move_init(struct nouveau_drm *drm) |
d1b167e1 | 1097 | { |
d1b167e1 BS |
1098 | static const struct { |
1099 | const char *name; | |
1a46098e | 1100 | int engine; |
315a8b2e | 1101 | s32 oclass; |
d1b167e1 BS |
1102 | int (*exec)(struct nouveau_channel *, |
1103 | struct ttm_buffer_object *, | |
1104 | struct ttm_mem_reg *, struct ttm_mem_reg *); | |
1105 | int (*init)(struct nouveau_channel *, u32 handle); | |
1106 | } _methods[] = { | |
990b4547 BS |
1107 | { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
1108 | { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, | |
00fc6f6f | 1109 | { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
49981046 | 1110 | { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, |
1a46098e BS |
1111 | { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, |
1112 | { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, | |
1113 | { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, | |
1114 | { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, | |
1115 | { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, | |
1116 | { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, | |
1117 | { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, | |
5490e5df | 1118 | {}, |
1a46098e | 1119 | { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, |
d1b167e1 BS |
1120 | }, *mthd = _methods; |
1121 | const char *name = "CPU"; | |
1122 | int ret; | |
1123 | ||
1124 | do { | |
49981046 | 1125 | struct nouveau_channel *chan; |
ebb945a9 | 1126 | |
00fc6f6f | 1127 | if (mthd->engine) |
49981046 BS |
1128 | chan = drm->cechan; |
1129 | else | |
1130 | chan = drm->channel; | |
1131 | if (chan == NULL) | |
1132 | continue; | |
1133 | ||
a01ca78c | 1134 | ret = nvif_object_init(&chan->user, |
0ad72863 BS |
1135 | mthd->oclass | (mthd->engine << 16), |
1136 | mthd->oclass, NULL, 0, | |
1137 | &drm->ttm.copy); | |
d1b167e1 | 1138 | if (ret == 0) { |
0ad72863 | 1139 | ret = mthd->init(chan, drm->ttm.copy.handle); |
ebb945a9 | 1140 | if (ret) { |
0ad72863 | 1141 | nvif_object_fini(&drm->ttm.copy); |
ebb945a9 | 1142 | continue; |
d1b167e1 | 1143 | } |
ebb945a9 BS |
1144 | |
1145 | drm->ttm.move = mthd->exec; | |
1bb3f6a2 | 1146 | drm->ttm.chan = chan; |
ebb945a9 BS |
1147 | name = mthd->name; |
1148 | break; | |
d1b167e1 BS |
1149 | } |
1150 | } while ((++mthd)->exec); | |
1151 | ||
ebb945a9 | 1152 | NV_INFO(drm, "MM: using %s for buffer copies\n", name); |
d1b167e1 BS |
1153 | } |
1154 | ||
6ee73861 BS |
1155 | static int |
1156 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
97a875cb | 1157 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
6ee73861 | 1158 | { |
f1217ed0 CK |
1159 | struct ttm_place placement_memtype = { |
1160 | .fpfn = 0, | |
1161 | .lpfn = 0, | |
1162 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING | |
1163 | }; | |
6ee73861 BS |
1164 | struct ttm_placement placement; |
1165 | struct ttm_mem_reg tmp_mem; | |
1166 | int ret; | |
1167 | ||
6ee73861 | 1168 | placement.num_placement = placement.num_busy_placement = 1; |
77e2b5ed | 1169 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
1170 | |
1171 | tmp_mem = *new_mem; | |
1172 | tmp_mem.mm_node = NULL; | |
97a875cb | 1173 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); |
6ee73861 BS |
1174 | if (ret) |
1175 | return ret; | |
1176 | ||
1177 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); | |
1178 | if (ret) | |
1179 | goto out; | |
1180 | ||
97a875cb | 1181 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
1182 | if (ret) |
1183 | goto out; | |
1184 | ||
97a875cb | 1185 | ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); |
6ee73861 | 1186 | out: |
42311ff9 | 1187 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
1188 | return ret; |
1189 | } | |
1190 | ||
1191 | static int | |
1192 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
97a875cb | 1193 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
6ee73861 | 1194 | { |
f1217ed0 CK |
1195 | struct ttm_place placement_memtype = { |
1196 | .fpfn = 0, | |
1197 | .lpfn = 0, | |
1198 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING | |
1199 | }; | |
6ee73861 BS |
1200 | struct ttm_placement placement; |
1201 | struct ttm_mem_reg tmp_mem; | |
1202 | int ret; | |
1203 | ||
6ee73861 | 1204 | placement.num_placement = placement.num_busy_placement = 1; |
77e2b5ed | 1205 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
1206 | |
1207 | tmp_mem = *new_mem; | |
1208 | tmp_mem.mm_node = NULL; | |
97a875cb | 1209 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); |
6ee73861 BS |
1210 | if (ret) |
1211 | return ret; | |
1212 | ||
97a875cb | 1213 | ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
1214 | if (ret) |
1215 | goto out; | |
1216 | ||
97a875cb | 1217 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem); |
6ee73861 BS |
1218 | if (ret) |
1219 | goto out; | |
1220 | ||
1221 | out: | |
42311ff9 | 1222 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
1223 | return ret; |
1224 | } | |
1225 | ||
a4154bbf BS |
1226 | static void |
1227 | nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) | |
1228 | { | |
a4154bbf | 1229 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
be83cd4e | 1230 | struct nvkm_vma *vma; |
fd2871af | 1231 | |
9f1feed2 BS |
1232 | /* ttm can now (stupidly) pass the driver bos it didn't create... */ |
1233 | if (bo->destroy != nouveau_bo_del_ttm) | |
1234 | return; | |
1235 | ||
fd2871af | 1236 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
2e2cfbe6 BS |
1237 | if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && |
1238 | (new_mem->mem_type == TTM_PL_VRAM || | |
5ce3bf3c | 1239 | nvbo->page_shift != vma->vm->mmu->lpg_shift)) { |
be83cd4e | 1240 | nvkm_vm_map(vma, new_mem->mm_node); |
fd2871af | 1241 | } else { |
be83cd4e | 1242 | nvkm_vm_unmap(vma); |
fd2871af | 1243 | } |
a4154bbf BS |
1244 | } |
1245 | } | |
1246 | ||
6ee73861 | 1247 | static int |
a0af9add | 1248 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
ebb945a9 | 1249 | struct nouveau_drm_tile **new_tile) |
6ee73861 | 1250 | { |
ebb945a9 BS |
1251 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1252 | struct drm_device *dev = drm->dev; | |
a0af9add | 1253 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
a4154bbf | 1254 | u64 offset = new_mem->start << PAGE_SHIFT; |
6ee73861 | 1255 | |
a4154bbf BS |
1256 | *new_tile = NULL; |
1257 | if (new_mem->mem_type != TTM_PL_VRAM) | |
a0af9add | 1258 | return 0; |
a0af9add | 1259 | |
967e7bde | 1260 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { |
bc9e7b9a | 1261 | *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size, |
a5cf68b0 FJ |
1262 | nvbo->tile_mode, |
1263 | nvbo->tile_flags); | |
6ee73861 BS |
1264 | } |
1265 | ||
a0af9add FJ |
1266 | return 0; |
1267 | } | |
1268 | ||
1269 | static void | |
1270 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
ebb945a9 BS |
1271 | struct nouveau_drm_tile *new_tile, |
1272 | struct nouveau_drm_tile **old_tile) | |
a0af9add | 1273 | { |
ebb945a9 BS |
1274 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1275 | struct drm_device *dev = drm->dev; | |
f2c24b83 | 1276 | struct fence *fence = reservation_object_get_excl(bo->resv); |
a0af9add | 1277 | |
f2c24b83 | 1278 | nv10_bo_put_tile_region(dev, *old_tile, fence); |
a4154bbf | 1279 | *old_tile = new_tile; |
a0af9add FJ |
1280 | } |
1281 | ||
1282 | static int | |
1283 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
97a875cb | 1284 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
a0af9add | 1285 | { |
ebb945a9 | 1286 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
a0af9add FJ |
1287 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1288 | struct ttm_mem_reg *old_mem = &bo->mem; | |
ebb945a9 | 1289 | struct nouveau_drm_tile *new_tile = NULL; |
a0af9add FJ |
1290 | int ret = 0; |
1291 | ||
5be5a15a AC |
1292 | if (nvbo->pin_refcnt) |
1293 | NV_WARN(drm, "Moving pinned object %p!\n", nvbo); | |
1294 | ||
967e7bde | 1295 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
a4154bbf BS |
1296 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); |
1297 | if (ret) | |
1298 | return ret; | |
1299 | } | |
a0af9add | 1300 | |
a0af9add | 1301 | /* Fake bo copy. */ |
6ee73861 BS |
1302 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
1303 | BUG_ON(bo->mem.mm_node != NULL); | |
1304 | bo->mem = *new_mem; | |
1305 | new_mem->mm_node = NULL; | |
a0af9add | 1306 | goto out; |
6ee73861 BS |
1307 | } |
1308 | ||
a0af9add | 1309 | /* Hardware assisted copy. */ |
cef9e99e BS |
1310 | if (drm->ttm.move) { |
1311 | if (new_mem->mem_type == TTM_PL_SYSTEM) | |
1312 | ret = nouveau_bo_move_flipd(bo, evict, intr, | |
1313 | no_wait_gpu, new_mem); | |
1314 | else if (old_mem->mem_type == TTM_PL_SYSTEM) | |
1315 | ret = nouveau_bo_move_flips(bo, evict, intr, | |
1316 | no_wait_gpu, new_mem); | |
1317 | else | |
1318 | ret = nouveau_bo_move_m2mf(bo, evict, intr, | |
1319 | no_wait_gpu, new_mem); | |
1320 | if (!ret) | |
1321 | goto out; | |
1322 | } | |
a0af9add FJ |
1323 | |
1324 | /* Fallback to software copy. */ | |
cef9e99e | 1325 | ret = ttm_bo_wait(bo, true, intr, no_wait_gpu); |
cef9e99e BS |
1326 | if (ret == 0) |
1327 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); | |
a0af9add FJ |
1328 | |
1329 | out: | |
967e7bde | 1330 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
a4154bbf BS |
1331 | if (ret) |
1332 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
1333 | else | |
1334 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
1335 | } | |
a0af9add FJ |
1336 | |
1337 | return ret; | |
6ee73861 BS |
1338 | } |
1339 | ||
1340 | static int | |
1341 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
1342 | { | |
acb46527 DH |
1343 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1344 | ||
55fb74ad | 1345 | return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp); |
6ee73861 BS |
1346 | } |
1347 | ||
f32f02fd JG |
1348 | static int |
1349 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
1350 | { | |
1351 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
ebb945a9 | 1352 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
7e8820fe | 1353 | struct nvkm_device *device = nvxx_device(&drm->device); |
be83cd4e | 1354 | struct nvkm_mem *node = mem->mm_node; |
f869ef88 | 1355 | int ret; |
f32f02fd JG |
1356 | |
1357 | mem->bus.addr = NULL; | |
1358 | mem->bus.offset = 0; | |
1359 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
1360 | mem->bus.base = 0; | |
1361 | mem->bus.is_iomem = false; | |
1362 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
1363 | return -EINVAL; | |
1364 | switch (mem->mem_type) { | |
1365 | case TTM_PL_SYSTEM: | |
1366 | /* System memory */ | |
1367 | return 0; | |
1368 | case TTM_PL_TT: | |
a7fb8a23 | 1369 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1370 | if (drm->agp.bridge) { |
d961db75 | 1371 | mem->bus.offset = mem->start << PAGE_SHIFT; |
ebb945a9 | 1372 | mem->bus.base = drm->agp.base; |
340b0e7c | 1373 | mem->bus.is_iomem = !drm->agp.cma; |
f32f02fd JG |
1374 | } |
1375 | #endif | |
967e7bde | 1376 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype) |
a5540906 ML |
1377 | /* untiled */ |
1378 | break; | |
1379 | /* fallthrough, tiled memory */ | |
f32f02fd | 1380 | case TTM_PL_VRAM: |
3863c9bc | 1381 | mem->bus.offset = mem->start << PAGE_SHIFT; |
7e8820fe | 1382 | mem->bus.base = device->func->resource_addr(device, 1); |
3863c9bc | 1383 | mem->bus.is_iomem = true; |
967e7bde | 1384 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
be83cd4e | 1385 | struct nvkm_bar *bar = nvxx_bar(&drm->device); |
d8e83994 BS |
1386 | int page_shift = 12; |
1387 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI) | |
1388 | page_shift = node->page_shift; | |
8984e046 | 1389 | |
32932281 BS |
1390 | ret = nvkm_bar_umap(bar, node->size << 12, page_shift, |
1391 | &node->bar_vma); | |
3863c9bc BS |
1392 | if (ret) |
1393 | return ret; | |
f869ef88 | 1394 | |
d8e83994 | 1395 | nvkm_vm_map(&node->bar_vma, node); |
3863c9bc | 1396 | mem->bus.offset = node->bar_vma.offset; |
f869ef88 | 1397 | } |
f32f02fd JG |
1398 | break; |
1399 | default: | |
1400 | return -EINVAL; | |
1401 | } | |
1402 | return 0; | |
1403 | } | |
1404 | ||
1405 | static void | |
1406 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
1407 | { | |
be83cd4e | 1408 | struct nvkm_mem *node = mem->mm_node; |
f869ef88 | 1409 | |
d5f42394 | 1410 | if (!node->bar_vma.node) |
f869ef88 BS |
1411 | return; |
1412 | ||
32932281 BS |
1413 | nvkm_vm_unmap(&node->bar_vma); |
1414 | nvkm_vm_put(&node->bar_vma); | |
f32f02fd JG |
1415 | } |
1416 | ||
1417 | static int | |
1418 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |
1419 | { | |
ebb945a9 | 1420 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
e1429b4c | 1421 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
7e8820fe BS |
1422 | struct nvkm_device *device = nvxx_device(&drm->device); |
1423 | u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; | |
f1217ed0 | 1424 | int i, ret; |
e1429b4c BS |
1425 | |
1426 | /* as long as the bo isn't in vram, and isn't tiled, we've got | |
1427 | * nothing to do here. | |
1428 | */ | |
1429 | if (bo->mem.mem_type != TTM_PL_VRAM) { | |
967e7bde | 1430 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || |
f13b3263 | 1431 | !nouveau_bo_tile_layout(nvbo)) |
e1429b4c | 1432 | return 0; |
a5540906 ML |
1433 | |
1434 | if (bo->mem.mem_type == TTM_PL_SYSTEM) { | |
1435 | nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); | |
1436 | ||
1437 | ret = nouveau_bo_validate(nvbo, false, false); | |
1438 | if (ret) | |
1439 | return ret; | |
1440 | } | |
1441 | return 0; | |
e1429b4c BS |
1442 | } |
1443 | ||
1444 | /* make sure bo is in mappable vram */ | |
967e7bde | 1445 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA || |
a5540906 | 1446 | bo->mem.start + bo->mem.num_pages < mappable) |
e1429b4c BS |
1447 | return 0; |
1448 | ||
f1217ed0 CK |
1449 | for (i = 0; i < nvbo->placement.num_placement; ++i) { |
1450 | nvbo->placements[i].fpfn = 0; | |
1451 | nvbo->placements[i].lpfn = mappable; | |
1452 | } | |
1453 | ||
1454 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { | |
1455 | nvbo->busy_placements[i].fpfn = 0; | |
1456 | nvbo->busy_placements[i].lpfn = mappable; | |
1457 | } | |
e1429b4c | 1458 | |
c284815d | 1459 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); |
97a875cb | 1460 | return nouveau_bo_validate(nvbo, false, false); |
f32f02fd JG |
1461 | } |
1462 | ||
3230cfc3 KRW |
1463 | static int |
1464 | nouveau_ttm_tt_populate(struct ttm_tt *ttm) | |
1465 | { | |
8e7e7052 | 1466 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1467 | struct nouveau_drm *drm; |
be83cd4e | 1468 | struct nvkm_device *device; |
3230cfc3 | 1469 | struct drm_device *dev; |
fd1496a0 | 1470 | struct device *pdev; |
3230cfc3 KRW |
1471 | unsigned i; |
1472 | int r; | |
22b33e8e | 1473 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
3230cfc3 KRW |
1474 | |
1475 | if (ttm->state != tt_unpopulated) | |
1476 | return 0; | |
1477 | ||
22b33e8e DA |
1478 | if (slave && ttm->sg) { |
1479 | /* make userspace faulting work */ | |
1480 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
1481 | ttm_dma->dma_address, ttm->num_pages); | |
1482 | ttm->state = tt_unbound; | |
1483 | return 0; | |
1484 | } | |
1485 | ||
ebb945a9 | 1486 | drm = nouveau_bdev(ttm->bdev); |
989aa5b7 | 1487 | device = nvxx_device(&drm->device); |
ebb945a9 | 1488 | dev = drm->dev; |
26c9e8ef | 1489 | pdev = device->dev; |
3230cfc3 | 1490 | |
c3a0c771 AC |
1491 | /* |
1492 | * Objects matching this condition have been marked as force_coherent, | |
1493 | * so use the DMA API for them. | |
1494 | */ | |
26c9e8ef | 1495 | if (!nvxx_device(&drm->device)->func->cpu_coherent && |
c3a0c771 AC |
1496 | ttm->caching_state == tt_uncached) |
1497 | return ttm_dma_populate(ttm_dma, dev->dev); | |
1498 | ||
a7fb8a23 | 1499 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1500 | if (drm->agp.bridge) { |
dea7e0ac JG |
1501 | return ttm_agp_tt_populate(ttm); |
1502 | } | |
1503 | #endif | |
1504 | ||
9bcd38de | 1505 | #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) |
3230cfc3 | 1506 | if (swiotlb_nr_tbl()) { |
8e7e7052 | 1507 | return ttm_dma_populate((void *)ttm, dev->dev); |
3230cfc3 KRW |
1508 | } |
1509 | #endif | |
1510 | ||
1511 | r = ttm_pool_populate(ttm); | |
1512 | if (r) { | |
1513 | return r; | |
1514 | } | |
1515 | ||
1516 | for (i = 0; i < ttm->num_pages; i++) { | |
fd1496a0 AC |
1517 | dma_addr_t addr; |
1518 | ||
1519 | addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE, | |
1520 | DMA_BIDIRECTIONAL); | |
1521 | ||
1522 | if (dma_mapping_error(pdev, addr)) { | |
4fbbed46 | 1523 | while (i--) { |
fd1496a0 AC |
1524 | dma_unmap_page(pdev, ttm_dma->dma_address[i], |
1525 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
8e7e7052 | 1526 | ttm_dma->dma_address[i] = 0; |
3230cfc3 KRW |
1527 | } |
1528 | ttm_pool_unpopulate(ttm); | |
1529 | return -EFAULT; | |
1530 | } | |
fd1496a0 AC |
1531 | |
1532 | ttm_dma->dma_address[i] = addr; | |
3230cfc3 KRW |
1533 | } |
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | static void | |
1538 | nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
1539 | { | |
8e7e7052 | 1540 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1541 | struct nouveau_drm *drm; |
be83cd4e | 1542 | struct nvkm_device *device; |
3230cfc3 | 1543 | struct drm_device *dev; |
fd1496a0 | 1544 | struct device *pdev; |
3230cfc3 | 1545 | unsigned i; |
22b33e8e DA |
1546 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
1547 | ||
1548 | if (slave) | |
1549 | return; | |
3230cfc3 | 1550 | |
ebb945a9 | 1551 | drm = nouveau_bdev(ttm->bdev); |
989aa5b7 | 1552 | device = nvxx_device(&drm->device); |
ebb945a9 | 1553 | dev = drm->dev; |
26c9e8ef | 1554 | pdev = device->dev; |
3230cfc3 | 1555 | |
c3a0c771 AC |
1556 | /* |
1557 | * Objects matching this condition have been marked as force_coherent, | |
1558 | * so use the DMA API for them. | |
1559 | */ | |
26c9e8ef | 1560 | if (!nvxx_device(&drm->device)->func->cpu_coherent && |
dcccdc14 | 1561 | ttm->caching_state == tt_uncached) { |
c3a0c771 | 1562 | ttm_dma_unpopulate(ttm_dma, dev->dev); |
dcccdc14 AC |
1563 | return; |
1564 | } | |
c3a0c771 | 1565 | |
a7fb8a23 | 1566 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1567 | if (drm->agp.bridge) { |
dea7e0ac JG |
1568 | ttm_agp_tt_unpopulate(ttm); |
1569 | return; | |
1570 | } | |
1571 | #endif | |
1572 | ||
9bcd38de | 1573 | #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) |
3230cfc3 | 1574 | if (swiotlb_nr_tbl()) { |
8e7e7052 | 1575 | ttm_dma_unpopulate((void *)ttm, dev->dev); |
3230cfc3 KRW |
1576 | return; |
1577 | } | |
1578 | #endif | |
1579 | ||
1580 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 | 1581 | if (ttm_dma->dma_address[i]) { |
fd1496a0 AC |
1582 | dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE, |
1583 | DMA_BIDIRECTIONAL); | |
3230cfc3 KRW |
1584 | } |
1585 | } | |
1586 | ||
1587 | ttm_pool_unpopulate(ttm); | |
1588 | } | |
1589 | ||
875ac34a | 1590 | void |
809e9447 | 1591 | nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) |
875ac34a | 1592 | { |
29ba89b2 | 1593 | struct reservation_object *resv = nvbo->bo.resv; |
bdaf7ddf | 1594 | |
809e9447 ML |
1595 | if (exclusive) |
1596 | reservation_object_add_excl_fence(resv, &fence->base); | |
1597 | else if (fence) | |
1598 | reservation_object_add_shared_fence(resv, &fence->base); | |
875ac34a BS |
1599 | } |
1600 | ||
6ee73861 | 1601 | struct ttm_bo_driver nouveau_bo_driver = { |
649bf3ca | 1602 | .ttm_tt_create = &nouveau_ttm_tt_create, |
3230cfc3 KRW |
1603 | .ttm_tt_populate = &nouveau_ttm_tt_populate, |
1604 | .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, | |
6ee73861 BS |
1605 | .invalidate_caches = nouveau_bo_invalidate_caches, |
1606 | .init_mem_type = nouveau_bo_init_mem_type, | |
1607 | .evict_flags = nouveau_bo_evict_flags, | |
a4154bbf | 1608 | .move_notify = nouveau_bo_move_ntfy, |
6ee73861 BS |
1609 | .move = nouveau_bo_move, |
1610 | .verify_access = nouveau_bo_verify_access, | |
f32f02fd JG |
1611 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
1612 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, | |
1613 | .io_mem_free = &nouveau_ttm_io_mem_free, | |
6ee73861 BS |
1614 | }; |
1615 | ||
be83cd4e BS |
1616 | struct nvkm_vma * |
1617 | nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm) | |
fd2871af | 1618 | { |
be83cd4e | 1619 | struct nvkm_vma *vma; |
fd2871af BS |
1620 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
1621 | if (vma->vm == vm) | |
1622 | return vma; | |
1623 | } | |
1624 | ||
1625 | return NULL; | |
1626 | } | |
1627 | ||
1628 | int | |
be83cd4e BS |
1629 | nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm, |
1630 | struct nvkm_vma *vma) | |
fd2871af BS |
1631 | { |
1632 | const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT; | |
fd2871af BS |
1633 | int ret; |
1634 | ||
be83cd4e | 1635 | ret = nvkm_vm_get(vm, size, nvbo->page_shift, |
fd2871af BS |
1636 | NV_MEM_ACCESS_RW, vma); |
1637 | if (ret) | |
1638 | return ret; | |
1639 | ||
2e2cfbe6 BS |
1640 | if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM && |
1641 | (nvbo->bo.mem.mem_type == TTM_PL_VRAM || | |
5ce3bf3c | 1642 | nvbo->page_shift != vma->vm->mmu->lpg_shift)) |
be83cd4e | 1643 | nvkm_vm_map(vma, nvbo->bo.mem.mm_node); |
fd2871af BS |
1644 | |
1645 | list_add_tail(&vma->head, &nvbo->vma_list); | |
2fd3db6f | 1646 | vma->refcount = 1; |
fd2871af BS |
1647 | return 0; |
1648 | } | |
1649 | ||
1650 | void | |
be83cd4e | 1651 | nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma) |
fd2871af BS |
1652 | { |
1653 | if (vma->node) { | |
c4c7044f | 1654 | if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) |
be83cd4e BS |
1655 | nvkm_vm_unmap(vma); |
1656 | nvkm_vm_put(vma); | |
fd2871af BS |
1657 | list_del(&vma->head); |
1658 | } | |
1659 | } |