Commit | Line | Data |
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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
fdb751ef | 30 | #include <linux/dma-mapping.h> |
3e2b756b | 31 | #include <linux/swiotlb.h> |
6ee73861 | 32 | |
4dc28134 | 33 | #include "nouveau_drv.h" |
6ee73861 | 34 | #include "nouveau_dma.h" |
d375e7d5 | 35 | #include "nouveau_fence.h" |
6ee73861 | 36 | |
ebb945a9 BS |
37 | #include "nouveau_bo.h" |
38 | #include "nouveau_ttm.h" | |
39 | #include "nouveau_gem.h" | |
9ce523cc | 40 | #include "nouveau_mem.h" |
24e8375b | 41 | #include "nouveau_vmm.h" |
a510604d | 42 | |
d7722134 BS |
43 | #include <nvif/class.h> |
44 | #include <nvif/if500b.h> | |
45 | #include <nvif/if900b.h> | |
46 | ||
bc9e7b9a BS |
47 | /* |
48 | * NV10-NV40 tiling helpers | |
49 | */ | |
50 | ||
51 | static void | |
ebb945a9 BS |
52 | nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, |
53 | u32 addr, u32 size, u32 pitch, u32 flags) | |
bc9e7b9a | 54 | { |
77145f1c | 55 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 56 | int i = reg - drm->tile.reg; |
359088d5 | 57 | struct nvkm_fb *fb = nvxx_fb(&drm->client.device); |
b1e4553c | 58 | struct nvkm_fb_tile *tile = &fb->tile.region[i]; |
bc9e7b9a | 59 | |
ebb945a9 | 60 | nouveau_fence_unref(®->fence); |
bc9e7b9a BS |
61 | |
62 | if (tile->pitch) | |
03c8952f | 63 | nvkm_fb_tile_fini(fb, i, tile); |
bc9e7b9a BS |
64 | |
65 | if (pitch) | |
03c8952f | 66 | nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); |
bc9e7b9a | 67 | |
03c8952f | 68 | nvkm_fb_tile_prog(fb, i, tile); |
bc9e7b9a BS |
69 | } |
70 | ||
ebb945a9 | 71 | static struct nouveau_drm_tile * |
bc9e7b9a BS |
72 | nv10_bo_get_tile_region(struct drm_device *dev, int i) |
73 | { | |
77145f1c | 74 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 75 | struct nouveau_drm_tile *tile = &drm->tile.reg[i]; |
bc9e7b9a | 76 | |
ebb945a9 | 77 | spin_lock(&drm->tile.lock); |
bc9e7b9a BS |
78 | |
79 | if (!tile->used && | |
80 | (!tile->fence || nouveau_fence_done(tile->fence))) | |
81 | tile->used = true; | |
82 | else | |
83 | tile = NULL; | |
84 | ||
ebb945a9 | 85 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
86 | return tile; |
87 | } | |
88 | ||
89 | static void | |
ebb945a9 | 90 | nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, |
f54d1867 | 91 | struct dma_fence *fence) |
bc9e7b9a | 92 | { |
77145f1c | 93 | struct nouveau_drm *drm = nouveau_drm(dev); |
bc9e7b9a BS |
94 | |
95 | if (tile) { | |
ebb945a9 | 96 | spin_lock(&drm->tile.lock); |
f54d1867 | 97 | tile->fence = (struct nouveau_fence *)dma_fence_get(fence); |
bc9e7b9a | 98 | tile->used = false; |
ebb945a9 | 99 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
100 | } |
101 | } | |
102 | ||
ebb945a9 BS |
103 | static struct nouveau_drm_tile * |
104 | nv10_bo_set_tiling(struct drm_device *dev, u32 addr, | |
7760a2e3 | 105 | u32 size, u32 pitch, u32 zeta) |
bc9e7b9a | 106 | { |
77145f1c | 107 | struct nouveau_drm *drm = nouveau_drm(dev); |
1167c6bc | 108 | struct nvkm_fb *fb = nvxx_fb(&drm->client.device); |
ebb945a9 | 109 | struct nouveau_drm_tile *tile, *found = NULL; |
bc9e7b9a BS |
110 | int i; |
111 | ||
b1e4553c | 112 | for (i = 0; i < fb->tile.regions; i++) { |
bc9e7b9a BS |
113 | tile = nv10_bo_get_tile_region(dev, i); |
114 | ||
115 | if (pitch && !found) { | |
116 | found = tile; | |
117 | continue; | |
118 | ||
b1e4553c | 119 | } else if (tile && fb->tile.region[i].pitch) { |
bc9e7b9a BS |
120 | /* Kill an unused tile region. */ |
121 | nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); | |
122 | } | |
123 | ||
124 | nv10_bo_put_tile_region(dev, tile, NULL); | |
125 | } | |
126 | ||
127 | if (found) | |
7760a2e3 | 128 | nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); |
bc9e7b9a BS |
129 | return found; |
130 | } | |
131 | ||
6ee73861 BS |
132 | static void |
133 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
134 | { | |
ebb945a9 BS |
135 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
136 | struct drm_device *dev = drm->dev; | |
6ee73861 BS |
137 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
138 | ||
55fb74ad | 139 | if (unlikely(nvbo->gem.filp)) |
6ee73861 | 140 | DRM_ERROR("bo %p still attached to GEM object\n", bo); |
4f385599 | 141 | WARN_ON(nvbo->pin_refcnt > 0); |
bc9e7b9a | 142 | nv10_bo_put_tile_region(dev, nvbo->tile, NULL); |
6ee73861 BS |
143 | kfree(nvbo); |
144 | } | |
145 | ||
4d8b3d34 BS |
146 | static inline u64 |
147 | roundup_64(u64 x, u32 y) | |
148 | { | |
149 | x += y - 1; | |
150 | do_div(x, y); | |
151 | return x * y; | |
152 | } | |
153 | ||
a0af9add | 154 | static void |
db5c8e29 | 155 | nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, |
4d8b3d34 | 156 | int *align, u64 *size) |
a0af9add | 157 | { |
ebb945a9 | 158 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
1167c6bc | 159 | struct nvif_device *device = &drm->client.device; |
a0af9add | 160 | |
967e7bde | 161 | if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { |
7760a2e3 | 162 | if (nvbo->mode) { |
967e7bde | 163 | if (device->info.chipset >= 0x40) { |
a0af9add | 164 | *align = 65536; |
7760a2e3 | 165 | *size = roundup_64(*size, 64 * nvbo->mode); |
a0af9add | 166 | |
967e7bde | 167 | } else if (device->info.chipset >= 0x30) { |
a0af9add | 168 | *align = 32768; |
7760a2e3 | 169 | *size = roundup_64(*size, 64 * nvbo->mode); |
a0af9add | 170 | |
967e7bde | 171 | } else if (device->info.chipset >= 0x20) { |
a0af9add | 172 | *align = 16384; |
7760a2e3 | 173 | *size = roundup_64(*size, 64 * nvbo->mode); |
a0af9add | 174 | |
967e7bde | 175 | } else if (device->info.chipset >= 0x10) { |
a0af9add | 176 | *align = 16384; |
7760a2e3 | 177 | *size = roundup_64(*size, 32 * nvbo->mode); |
a0af9add FJ |
178 | } |
179 | } | |
bfd83aca | 180 | } else { |
7760a2e3 BS |
181 | *size = roundup_64(*size, (1 << nvbo->page)); |
182 | *align = max((1 << nvbo->page), *align); | |
a0af9add FJ |
183 | } |
184 | ||
4d8b3d34 | 185 | *size = roundup_64(*size, PAGE_SIZE); |
a0af9add FJ |
186 | } |
187 | ||
6ee73861 | 188 | int |
4d8b3d34 | 189 | nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, |
7375c95b | 190 | uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, |
bb6178b0 | 191 | struct sg_table *sg, struct reservation_object *robj, |
7375c95b | 192 | struct nouveau_bo **pnvbo) |
6ee73861 | 193 | { |
e75c091b | 194 | struct nouveau_drm *drm = cli->drm; |
6ee73861 | 195 | struct nouveau_bo *nvbo; |
a220dd73 | 196 | struct nvif_mmu *mmu = &cli->mmu; |
7dc6a446 | 197 | struct nvif_vmm *vmm = &cli->vmm.vmm; |
57de4ba9 | 198 | size_t acc_size; |
22b33e8e | 199 | int type = ttm_bo_type_device; |
7dc6a446 | 200 | int ret, i, pi = -1; |
0108bc80 | 201 | |
4d8b3d34 BS |
202 | if (!size) { |
203 | NV_WARN(drm, "skipped size %016llx\n", size); | |
0108bc80 ML |
204 | return -EINVAL; |
205 | } | |
22b33e8e DA |
206 | |
207 | if (sg) | |
208 | type = ttm_bo_type_sg; | |
6ee73861 BS |
209 | |
210 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
211 | if (!nvbo) | |
212 | return -ENOMEM; | |
213 | INIT_LIST_HEAD(&nvbo->head); | |
214 | INIT_LIST_HEAD(&nvbo->entry); | |
fd2871af | 215 | INIT_LIST_HEAD(&nvbo->vma_list); |
ebb945a9 | 216 | nvbo->bo.bdev = &drm->ttm.bdev; |
bab7cc18 | 217 | nvbo->cli = cli; |
6ee73861 | 218 | |
acb16cfa BS |
219 | /* This is confusing, and doesn't actually mean we want an uncached |
220 | * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated | |
221 | * into in nouveau_gem_new(). | |
222 | */ | |
223 | if (flags & TTM_PL_FLAG_UNCACHED) { | |
224 | /* Determine if we can get a cache-coherent map, forcing | |
225 | * uncached mapping if we can't. | |
226 | */ | |
74a39954 | 227 | if (!nouveau_drm_use_coherent_gpu_mapping(drm)) |
acb16cfa BS |
228 | nvbo->force_coherent = true; |
229 | } | |
c3a0c771 | 230 | |
7760a2e3 BS |
231 | if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { |
232 | nvbo->kind = (tile_flags & 0x0000ff00) >> 8; | |
a220dd73 BS |
233 | if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { |
234 | kfree(nvbo); | |
235 | return -EINVAL; | |
236 | } | |
237 | ||
238 | nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; | |
7760a2e3 BS |
239 | } else |
240 | if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { | |
241 | nvbo->kind = (tile_flags & 0x00007f00) >> 8; | |
242 | nvbo->comp = (tile_flags & 0x00030000) >> 16; | |
a220dd73 BS |
243 | if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { |
244 | kfree(nvbo); | |
245 | return -EINVAL; | |
246 | } | |
7760a2e3 BS |
247 | } else { |
248 | nvbo->zeta = (tile_flags & 0x00000007); | |
249 | } | |
250 | nvbo->mode = tile_mode; | |
251 | nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); | |
252 | ||
7dc6a446 BS |
253 | /* Determine the desirable target GPU page size for the buffer. */ |
254 | for (i = 0; i < vmm->page_nr; i++) { | |
255 | /* Because we cannot currently allow VMM maps to fail | |
256 | * during buffer migration, we need to determine page | |
257 | * size for the buffer up-front, and pre-allocate its | |
258 | * page tables. | |
259 | * | |
260 | * Skip page sizes that can't support needed domains. | |
261 | */ | |
262 | if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && | |
263 | (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) | |
264 | continue; | |
f29f18eb BS |
265 | if ((flags & TTM_PL_FLAG_TT) && |
266 | (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) | |
7dc6a446 BS |
267 | continue; |
268 | ||
269 | /* Select this page size if it's the first that supports | |
270 | * the potential memory domains, or when it's compatible | |
271 | * with the requested compression settings. | |
272 | */ | |
273 | if (pi < 0 || !nvbo->comp || vmm->page[i].comp) | |
274 | pi = i; | |
275 | ||
276 | /* Stop once the buffer is larger than the current page size. */ | |
277 | if (size >= 1ULL << vmm->page[i].shift) | |
278 | break; | |
279 | } | |
280 | ||
281 | if (WARN_ON(pi < 0)) | |
282 | return -EINVAL; | |
283 | ||
284 | /* Disable compression if suitable settings couldn't be found. */ | |
285 | if (nvbo->comp && !vmm->page[pi].comp) { | |
286 | if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) | |
287 | nvbo->kind = mmu->kind[nvbo->kind]; | |
288 | nvbo->comp = 0; | |
f91bac5b | 289 | } |
7dc6a446 | 290 | nvbo->page = vmm->page[pi].shift; |
f91bac5b BS |
291 | |
292 | nouveau_bo_fixup_align(nvbo, flags, &align, &size); | |
fd2871af BS |
293 | nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; |
294 | nouveau_bo_placement_set(nvbo, flags, 0); | |
6ee73861 | 295 | |
ebb945a9 | 296 | acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, |
57de4ba9 JG |
297 | sizeof(struct nouveau_bo)); |
298 | ||
ebb945a9 | 299 | ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, |
22b33e8e | 300 | type, &nvbo->placement, |
0b91c4a1 | 301 | align >> PAGE_SHIFT, false, NULL, acc_size, sg, |
bb6178b0 | 302 | robj, nouveau_bo_del_ttm); |
6ee73861 BS |
303 | if (ret) { |
304 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
305 | return ret; | |
306 | } | |
307 | ||
6ee73861 BS |
308 | *pnvbo = nvbo; |
309 | return 0; | |
310 | } | |
311 | ||
78ad0f7b | 312 | static void |
f1217ed0 | 313 | set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) |
78ad0f7b FJ |
314 | { |
315 | *n = 0; | |
316 | ||
317 | if (type & TTM_PL_FLAG_VRAM) | |
f1217ed0 | 318 | pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; |
78ad0f7b | 319 | if (type & TTM_PL_FLAG_TT) |
f1217ed0 | 320 | pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; |
78ad0f7b | 321 | if (type & TTM_PL_FLAG_SYSTEM) |
f1217ed0 | 322 | pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; |
78ad0f7b FJ |
323 | } |
324 | ||
699ddfd9 FJ |
325 | static void |
326 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) | |
327 | { | |
ebb945a9 | 328 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
1167c6bc | 329 | u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; |
f1217ed0 | 330 | unsigned i, fpfn, lpfn; |
699ddfd9 | 331 | |
1167c6bc | 332 | if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && |
7760a2e3 | 333 | nvbo->mode && (type & TTM_PL_FLAG_VRAM) && |
4beb116a | 334 | nvbo->bo.mem.num_pages < vram_pages / 4) { |
699ddfd9 FJ |
335 | /* |
336 | * Make sure that the color and depth buffers are handled | |
337 | * by independent memory controller units. Up to a 9x | |
338 | * speed up when alpha-blending and depth-test are enabled | |
339 | * at the same time. | |
340 | */ | |
7760a2e3 | 341 | if (nvbo->zeta) { |
f1217ed0 CK |
342 | fpfn = vram_pages / 2; |
343 | lpfn = ~0; | |
699ddfd9 | 344 | } else { |
f1217ed0 CK |
345 | fpfn = 0; |
346 | lpfn = vram_pages / 2; | |
347 | } | |
348 | for (i = 0; i < nvbo->placement.num_placement; ++i) { | |
349 | nvbo->placements[i].fpfn = fpfn; | |
350 | nvbo->placements[i].lpfn = lpfn; | |
351 | } | |
352 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { | |
353 | nvbo->busy_placements[i].fpfn = fpfn; | |
354 | nvbo->busy_placements[i].lpfn = lpfn; | |
699ddfd9 FJ |
355 | } |
356 | } | |
357 | } | |
358 | ||
6ee73861 | 359 | void |
78ad0f7b | 360 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
6ee73861 | 361 | { |
78ad0f7b | 362 | struct ttm_placement *pl = &nvbo->placement; |
c3a0c771 AC |
363 | uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : |
364 | TTM_PL_MASK_CACHING) | | |
365 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); | |
78ad0f7b FJ |
366 | |
367 | pl->placement = nvbo->placements; | |
368 | set_placement_list(nvbo->placements, &pl->num_placement, | |
369 | type, flags); | |
370 | ||
371 | pl->busy_placement = nvbo->busy_placements; | |
372 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, | |
373 | type | busy, flags); | |
699ddfd9 FJ |
374 | |
375 | set_placement_range(nvbo, type); | |
6ee73861 BS |
376 | } |
377 | ||
378 | int | |
ad76b3f7 | 379 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) |
6ee73861 | 380 | { |
ebb945a9 | 381 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 382 | struct ttm_buffer_object *bo = &nvbo->bo; |
ad76b3f7 | 383 | bool force = false, evict = false; |
78ad0f7b | 384 | int ret; |
6ee73861 | 385 | |
dfd5e50e | 386 | ret = ttm_bo_reserve(bo, false, false, NULL); |
0ae6d7bc | 387 | if (ret) |
50ab2e52 | 388 | return ret; |
0ae6d7bc | 389 | |
1167c6bc | 390 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && |
ad76b3f7 | 391 | memtype == TTM_PL_FLAG_VRAM && contig) { |
7760a2e3 BS |
392 | if (!nvbo->contig) { |
393 | nvbo->contig = true; | |
ad76b3f7 | 394 | force = true; |
7760a2e3 | 395 | evict = true; |
ad76b3f7 | 396 | } |
6ee73861 BS |
397 | } |
398 | ||
ad76b3f7 BS |
399 | if (nvbo->pin_refcnt) { |
400 | if (!(memtype & (1 << bo->mem.mem_type)) || evict) { | |
401 | NV_ERROR(drm, "bo %p pinned elsewhere: " | |
402 | "0x%08x vs 0x%08x\n", bo, | |
403 | 1 << bo->mem.mem_type, memtype); | |
404 | ret = -EBUSY; | |
405 | } | |
406 | nvbo->pin_refcnt++; | |
50ab2e52 | 407 | goto out; |
ad76b3f7 BS |
408 | } |
409 | ||
410 | if (evict) { | |
411 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); | |
412 | ret = nouveau_bo_validate(nvbo, false, false); | |
413 | if (ret) | |
414 | goto out; | |
415 | } | |
6ee73861 | 416 | |
ad76b3f7 | 417 | nvbo->pin_refcnt++; |
78ad0f7b | 418 | nouveau_bo_placement_set(nvbo, memtype, 0); |
6ee73861 | 419 | |
50ab2e52 BS |
420 | /* drop pin_refcnt temporarily, so we don't trip the assertion |
421 | * in nouveau_bo_move() that makes sure we're not trying to | |
422 | * move a pinned buffer | |
423 | */ | |
424 | nvbo->pin_refcnt--; | |
97a875cb | 425 | ret = nouveau_bo_validate(nvbo, false, false); |
6aac6ced BS |
426 | if (ret) |
427 | goto out; | |
50ab2e52 | 428 | nvbo->pin_refcnt++; |
6aac6ced BS |
429 | |
430 | switch (bo->mem.mem_type) { | |
431 | case TTM_PL_VRAM: | |
432 | drm->gem.vram_available -= bo->mem.size; | |
433 | break; | |
434 | case TTM_PL_TT: | |
435 | drm->gem.gart_available -= bo->mem.size; | |
436 | break; | |
437 | default: | |
438 | break; | |
6ee73861 | 439 | } |
5be5a15a | 440 | |
6ee73861 | 441 | out: |
ad76b3f7 | 442 | if (force && ret) |
7760a2e3 | 443 | nvbo->contig = false; |
0ae6d7bc | 444 | ttm_bo_unreserve(bo); |
6ee73861 BS |
445 | return ret; |
446 | } | |
447 | ||
448 | int | |
449 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
450 | { | |
ebb945a9 | 451 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 452 | struct ttm_buffer_object *bo = &nvbo->bo; |
4f385599 | 453 | int ret, ref; |
6ee73861 | 454 | |
dfd5e50e | 455 | ret = ttm_bo_reserve(bo, false, false, NULL); |
6ee73861 BS |
456 | if (ret) |
457 | return ret; | |
458 | ||
4f385599 ML |
459 | ref = --nvbo->pin_refcnt; |
460 | WARN_ON_ONCE(ref < 0); | |
461 | if (ref) | |
0ae6d7bc DV |
462 | goto out; |
463 | ||
78ad0f7b | 464 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
6ee73861 | 465 | |
97a875cb | 466 | ret = nouveau_bo_validate(nvbo, false, false); |
6ee73861 BS |
467 | if (ret == 0) { |
468 | switch (bo->mem.mem_type) { | |
469 | case TTM_PL_VRAM: | |
ebb945a9 | 470 | drm->gem.vram_available += bo->mem.size; |
6ee73861 BS |
471 | break; |
472 | case TTM_PL_TT: | |
ebb945a9 | 473 | drm->gem.gart_available += bo->mem.size; |
6ee73861 BS |
474 | break; |
475 | default: | |
476 | break; | |
477 | } | |
478 | } | |
479 | ||
0ae6d7bc | 480 | out: |
6ee73861 BS |
481 | ttm_bo_unreserve(bo); |
482 | return ret; | |
483 | } | |
484 | ||
485 | int | |
486 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
487 | { | |
488 | int ret; | |
489 | ||
dfd5e50e | 490 | ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); |
6ee73861 BS |
491 | if (ret) |
492 | return ret; | |
493 | ||
36a471ba | 494 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); |
c3a0c771 | 495 | |
6ee73861 BS |
496 | ttm_bo_unreserve(&nvbo->bo); |
497 | return ret; | |
498 | } | |
499 | ||
500 | void | |
501 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
502 | { | |
c3a0c771 AC |
503 | if (!nvbo) |
504 | return; | |
505 | ||
36a471ba | 506 | ttm_bo_kunmap(&nvbo->kmap); |
6ee73861 BS |
507 | } |
508 | ||
b22870ba AC |
509 | void |
510 | nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) | |
511 | { | |
512 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); | |
b22870ba AC |
513 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
514 | int i; | |
515 | ||
516 | if (!ttm_dma) | |
517 | return; | |
518 | ||
519 | /* Don't waste time looping if the object is coherent */ | |
520 | if (nvbo->force_coherent) | |
521 | return; | |
522 | ||
523 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) | |
359088d5 BS |
524 | dma_sync_single_for_device(drm->dev->dev, |
525 | ttm_dma->dma_address[i], | |
26c9e8ef | 526 | PAGE_SIZE, DMA_TO_DEVICE); |
b22870ba AC |
527 | } |
528 | ||
529 | void | |
530 | nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) | |
531 | { | |
532 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); | |
b22870ba AC |
533 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
534 | int i; | |
535 | ||
536 | if (!ttm_dma) | |
537 | return; | |
538 | ||
539 | /* Don't waste time looping if the object is coherent */ | |
540 | if (nvbo->force_coherent) | |
541 | return; | |
542 | ||
543 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) | |
359088d5 | 544 | dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], |
26c9e8ef | 545 | PAGE_SIZE, DMA_FROM_DEVICE); |
b22870ba AC |
546 | } |
547 | ||
7a45d764 BS |
548 | int |
549 | nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, | |
97a875cb | 550 | bool no_wait_gpu) |
7a45d764 BS |
551 | { |
552 | int ret; | |
553 | ||
97a875cb ML |
554 | ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, |
555 | interruptible, no_wait_gpu); | |
7a45d764 BS |
556 | if (ret) |
557 | return ret; | |
558 | ||
b22870ba AC |
559 | nouveau_bo_sync_for_device(nvbo); |
560 | ||
7a45d764 BS |
561 | return 0; |
562 | } | |
563 | ||
6ee73861 BS |
564 | void |
565 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
566 | { | |
567 | bool is_iomem; | |
568 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 | 569 | |
36a471ba | 570 | mem += index; |
c3a0c771 | 571 | |
6ee73861 BS |
572 | if (is_iomem) |
573 | iowrite16_native(val, (void __force __iomem *)mem); | |
574 | else | |
575 | *mem = val; | |
576 | } | |
577 | ||
578 | u32 | |
579 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
580 | { | |
581 | bool is_iomem; | |
582 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 | 583 | |
36a471ba | 584 | mem += index; |
c3a0c771 | 585 | |
6ee73861 BS |
586 | if (is_iomem) |
587 | return ioread32_native((void __force __iomem *)mem); | |
588 | else | |
589 | return *mem; | |
590 | } | |
591 | ||
592 | void | |
593 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
594 | { | |
595 | bool is_iomem; | |
596 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 | 597 | |
36a471ba | 598 | mem += index; |
c3a0c771 | 599 | |
6ee73861 BS |
600 | if (is_iomem) |
601 | iowrite32_native(val, (void __force __iomem *)mem); | |
602 | else | |
603 | *mem = val; | |
604 | } | |
605 | ||
649bf3ca | 606 | static struct ttm_tt * |
ebb945a9 BS |
607 | nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, |
608 | uint32_t page_flags, struct page *dummy_read) | |
6ee73861 | 609 | { |
a7fb8a23 | 610 | #if IS_ENABLED(CONFIG_AGP) |
ebb945a9 | 611 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
6ee73861 | 612 | |
340b0e7c BS |
613 | if (drm->agp.bridge) { |
614 | return ttm_agp_tt_create(bdev, drm->agp.bridge, size, | |
ebb945a9 | 615 | page_flags, dummy_read); |
6ee73861 | 616 | } |
df1b4b91 | 617 | #endif |
6ee73861 | 618 | |
ebb945a9 | 619 | return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read); |
6ee73861 BS |
620 | } |
621 | ||
622 | static int | |
623 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
624 | { | |
625 | /* We'll do this from user space. */ | |
626 | return 0; | |
627 | } | |
628 | ||
629 | static int | |
630 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
631 | struct ttm_mem_type_manager *man) | |
632 | { | |
ebb945a9 | 633 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
b3472020 | 634 | struct nvif_mmu *mmu = &drm->client.mmu; |
6ee73861 BS |
635 | |
636 | switch (type) { | |
637 | case TTM_PL_SYSTEM: | |
638 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
639 | man->available_caching = TTM_PL_MASK_CACHING; | |
640 | man->default_caching = TTM_PL_FLAG_CACHED; | |
641 | break; | |
642 | case TTM_PL_VRAM: | |
e2a4e78c AC |
643 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
644 | TTM_MEMTYPE_FLAG_MAPPABLE; | |
645 | man->available_caching = TTM_PL_FLAG_UNCACHED | | |
646 | TTM_PL_FLAG_WC; | |
647 | man->default_caching = TTM_PL_FLAG_WC; | |
648 | ||
1167c6bc | 649 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
e2a4e78c | 650 | /* Some BARs do not support being ioremapped WC */ |
b3472020 BS |
651 | const u8 type = mmu->type[drm->ttm.type_vram].type; |
652 | if (type & NVIF_MEM_UNCACHED) { | |
e2a4e78c AC |
653 | man->available_caching = TTM_PL_FLAG_UNCACHED; |
654 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
655 | } | |
656 | ||
573a2a37 | 657 | man->func = &nouveau_vram_manager; |
f869ef88 BS |
658 | man->io_reserve_fastpath = false; |
659 | man->use_io_reserve_lru = true; | |
660 | } else { | |
573a2a37 | 661 | man->func = &ttm_bo_manager_func; |
f869ef88 | 662 | } |
6ee73861 BS |
663 | break; |
664 | case TTM_PL_TT: | |
1167c6bc | 665 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) |
26c0c9e3 | 666 | man->func = &nouveau_gart_manager; |
3863c9bc | 667 | else |
340b0e7c | 668 | if (!drm->agp.bridge) |
3863c9bc | 669 | man->func = &nv04_gart_manager; |
26c0c9e3 BS |
670 | else |
671 | man->func = &ttm_bo_manager_func; | |
ebb945a9 | 672 | |
340b0e7c | 673 | if (drm->agp.bridge) { |
f32f02fd | 674 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
a3d487ea FJ |
675 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
676 | TTM_PL_FLAG_WC; | |
677 | man->default_caching = TTM_PL_FLAG_WC; | |
ebb945a9 | 678 | } else { |
6ee73861 BS |
679 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | |
680 | TTM_MEMTYPE_FLAG_CMA; | |
681 | man->available_caching = TTM_PL_MASK_CACHING; | |
682 | man->default_caching = TTM_PL_FLAG_CACHED; | |
6ee73861 | 683 | } |
ebb945a9 | 684 | |
6ee73861 BS |
685 | break; |
686 | default: | |
6ee73861 BS |
687 | return -EINVAL; |
688 | } | |
689 | return 0; | |
690 | } | |
691 | ||
692 | static void | |
693 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
694 | { | |
695 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
696 | ||
697 | switch (bo->mem.mem_type) { | |
22fbd538 | 698 | case TTM_PL_VRAM: |
78ad0f7b FJ |
699 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
700 | TTM_PL_FLAG_SYSTEM); | |
22fbd538 | 701 | break; |
6ee73861 | 702 | default: |
78ad0f7b | 703 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
6ee73861 BS |
704 | break; |
705 | } | |
22fbd538 FJ |
706 | |
707 | *pl = nvbo->placement; | |
6ee73861 BS |
708 | } |
709 | ||
710 | ||
49981046 BS |
711 | static int |
712 | nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
713 | { | |
714 | int ret = RING_SPACE(chan, 2); | |
715 | if (ret == 0) { | |
716 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
00fc6f6f | 717 | OUT_RING (chan, handle & 0x0000ffff); |
49981046 BS |
718 | FIRE_RING (chan); |
719 | } | |
720 | return ret; | |
721 | } | |
722 | ||
c6b7e895 BS |
723 | static int |
724 | nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 725 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
c6b7e895 | 726 | { |
9ce523cc | 727 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
c6b7e895 BS |
728 | int ret = RING_SPACE(chan, 10); |
729 | if (ret == 0) { | |
6d597027 | 730 | BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); |
9ce523cc BS |
731 | OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); |
732 | OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); | |
733 | OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); | |
734 | OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); | |
c6b7e895 BS |
735 | OUT_RING (chan, PAGE_SIZE); |
736 | OUT_RING (chan, PAGE_SIZE); | |
737 | OUT_RING (chan, PAGE_SIZE); | |
605f9ccd | 738 | OUT_RING (chan, new_reg->num_pages); |
6d597027 | 739 | BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); |
c6b7e895 BS |
740 | } |
741 | return ret; | |
742 | } | |
743 | ||
d1b167e1 BS |
744 | static int |
745 | nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
746 | { | |
747 | int ret = RING_SPACE(chan, 2); | |
748 | if (ret == 0) { | |
749 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
750 | OUT_RING (chan, handle); | |
751 | } | |
752 | return ret; | |
753 | } | |
754 | ||
1a46098e BS |
755 | static int |
756 | nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 757 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
1a46098e | 758 | { |
9ce523cc BS |
759 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
760 | u64 src_offset = mem->vma[0].addr; | |
761 | u64 dst_offset = mem->vma[1].addr; | |
605f9ccd | 762 | u32 page_count = new_reg->num_pages; |
1a46098e BS |
763 | int ret; |
764 | ||
605f9ccd | 765 | page_count = new_reg->num_pages; |
1a46098e BS |
766 | while (page_count) { |
767 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
768 | ||
769 | ret = RING_SPACE(chan, 11); | |
770 | if (ret) | |
771 | return ret; | |
772 | ||
773 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); | |
774 | OUT_RING (chan, upper_32_bits(src_offset)); | |
775 | OUT_RING (chan, lower_32_bits(src_offset)); | |
776 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
777 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
778 | OUT_RING (chan, PAGE_SIZE); | |
779 | OUT_RING (chan, PAGE_SIZE); | |
780 | OUT_RING (chan, PAGE_SIZE); | |
781 | OUT_RING (chan, line_count); | |
782 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); | |
783 | OUT_RING (chan, 0x00000110); | |
784 | ||
785 | page_count -= line_count; | |
786 | src_offset += (PAGE_SIZE * line_count); | |
787 | dst_offset += (PAGE_SIZE * line_count); | |
788 | } | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
183720b8 BS |
793 | static int |
794 | nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 795 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
183720b8 | 796 | { |
9ce523cc BS |
797 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
798 | u64 src_offset = mem->vma[0].addr; | |
799 | u64 dst_offset = mem->vma[1].addr; | |
605f9ccd | 800 | u32 page_count = new_reg->num_pages; |
183720b8 BS |
801 | int ret; |
802 | ||
605f9ccd | 803 | page_count = new_reg->num_pages; |
183720b8 BS |
804 | while (page_count) { |
805 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
806 | ||
807 | ret = RING_SPACE(chan, 12); | |
808 | if (ret) | |
809 | return ret; | |
810 | ||
d1b167e1 | 811 | BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); |
183720b8 BS |
812 | OUT_RING (chan, upper_32_bits(dst_offset)); |
813 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
d1b167e1 | 814 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); |
183720b8 BS |
815 | OUT_RING (chan, upper_32_bits(src_offset)); |
816 | OUT_RING (chan, lower_32_bits(src_offset)); | |
817 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
818 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
819 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
820 | OUT_RING (chan, line_count); | |
d1b167e1 | 821 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); |
183720b8 BS |
822 | OUT_RING (chan, 0x00100110); |
823 | ||
824 | page_count -= line_count; | |
825 | src_offset += (PAGE_SIZE * line_count); | |
826 | dst_offset += (PAGE_SIZE * line_count); | |
827 | } | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
fdf53241 BS |
832 | static int |
833 | nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 834 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
fdf53241 | 835 | { |
9ce523cc BS |
836 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
837 | u64 src_offset = mem->vma[0].addr; | |
838 | u64 dst_offset = mem->vma[1].addr; | |
605f9ccd | 839 | u32 page_count = new_reg->num_pages; |
fdf53241 BS |
840 | int ret; |
841 | ||
605f9ccd | 842 | page_count = new_reg->num_pages; |
fdf53241 BS |
843 | while (page_count) { |
844 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
845 | ||
846 | ret = RING_SPACE(chan, 11); | |
847 | if (ret) | |
848 | return ret; | |
849 | ||
850 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); | |
851 | OUT_RING (chan, upper_32_bits(src_offset)); | |
852 | OUT_RING (chan, lower_32_bits(src_offset)); | |
853 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
854 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
855 | OUT_RING (chan, PAGE_SIZE); | |
856 | OUT_RING (chan, PAGE_SIZE); | |
857 | OUT_RING (chan, PAGE_SIZE); | |
858 | OUT_RING (chan, line_count); | |
859 | BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); | |
860 | OUT_RING (chan, 0x00000110); | |
861 | ||
862 | page_count -= line_count; | |
863 | src_offset += (PAGE_SIZE * line_count); | |
864 | dst_offset += (PAGE_SIZE * line_count); | |
865 | } | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
5490e5df BS |
870 | static int |
871 | nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 872 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
5490e5df | 873 | { |
9ce523cc | 874 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
5490e5df BS |
875 | int ret = RING_SPACE(chan, 7); |
876 | if (ret == 0) { | |
877 | BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); | |
9ce523cc BS |
878 | OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); |
879 | OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); | |
880 | OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); | |
881 | OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); | |
5490e5df | 882 | OUT_RING (chan, 0x00000000 /* COPY */); |
605f9ccd | 883 | OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); |
5490e5df BS |
884 | } |
885 | return ret; | |
886 | } | |
887 | ||
4c193d25 BS |
888 | static int |
889 | nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 890 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
4c193d25 | 891 | { |
9ce523cc | 892 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
4c193d25 BS |
893 | int ret = RING_SPACE(chan, 7); |
894 | if (ret == 0) { | |
895 | BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); | |
605f9ccd | 896 | OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); |
9ce523cc BS |
897 | OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); |
898 | OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); | |
899 | OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); | |
900 | OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); | |
4c193d25 BS |
901 | OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); |
902 | } | |
903 | return ret; | |
904 | } | |
905 | ||
d1b167e1 BS |
906 | static int |
907 | nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
908 | { | |
ebb945a9 | 909 | int ret = RING_SPACE(chan, 6); |
d1b167e1 | 910 | if (ret == 0) { |
ebb945a9 BS |
911 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
912 | OUT_RING (chan, handle); | |
913 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); | |
f45f55c4 BS |
914 | OUT_RING (chan, chan->drm->ntfy.handle); |
915 | OUT_RING (chan, chan->vram.handle); | |
916 | OUT_RING (chan, chan->vram.handle); | |
d1b167e1 BS |
917 | } |
918 | ||
919 | return ret; | |
920 | } | |
921 | ||
6ee73861 | 922 | static int |
f1ab0cc9 | 923 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
605f9ccd | 924 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
6ee73861 | 925 | { |
9ce523cc | 926 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
605f9ccd | 927 | u64 length = (new_reg->num_pages << PAGE_SHIFT); |
9ce523cc BS |
928 | u64 src_offset = mem->vma[0].addr; |
929 | u64 dst_offset = mem->vma[1].addr; | |
930 | int src_tiled = !!mem->kind; | |
931 | int dst_tiled = !!nouveau_mem(new_reg)->kind; | |
6ee73861 BS |
932 | int ret; |
933 | ||
f1ab0cc9 BS |
934 | while (length) { |
935 | u32 amount, stride, height; | |
936 | ||
ce8f7699 ML |
937 | ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); |
938 | if (ret) | |
939 | return ret; | |
940 | ||
5220b3c1 BS |
941 | amount = min(length, (u64)(4 * 1024 * 1024)); |
942 | stride = 16 * 4; | |
f1ab0cc9 BS |
943 | height = amount / stride; |
944 | ||
ce8f7699 | 945 | if (src_tiled) { |
d1b167e1 | 946 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); |
f1ab0cc9 | 947 | OUT_RING (chan, 0); |
5220b3c1 | 948 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
949 | OUT_RING (chan, stride); |
950 | OUT_RING (chan, height); | |
951 | OUT_RING (chan, 1); | |
952 | OUT_RING (chan, 0); | |
953 | OUT_RING (chan, 0); | |
954 | } else { | |
d1b167e1 | 955 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); |
f1ab0cc9 BS |
956 | OUT_RING (chan, 1); |
957 | } | |
ce8f7699 | 958 | if (dst_tiled) { |
d1b167e1 | 959 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); |
f1ab0cc9 | 960 | OUT_RING (chan, 0); |
5220b3c1 | 961 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
962 | OUT_RING (chan, stride); |
963 | OUT_RING (chan, height); | |
964 | OUT_RING (chan, 1); | |
965 | OUT_RING (chan, 0); | |
966 | OUT_RING (chan, 0); | |
967 | } else { | |
d1b167e1 | 968 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); |
f1ab0cc9 BS |
969 | OUT_RING (chan, 1); |
970 | } | |
971 | ||
d1b167e1 | 972 | BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); |
f1ab0cc9 BS |
973 | OUT_RING (chan, upper_32_bits(src_offset)); |
974 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
d1b167e1 | 975 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); |
f1ab0cc9 BS |
976 | OUT_RING (chan, lower_32_bits(src_offset)); |
977 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
978 | OUT_RING (chan, stride); | |
979 | OUT_RING (chan, stride); | |
980 | OUT_RING (chan, stride); | |
981 | OUT_RING (chan, height); | |
982 | OUT_RING (chan, 0x00000101); | |
983 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 984 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 BS |
985 | OUT_RING (chan, 0); |
986 | ||
987 | length -= amount; | |
988 | src_offset += amount; | |
989 | dst_offset += amount; | |
6ee73861 BS |
990 | } |
991 | ||
f1ab0cc9 BS |
992 | return 0; |
993 | } | |
994 | ||
d1b167e1 BS |
995 | static int |
996 | nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
997 | { | |
ebb945a9 | 998 | int ret = RING_SPACE(chan, 4); |
d1b167e1 | 999 | if (ret == 0) { |
ebb945a9 BS |
1000 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
1001 | OUT_RING (chan, handle); | |
1002 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); | |
f45f55c4 | 1003 | OUT_RING (chan, chan->drm->ntfy.handle); |
d1b167e1 BS |
1004 | } |
1005 | ||
1006 | return ret; | |
1007 | } | |
1008 | ||
a6704788 BS |
1009 | static inline uint32_t |
1010 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, | |
605f9ccd | 1011 | struct nouveau_channel *chan, struct ttm_mem_reg *reg) |
a6704788 | 1012 | { |
605f9ccd | 1013 | if (reg->mem_type == TTM_PL_TT) |
ebb945a9 | 1014 | return NvDmaTT; |
f45f55c4 | 1015 | return chan->vram.handle; |
a6704788 BS |
1016 | } |
1017 | ||
f1ab0cc9 BS |
1018 | static int |
1019 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 1020 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
f1ab0cc9 | 1021 | { |
605f9ccd BS |
1022 | u32 src_offset = old_reg->start << PAGE_SHIFT; |
1023 | u32 dst_offset = new_reg->start << PAGE_SHIFT; | |
1024 | u32 page_count = new_reg->num_pages; | |
f1ab0cc9 BS |
1025 | int ret; |
1026 | ||
1027 | ret = RING_SPACE(chan, 3); | |
1028 | if (ret) | |
1029 | return ret; | |
1030 | ||
d1b167e1 | 1031 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); |
605f9ccd BS |
1032 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); |
1033 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); | |
f1ab0cc9 | 1034 | |
605f9ccd | 1035 | page_count = new_reg->num_pages; |
6ee73861 BS |
1036 | while (page_count) { |
1037 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
1038 | ||
6ee73861 BS |
1039 | ret = RING_SPACE(chan, 11); |
1040 | if (ret) | |
1041 | return ret; | |
f1ab0cc9 | 1042 | |
d1b167e1 | 1043 | BEGIN_NV04(chan, NvSubCopy, |
6ee73861 | 1044 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); |
f1ab0cc9 BS |
1045 | OUT_RING (chan, src_offset); |
1046 | OUT_RING (chan, dst_offset); | |
1047 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
1048 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
1049 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
1050 | OUT_RING (chan, line_count); | |
1051 | OUT_RING (chan, 0x00000101); | |
1052 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 1053 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 | 1054 | OUT_RING (chan, 0); |
6ee73861 BS |
1055 | |
1056 | page_count -= line_count; | |
1057 | src_offset += (PAGE_SIZE * line_count); | |
1058 | dst_offset += (PAGE_SIZE * line_count); | |
1059 | } | |
1060 | ||
f1ab0cc9 BS |
1061 | return 0; |
1062 | } | |
1063 | ||
d2f96666 | 1064 | static int |
3c57d85d | 1065 | nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, |
605f9ccd | 1066 | struct ttm_mem_reg *reg) |
d2f96666 | 1067 | { |
9ce523cc BS |
1068 | struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); |
1069 | struct nouveau_mem *new_mem = nouveau_mem(reg); | |
d7722134 | 1070 | struct nvif_vmm *vmm = &drm->client.vmm.vmm; |
d2f96666 BS |
1071 | int ret; |
1072 | ||
d7722134 BS |
1073 | ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, |
1074 | old_mem->mem.size, &old_mem->vma[0]); | |
d2f96666 BS |
1075 | if (ret) |
1076 | return ret; | |
1077 | ||
d7722134 BS |
1078 | ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, |
1079 | new_mem->mem.size, &old_mem->vma[1]); | |
1080 | if (ret) | |
1081 | goto done; | |
3c57d85d | 1082 | |
9ce523cc BS |
1083 | ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); |
1084 | if (ret) | |
1085 | goto done; | |
1086 | ||
1087 | ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); | |
1088 | done: | |
1089 | if (ret) { | |
d7722134 BS |
1090 | nvif_vmm_put(vmm, &old_mem->vma[1]); |
1091 | nvif_vmm_put(vmm, &old_mem->vma[0]); | |
9ce523cc | 1092 | } |
d2f96666 BS |
1093 | return 0; |
1094 | } | |
1095 | ||
f1ab0cc9 BS |
1096 | static int |
1097 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |
605f9ccd | 1098 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
f1ab0cc9 | 1099 | { |
ebb945a9 | 1100 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1934a2ad | 1101 | struct nouveau_channel *chan = drm->ttm.chan; |
a01ca78c | 1102 | struct nouveau_cli *cli = (void *)chan->user.client; |
35b8141b | 1103 | struct nouveau_fence *fence; |
f1ab0cc9 BS |
1104 | int ret; |
1105 | ||
d2f96666 | 1106 | /* create temporary vmas for the transfer and attach them to the |
be83cd4e | 1107 | * old nvkm_mem node, these will get cleaned up after ttm has |
d2f96666 | 1108 | * destroyed the ttm_mem_reg |
3425df48 | 1109 | */ |
1167c6bc | 1110 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
605f9ccd | 1111 | ret = nouveau_bo_move_prep(drm, bo, new_reg); |
d2f96666 | 1112 | if (ret) |
3c57d85d | 1113 | return ret; |
3425df48 BS |
1114 | } |
1115 | ||
0ad72863 | 1116 | mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); |
e3be4c23 | 1117 | ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); |
6a6b73f2 | 1118 | if (ret == 0) { |
605f9ccd | 1119 | ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); |
35b8141b BS |
1120 | if (ret == 0) { |
1121 | ret = nouveau_fence_new(chan, false, &fence); | |
1122 | if (ret == 0) { | |
f2c24b83 ML |
1123 | ret = ttm_bo_move_accel_cleanup(bo, |
1124 | &fence->base, | |
35b8141b | 1125 | evict, |
605f9ccd | 1126 | new_reg); |
35b8141b BS |
1127 | nouveau_fence_unref(&fence); |
1128 | } | |
1129 | } | |
6a6b73f2 | 1130 | } |
0ad72863 | 1131 | mutex_unlock(&cli->mutex); |
6a6b73f2 | 1132 | return ret; |
6ee73861 BS |
1133 | } |
1134 | ||
d1b167e1 | 1135 | void |
49981046 | 1136 | nouveau_bo_move_init(struct nouveau_drm *drm) |
d1b167e1 | 1137 | { |
d1b167e1 BS |
1138 | static const struct { |
1139 | const char *name; | |
1a46098e | 1140 | int engine; |
315a8b2e | 1141 | s32 oclass; |
d1b167e1 BS |
1142 | int (*exec)(struct nouveau_channel *, |
1143 | struct ttm_buffer_object *, | |
1144 | struct ttm_mem_reg *, struct ttm_mem_reg *); | |
1145 | int (*init)(struct nouveau_channel *, u32 handle); | |
1146 | } _methods[] = { | |
146cfe24 BS |
1147 | { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, |
1148 | { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, | |
8e7e1586 BS |
1149 | { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
1150 | { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, | |
990b4547 BS |
1151 | { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
1152 | { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, | |
00fc6f6f | 1153 | { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
49981046 | 1154 | { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, |
1a46098e BS |
1155 | { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, |
1156 | { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, | |
1157 | { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, | |
1158 | { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, | |
1159 | { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, | |
1160 | { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, | |
1161 | { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, | |
5490e5df | 1162 | {}, |
1a46098e | 1163 | { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, |
d1b167e1 BS |
1164 | }, *mthd = _methods; |
1165 | const char *name = "CPU"; | |
1166 | int ret; | |
1167 | ||
1168 | do { | |
49981046 | 1169 | struct nouveau_channel *chan; |
ebb945a9 | 1170 | |
00fc6f6f | 1171 | if (mthd->engine) |
49981046 BS |
1172 | chan = drm->cechan; |
1173 | else | |
1174 | chan = drm->channel; | |
1175 | if (chan == NULL) | |
1176 | continue; | |
1177 | ||
a01ca78c | 1178 | ret = nvif_object_init(&chan->user, |
0ad72863 BS |
1179 | mthd->oclass | (mthd->engine << 16), |
1180 | mthd->oclass, NULL, 0, | |
1181 | &drm->ttm.copy); | |
d1b167e1 | 1182 | if (ret == 0) { |
0ad72863 | 1183 | ret = mthd->init(chan, drm->ttm.copy.handle); |
ebb945a9 | 1184 | if (ret) { |
0ad72863 | 1185 | nvif_object_fini(&drm->ttm.copy); |
ebb945a9 | 1186 | continue; |
d1b167e1 | 1187 | } |
ebb945a9 BS |
1188 | |
1189 | drm->ttm.move = mthd->exec; | |
1bb3f6a2 | 1190 | drm->ttm.chan = chan; |
ebb945a9 BS |
1191 | name = mthd->name; |
1192 | break; | |
d1b167e1 BS |
1193 | } |
1194 | } while ((++mthd)->exec); | |
1195 | ||
ebb945a9 | 1196 | NV_INFO(drm, "MM: using %s for buffer copies\n", name); |
d1b167e1 BS |
1197 | } |
1198 | ||
6ee73861 BS |
1199 | static int |
1200 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
605f9ccd | 1201 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
6ee73861 | 1202 | { |
f1217ed0 CK |
1203 | struct ttm_place placement_memtype = { |
1204 | .fpfn = 0, | |
1205 | .lpfn = 0, | |
1206 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING | |
1207 | }; | |
6ee73861 | 1208 | struct ttm_placement placement; |
605f9ccd | 1209 | struct ttm_mem_reg tmp_reg; |
6ee73861 BS |
1210 | int ret; |
1211 | ||
6ee73861 | 1212 | placement.num_placement = placement.num_busy_placement = 1; |
77e2b5ed | 1213 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 | 1214 | |
605f9ccd BS |
1215 | tmp_reg = *new_reg; |
1216 | tmp_reg.mm_node = NULL; | |
1217 | ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); | |
6ee73861 BS |
1218 | if (ret) |
1219 | return ret; | |
1220 | ||
605f9ccd | 1221 | ret = ttm_tt_bind(bo->ttm, &tmp_reg); |
6ee73861 BS |
1222 | if (ret) |
1223 | goto out; | |
1224 | ||
605f9ccd | 1225 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); |
6ee73861 BS |
1226 | if (ret) |
1227 | goto out; | |
1228 | ||
605f9ccd | 1229 | ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_reg); |
6ee73861 | 1230 | out: |
605f9ccd | 1231 | ttm_bo_mem_put(bo, &tmp_reg); |
6ee73861 BS |
1232 | return ret; |
1233 | } | |
1234 | ||
1235 | static int | |
1236 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
605f9ccd | 1237 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
6ee73861 | 1238 | { |
f1217ed0 CK |
1239 | struct ttm_place placement_memtype = { |
1240 | .fpfn = 0, | |
1241 | .lpfn = 0, | |
1242 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING | |
1243 | }; | |
6ee73861 | 1244 | struct ttm_placement placement; |
605f9ccd | 1245 | struct ttm_mem_reg tmp_reg; |
6ee73861 BS |
1246 | int ret; |
1247 | ||
6ee73861 | 1248 | placement.num_placement = placement.num_busy_placement = 1; |
77e2b5ed | 1249 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 | 1250 | |
605f9ccd BS |
1251 | tmp_reg = *new_reg; |
1252 | tmp_reg.mm_node = NULL; | |
1253 | ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); | |
6ee73861 BS |
1254 | if (ret) |
1255 | return ret; | |
1256 | ||
605f9ccd | 1257 | ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_reg); |
6ee73861 BS |
1258 | if (ret) |
1259 | goto out; | |
1260 | ||
605f9ccd | 1261 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); |
6ee73861 BS |
1262 | if (ret) |
1263 | goto out; | |
1264 | ||
1265 | out: | |
605f9ccd | 1266 | ttm_bo_mem_put(bo, &tmp_reg); |
6ee73861 BS |
1267 | return ret; |
1268 | } | |
1269 | ||
a4154bbf | 1270 | static void |
66257db7 | 1271 | nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, |
605f9ccd | 1272 | struct ttm_mem_reg *new_reg) |
a4154bbf | 1273 | { |
9ce523cc | 1274 | struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; |
a4154bbf | 1275 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
24e8375b | 1276 | struct nouveau_vma *vma; |
fd2871af | 1277 | |
9f1feed2 BS |
1278 | /* ttm can now (stupidly) pass the driver bos it didn't create... */ |
1279 | if (bo->destroy != nouveau_bo_del_ttm) | |
1280 | return; | |
1281 | ||
a48296ab | 1282 | if (mem && new_reg->mem_type != TTM_PL_SYSTEM && |
9ce523cc | 1283 | mem->mem.page == nvbo->page) { |
a48296ab | 1284 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
24e8375b | 1285 | nouveau_vma_map(vma, mem); |
a48296ab BS |
1286 | } |
1287 | } else { | |
1288 | list_for_each_entry(vma, &nvbo->vma_list, head) { | |
10dcab3e | 1289 | WARN_ON(ttm_bo_wait(bo, false, false)); |
24e8375b | 1290 | nouveau_vma_unmap(vma); |
fd2871af | 1291 | } |
a4154bbf BS |
1292 | } |
1293 | } | |
1294 | ||
6ee73861 | 1295 | static int |
605f9ccd | 1296 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, |
ebb945a9 | 1297 | struct nouveau_drm_tile **new_tile) |
6ee73861 | 1298 | { |
ebb945a9 BS |
1299 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1300 | struct drm_device *dev = drm->dev; | |
a0af9add | 1301 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
605f9ccd | 1302 | u64 offset = new_reg->start << PAGE_SHIFT; |
6ee73861 | 1303 | |
a4154bbf | 1304 | *new_tile = NULL; |
605f9ccd | 1305 | if (new_reg->mem_type != TTM_PL_VRAM) |
a0af9add | 1306 | return 0; |
a0af9add | 1307 | |
1167c6bc | 1308 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { |
605f9ccd | 1309 | *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, |
7760a2e3 | 1310 | nvbo->mode, nvbo->zeta); |
6ee73861 BS |
1311 | } |
1312 | ||
a0af9add FJ |
1313 | return 0; |
1314 | } | |
1315 | ||
1316 | static void | |
1317 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
ebb945a9 BS |
1318 | struct nouveau_drm_tile *new_tile, |
1319 | struct nouveau_drm_tile **old_tile) | |
a0af9add | 1320 | { |
ebb945a9 BS |
1321 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1322 | struct drm_device *dev = drm->dev; | |
f54d1867 | 1323 | struct dma_fence *fence = reservation_object_get_excl(bo->resv); |
a0af9add | 1324 | |
f2c24b83 | 1325 | nv10_bo_put_tile_region(dev, *old_tile, fence); |
a4154bbf | 1326 | *old_tile = new_tile; |
a0af9add FJ |
1327 | } |
1328 | ||
1329 | static int | |
1330 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
605f9ccd | 1331 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
a0af9add | 1332 | { |
ebb945a9 | 1333 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
a0af9add | 1334 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
605f9ccd | 1335 | struct ttm_mem_reg *old_reg = &bo->mem; |
ebb945a9 | 1336 | struct nouveau_drm_tile *new_tile = NULL; |
a0af9add FJ |
1337 | int ret = 0; |
1338 | ||
88932a7b CK |
1339 | ret = ttm_bo_wait(bo, intr, no_wait_gpu); |
1340 | if (ret) | |
1341 | return ret; | |
1342 | ||
5be5a15a AC |
1343 | if (nvbo->pin_refcnt) |
1344 | NV_WARN(drm, "Moving pinned object %p!\n", nvbo); | |
1345 | ||
1167c6bc | 1346 | if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
605f9ccd | 1347 | ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); |
a4154bbf BS |
1348 | if (ret) |
1349 | return ret; | |
1350 | } | |
a0af9add | 1351 | |
a0af9add | 1352 | /* Fake bo copy. */ |
605f9ccd | 1353 | if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
6ee73861 | 1354 | BUG_ON(bo->mem.mm_node != NULL); |
605f9ccd BS |
1355 | bo->mem = *new_reg; |
1356 | new_reg->mm_node = NULL; | |
a0af9add | 1357 | goto out; |
6ee73861 BS |
1358 | } |
1359 | ||
a0af9add | 1360 | /* Hardware assisted copy. */ |
cef9e99e | 1361 | if (drm->ttm.move) { |
605f9ccd | 1362 | if (new_reg->mem_type == TTM_PL_SYSTEM) |
cef9e99e | 1363 | ret = nouveau_bo_move_flipd(bo, evict, intr, |
605f9ccd BS |
1364 | no_wait_gpu, new_reg); |
1365 | else if (old_reg->mem_type == TTM_PL_SYSTEM) | |
cef9e99e | 1366 | ret = nouveau_bo_move_flips(bo, evict, intr, |
605f9ccd | 1367 | no_wait_gpu, new_reg); |
cef9e99e BS |
1368 | else |
1369 | ret = nouveau_bo_move_m2mf(bo, evict, intr, | |
605f9ccd | 1370 | no_wait_gpu, new_reg); |
cef9e99e BS |
1371 | if (!ret) |
1372 | goto out; | |
1373 | } | |
a0af9add FJ |
1374 | |
1375 | /* Fallback to software copy. */ | |
8aa6d4fc | 1376 | ret = ttm_bo_wait(bo, intr, no_wait_gpu); |
cef9e99e | 1377 | if (ret == 0) |
605f9ccd | 1378 | ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg); |
a0af9add FJ |
1379 | |
1380 | out: | |
1167c6bc | 1381 | if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
a4154bbf BS |
1382 | if (ret) |
1383 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
1384 | else | |
1385 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
1386 | } | |
a0af9add FJ |
1387 | |
1388 | return ret; | |
6ee73861 BS |
1389 | } |
1390 | ||
1391 | static int | |
1392 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
1393 | { | |
acb46527 DH |
1394 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1395 | ||
d9a1f0b4 DH |
1396 | return drm_vma_node_verify_access(&nvbo->gem.vma_node, |
1397 | filp->private_data); | |
6ee73861 BS |
1398 | } |
1399 | ||
f32f02fd | 1400 | static int |
605f9ccd | 1401 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) |
f32f02fd | 1402 | { |
605f9ccd | 1403 | struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; |
ebb945a9 | 1404 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
1167c6bc | 1405 | struct nvkm_device *device = nvxx_device(&drm->client.device); |
9ce523cc | 1406 | struct nouveau_mem *mem = nouveau_mem(reg); |
f32f02fd | 1407 | |
605f9ccd BS |
1408 | reg->bus.addr = NULL; |
1409 | reg->bus.offset = 0; | |
1410 | reg->bus.size = reg->num_pages << PAGE_SHIFT; | |
1411 | reg->bus.base = 0; | |
1412 | reg->bus.is_iomem = false; | |
f32f02fd JG |
1413 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) |
1414 | return -EINVAL; | |
605f9ccd | 1415 | switch (reg->mem_type) { |
f32f02fd JG |
1416 | case TTM_PL_SYSTEM: |
1417 | /* System memory */ | |
1418 | return 0; | |
1419 | case TTM_PL_TT: | |
a7fb8a23 | 1420 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1421 | if (drm->agp.bridge) { |
605f9ccd BS |
1422 | reg->bus.offset = reg->start << PAGE_SHIFT; |
1423 | reg->bus.base = drm->agp.base; | |
1424 | reg->bus.is_iomem = !drm->agp.cma; | |
f32f02fd JG |
1425 | } |
1426 | #endif | |
d7722134 | 1427 | if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) |
a5540906 ML |
1428 | /* untiled */ |
1429 | break; | |
1430 | /* fallthrough, tiled memory */ | |
f32f02fd | 1431 | case TTM_PL_VRAM: |
605f9ccd BS |
1432 | reg->bus.offset = reg->start << PAGE_SHIFT; |
1433 | reg->bus.base = device->func->resource_addr(device, 1); | |
1434 | reg->bus.is_iomem = true; | |
d7722134 BS |
1435 | if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { |
1436 | union { | |
1437 | struct nv50_mem_map_v0 nv50; | |
1438 | struct gf100_mem_map_v0 gf100; | |
1439 | } args; | |
1440 | u64 handle, length; | |
1441 | u32 argc = 0; | |
1442 | int ret; | |
1443 | ||
1444 | switch (mem->mem.object.oclass) { | |
1445 | case NVIF_CLASS_MEM_NV50: | |
1446 | args.nv50.version = 0; | |
1447 | args.nv50.ro = 0; | |
1448 | args.nv50.kind = mem->kind; | |
1449 | args.nv50.comp = mem->comp; | |
1450 | break; | |
1451 | case NVIF_CLASS_MEM_GF100: | |
1452 | args.gf100.version = 0; | |
1453 | args.gf100.ro = 0; | |
1454 | args.gf100.kind = mem->kind; | |
1455 | break; | |
1456 | default: | |
1457 | WARN_ON(1); | |
1458 | break; | |
1459 | } | |
1460 | ||
1461 | ret = nvif_object_map_handle(&mem->mem.object, | |
1462 | &argc, argc, | |
1463 | &handle, &length); | |
1464 | if (ret != 1) | |
1465 | return ret ? ret : -EINVAL; | |
1466 | ||
1467 | reg->bus.base = 0; | |
1468 | reg->bus.offset = handle; | |
f869ef88 | 1469 | } |
f32f02fd JG |
1470 | break; |
1471 | default: | |
1472 | return -EINVAL; | |
1473 | } | |
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static void | |
605f9ccd | 1478 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) |
f32f02fd | 1479 | { |
d7722134 | 1480 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
9ce523cc | 1481 | struct nouveau_mem *mem = nouveau_mem(reg); |
f869ef88 | 1482 | |
d7722134 BS |
1483 | if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { |
1484 | switch (reg->mem_type) { | |
1485 | case TTM_PL_TT: | |
1486 | if (mem->kind) | |
1487 | nvif_object_unmap_handle(&mem->mem.object); | |
1488 | break; | |
1489 | case TTM_PL_VRAM: | |
1490 | nvif_object_unmap_handle(&mem->mem.object); | |
1491 | break; | |
1492 | default: | |
1493 | break; | |
1494 | } | |
1495 | } | |
f32f02fd JG |
1496 | } |
1497 | ||
1498 | static int | |
1499 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |
1500 | { | |
ebb945a9 | 1501 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
e1429b4c | 1502 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1167c6bc | 1503 | struct nvkm_device *device = nvxx_device(&drm->client.device); |
7e8820fe | 1504 | u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; |
f1217ed0 | 1505 | int i, ret; |
e1429b4c BS |
1506 | |
1507 | /* as long as the bo isn't in vram, and isn't tiled, we've got | |
1508 | * nothing to do here. | |
1509 | */ | |
1510 | if (bo->mem.mem_type != TTM_PL_VRAM) { | |
1167c6bc | 1511 | if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || |
7760a2e3 | 1512 | !nvbo->kind) |
e1429b4c | 1513 | return 0; |
a5540906 ML |
1514 | |
1515 | if (bo->mem.mem_type == TTM_PL_SYSTEM) { | |
1516 | nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); | |
1517 | ||
1518 | ret = nouveau_bo_validate(nvbo, false, false); | |
1519 | if (ret) | |
1520 | return ret; | |
1521 | } | |
1522 | return 0; | |
e1429b4c BS |
1523 | } |
1524 | ||
1525 | /* make sure bo is in mappable vram */ | |
1167c6bc | 1526 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || |
a5540906 | 1527 | bo->mem.start + bo->mem.num_pages < mappable) |
e1429b4c BS |
1528 | return 0; |
1529 | ||
f1217ed0 CK |
1530 | for (i = 0; i < nvbo->placement.num_placement; ++i) { |
1531 | nvbo->placements[i].fpfn = 0; | |
1532 | nvbo->placements[i].lpfn = mappable; | |
1533 | } | |
1534 | ||
1535 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { | |
1536 | nvbo->busy_placements[i].fpfn = 0; | |
1537 | nvbo->busy_placements[i].lpfn = mappable; | |
1538 | } | |
e1429b4c | 1539 | |
c284815d | 1540 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); |
97a875cb | 1541 | return nouveau_bo_validate(nvbo, false, false); |
f32f02fd JG |
1542 | } |
1543 | ||
3230cfc3 KRW |
1544 | static int |
1545 | nouveau_ttm_tt_populate(struct ttm_tt *ttm) | |
1546 | { | |
8e7e7052 | 1547 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1548 | struct nouveau_drm *drm; |
359088d5 | 1549 | struct device *dev; |
3230cfc3 KRW |
1550 | unsigned i; |
1551 | int r; | |
22b33e8e | 1552 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
3230cfc3 KRW |
1553 | |
1554 | if (ttm->state != tt_unpopulated) | |
1555 | return 0; | |
1556 | ||
22b33e8e DA |
1557 | if (slave && ttm->sg) { |
1558 | /* make userspace faulting work */ | |
1559 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
1560 | ttm_dma->dma_address, ttm->num_pages); | |
1561 | ttm->state = tt_unbound; | |
1562 | return 0; | |
1563 | } | |
1564 | ||
ebb945a9 | 1565 | drm = nouveau_bdev(ttm->bdev); |
359088d5 | 1566 | dev = drm->dev->dev; |
3230cfc3 | 1567 | |
a7fb8a23 | 1568 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1569 | if (drm->agp.bridge) { |
dea7e0ac JG |
1570 | return ttm_agp_tt_populate(ttm); |
1571 | } | |
1572 | #endif | |
1573 | ||
9bcd38de | 1574 | #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) |
3230cfc3 | 1575 | if (swiotlb_nr_tbl()) { |
359088d5 | 1576 | return ttm_dma_populate((void *)ttm, dev); |
3230cfc3 KRW |
1577 | } |
1578 | #endif | |
1579 | ||
1580 | r = ttm_pool_populate(ttm); | |
1581 | if (r) { | |
1582 | return r; | |
1583 | } | |
1584 | ||
1585 | for (i = 0; i < ttm->num_pages; i++) { | |
fd1496a0 AC |
1586 | dma_addr_t addr; |
1587 | ||
359088d5 | 1588 | addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE, |
fd1496a0 AC |
1589 | DMA_BIDIRECTIONAL); |
1590 | ||
359088d5 | 1591 | if (dma_mapping_error(dev, addr)) { |
4fbbed46 | 1592 | while (i--) { |
359088d5 | 1593 | dma_unmap_page(dev, ttm_dma->dma_address[i], |
fd1496a0 | 1594 | PAGE_SIZE, DMA_BIDIRECTIONAL); |
8e7e7052 | 1595 | ttm_dma->dma_address[i] = 0; |
3230cfc3 KRW |
1596 | } |
1597 | ttm_pool_unpopulate(ttm); | |
1598 | return -EFAULT; | |
1599 | } | |
fd1496a0 AC |
1600 | |
1601 | ttm_dma->dma_address[i] = addr; | |
3230cfc3 KRW |
1602 | } |
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | static void | |
1607 | nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
1608 | { | |
8e7e7052 | 1609 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1610 | struct nouveau_drm *drm; |
359088d5 | 1611 | struct device *dev; |
3230cfc3 | 1612 | unsigned i; |
22b33e8e DA |
1613 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
1614 | ||
1615 | if (slave) | |
1616 | return; | |
3230cfc3 | 1617 | |
ebb945a9 | 1618 | drm = nouveau_bdev(ttm->bdev); |
359088d5 | 1619 | dev = drm->dev->dev; |
3230cfc3 | 1620 | |
a7fb8a23 | 1621 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1622 | if (drm->agp.bridge) { |
dea7e0ac JG |
1623 | ttm_agp_tt_unpopulate(ttm); |
1624 | return; | |
1625 | } | |
1626 | #endif | |
1627 | ||
9bcd38de | 1628 | #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) |
3230cfc3 | 1629 | if (swiotlb_nr_tbl()) { |
359088d5 | 1630 | ttm_dma_unpopulate((void *)ttm, dev); |
3230cfc3 KRW |
1631 | return; |
1632 | } | |
1633 | #endif | |
1634 | ||
1635 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 | 1636 | if (ttm_dma->dma_address[i]) { |
359088d5 | 1637 | dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE, |
fd1496a0 | 1638 | DMA_BIDIRECTIONAL); |
3230cfc3 KRW |
1639 | } |
1640 | } | |
1641 | ||
1642 | ttm_pool_unpopulate(ttm); | |
1643 | } | |
1644 | ||
875ac34a | 1645 | void |
809e9447 | 1646 | nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) |
875ac34a | 1647 | { |
29ba89b2 | 1648 | struct reservation_object *resv = nvbo->bo.resv; |
bdaf7ddf | 1649 | |
809e9447 ML |
1650 | if (exclusive) |
1651 | reservation_object_add_excl_fence(resv, &fence->base); | |
1652 | else if (fence) | |
1653 | reservation_object_add_shared_fence(resv, &fence->base); | |
875ac34a BS |
1654 | } |
1655 | ||
6ee73861 | 1656 | struct ttm_bo_driver nouveau_bo_driver = { |
649bf3ca | 1657 | .ttm_tt_create = &nouveau_ttm_tt_create, |
3230cfc3 KRW |
1658 | .ttm_tt_populate = &nouveau_ttm_tt_populate, |
1659 | .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, | |
6ee73861 BS |
1660 | .invalidate_caches = nouveau_bo_invalidate_caches, |
1661 | .init_mem_type = nouveau_bo_init_mem_type, | |
a2ab19fe | 1662 | .eviction_valuable = ttm_bo_eviction_valuable, |
6ee73861 | 1663 | .evict_flags = nouveau_bo_evict_flags, |
a4154bbf | 1664 | .move_notify = nouveau_bo_move_ntfy, |
6ee73861 BS |
1665 | .move = nouveau_bo_move, |
1666 | .verify_access = nouveau_bo_verify_access, | |
f32f02fd JG |
1667 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
1668 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, | |
1669 | .io_mem_free = &nouveau_ttm_io_mem_free, | |
ea642c32 | 1670 | .io_mem_pfn = ttm_bo_default_io_mem_pfn, |
6ee73861 | 1671 | }; |