[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_abi16.h

#ifndef __NOUVEAU_ABI16_H__
#define __NOUVEAU_ABI16_H__

#define ABI16_IOCTL_ARGS                                                       \
	struct drm_device *dev, void *data, struct drm_file *file_priv

int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);

struct nouveau_abi16_ntfy {
	struct nvif_object object;
	struct list_head head;
	struct nvkm_mm_node *node;
};

struct nouveau_abi16_chan {
	struct list_head head;
	struct nouveau_channel *chan;
	struct list_head notifiers;
	struct nouveau_bo *ntfy;
	struct nvkm_vma ntfy_vma;
	struct nvkm_mm  heap;
};

struct nouveau_abi16 {
	struct nvif_device device;
	struct list_head channels;
	u64 handles;
};

struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *);
int  nouveau_abi16_put(struct nouveau_abi16 *, int);
void nouveau_abi16_fini(struct nouveau_abi16 *);
s32  nouveau_abi16_swclass(struct nouveau_drm *);
int  nouveau_abi16_usif(struct drm_file *, void *data, u32 size);

#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)

struct drm_nouveau_channel_alloc {
	uint32_t     fb_ctxdma_handle;
	uint32_t     tt_ctxdma_handle;

	int          channel;
	uint32_t     pushbuf_domains;

	/* Notifier memory */
	uint32_t     notifier_handle;

	/* DRM-enforced subchannel assignments */
	struct {
		uint32_t handle;
		uint32_t grclass;
	} subchan[8];
	uint32_t nr_subchan;
};

struct drm_nouveau_channel_free {
	int channel;
};

struct drm_nouveau_grobj_alloc {
	int      channel;
	uint32_t handle;
	int      class;
};

struct drm_nouveau_notifierobj_alloc {
	uint32_t channel;
	uint32_t handle;
	uint32_t size;
	uint32_t offset;
};

struct drm_nouveau_gpuobj_free {
	int      channel;
	uint32_t handle;
};

#define NOUVEAU_GETPARAM_PCI_VENDOR      3
#define NOUVEAU_GETPARAM_PCI_DEVICE      4
#define NOUVEAU_GETPARAM_BUS_TYPE        5
#define NOUVEAU_GETPARAM_FB_SIZE         8
#define NOUVEAU_GETPARAM_AGP_SIZE        9
#define NOUVEAU_GETPARAM_CHIPSET_ID      11
#define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
#define NOUVEAU_GETPARAM_GRAPH_UNITS     13
#define NOUVEAU_GETPARAM_PTIMER_TIME     14
#define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
#define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
struct drm_nouveau_getparam {
	uint64_t param;
	uint64_t value;
};

struct drm_nouveau_setparam {
	uint64_t param;
	uint64_t value;
};

#define DRM_IOCTL_NOUVEAU_GETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
#define DRM_IOCTL_NOUVEAU_SETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC  DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)

#endif
Commit	Line	Data
2a259a3d BS	1	#ifndef __NOUVEAU_ABI16_H__
	2	#define __NOUVEAU_ABI16_H__
	3
	4	#define ABI16_IOCTL_ARGS \
	5	struct drm_device dev, void data, struct drm_file *file_priv
ebb945a9	6
2a259a3d BS	7	int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
	8	int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
	9	int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
	10	int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
	11	int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
	12	int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
	13	int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
	14
ebb945a9	15	struct nouveau_abi16_ntfy {
a01ca78c	16	struct nvif_object object;
ebb945a9	17	struct list_head head;
be83cd4e	18	struct nvkm_mm_node *node;
ebb945a9 BS	19	};
	20
	21	struct nouveau_abi16_chan {
	22	struct list_head head;
	23	struct nouveau_channel *chan;
	24	struct list_head notifiers;
	25	struct nouveau_bo *ntfy;
be83cd4e BS	26	struct nvkm_vma ntfy_vma;
be83cd4e BS	27	struct nvkm_mm heap;
ebb945a9 BS	28	};
	29
	30	struct nouveau_abi16 {
967e7bde	31	struct nvif_device device;
ebb945a9 BS	32	struct list_head channels;
	33	u64 handles;
	34	};
	35
09433f24	36	struct nouveau_abi16 nouveau_abi16_get(struct drm_file );
ebb945a9 BS	37	int nouveau_abi16_put(struct nouveau_abi16 *, int);
ebb945a9 BS	38	void nouveau_abi16_fini(struct nouveau_abi16 *);
f58ddf95	39	s32 nouveau_abi16_swclass(struct nouveau_drm *);
2621a416	40	int nouveau_abi16_usif(struct drm_file , void data, u32 size);
ebb945a9 BS	41
	42	#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
	43	#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
	44
2a259a3d BS	45	struct drm_nouveau_channel_alloc {
	46	uint32_t fb_ctxdma_handle;
	47	uint32_t tt_ctxdma_handle;
	48
	49	int channel;
	50	uint32_t pushbuf_domains;
	51
	52	/* Notifier memory */
	53	uint32_t notifier_handle;
	54
	55	/* DRM-enforced subchannel assignments */
	56	struct {
	57	uint32_t handle;
	58	uint32_t grclass;
	59	} subchan[8];
	60	uint32_t nr_subchan;
	61	};
	62
	63	struct drm_nouveau_channel_free {
	64	int channel;
	65	};
	66
	67	struct drm_nouveau_grobj_alloc {
	68	int channel;
	69	uint32_t handle;
	70	int class;
	71	};
	72
	73	struct drm_nouveau_notifierobj_alloc {
	74	uint32_t channel;
	75	uint32_t handle;
	76	uint32_t size;
	77	uint32_t offset;
	78	};
	79
	80	struct drm_nouveau_gpuobj_free {
	81	int channel;
	82	uint32_t handle;
	83	};
	84
	85	#define NOUVEAU_GETPARAM_PCI_VENDOR 3
	86	#define NOUVEAU_GETPARAM_PCI_DEVICE 4
	87	#define NOUVEAU_GETPARAM_BUS_TYPE 5
	88	#define NOUVEAU_GETPARAM_FB_SIZE 8
	89	#define NOUVEAU_GETPARAM_AGP_SIZE 9
	90	#define NOUVEAU_GETPARAM_CHIPSET_ID 11
	91	#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
	92	#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
	93	#define NOUVEAU_GETPARAM_PTIMER_TIME 14
	94	#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
	95	#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
	96	struct drm_nouveau_getparam {
	97	uint64_t param;
	98	uint64_t value;
	99	};
	100
	101	struct drm_nouveau_setparam {
	102	uint64_t param;
	103	uint64_t value;
	104	};
	105
	106	#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
	107	#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
	108	#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
109	#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
110	#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
111	#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
112	#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
113
114	#endif