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b7019ac5 | 1 | /* SPDX-License-Identifier: MIT */ |
5025407b BS |
2 | #ifndef __NVKM_DEVICE_H__ |
3 | #define __NVKM_DEVICE_H__ | |
4246b92c | 4 | #include <core/oclass.h> |
727fd72f | 5 | #include <core/intr.h> |
f483253f | 6 | enum nvkm_subdev_type; |
9274f4a9 | 7 | |
26c9e8ef BS |
8 | enum nvkm_device_type { |
9 | NVKM_DEVICE_PCI, | |
10 | NVKM_DEVICE_AGP, | |
11 | NVKM_DEVICE_PCIE, | |
12 | NVKM_DEVICE_TEGRA, | |
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13 | }; |
14 | ||
5025407b | 15 | struct nvkm_device { |
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16 | const struct nvkm_device_func *func; |
17 | const struct nvkm_device_quirk *quirk; | |
18 | struct device *dev; | |
26c9e8ef | 19 | enum nvkm_device_type type; |
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20 | u64 handle; |
21 | const char *name; | |
22 | const char *cfgopt; | |
23 | const char *dbgopt; | |
24 | ||
9274f4a9 | 25 | struct list_head head; |
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26 | struct mutex mutex; |
27 | int refcount; | |
9274f4a9 | 28 | |
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29 | void __iomem *pri; |
30 | ||
68f3f702 | 31 | u32 debug; |
9274f4a9 | 32 | |
6cf813fb | 33 | const struct nvkm_device_chip *chip; |
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34 | enum { |
35 | NV_04 = 0x04, | |
36 | NV_10 = 0x10, | |
4a0ff754 | 37 | NV_11 = 0x11, |
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38 | NV_20 = 0x20, |
39 | NV_30 = 0x30, | |
40 | NV_40 = 0x40, | |
41 | NV_50 = 0x50, | |
42 | NV_C0 = 0xc0, | |
9274f4a9 | 43 | NV_E0 = 0xe0, |
3f204647 | 44 | GM100 = 0x110, |
7f53abdb | 45 | GP100 = 0x130, |
c1f856bb | 46 | GV100 = 0x140, |
344d9c8f | 47 | TU100 = 0x160, |
3b050680 | 48 | GA100 = 0x170, |
176fdcbd | 49 | AD100 = 0x190, |
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50 | } card_type; |
51 | u32 chipset; | |
3704791d | 52 | u8 chiprev; |
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53 | u32 crystal; |
54 | ||
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55 | struct { |
56 | struct notifier_block nb; | |
57 | } acpi; | |
741d778e | 58 | |
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59 | #define NVKM_LAYOUT_ONCE(type,data,ptr) data *ptr; |
60 | #define NVKM_LAYOUT_INST(type,data,ptr,cnt) data *ptr[cnt]; | |
61 | #include <core/layout.h> | |
62 | #undef NVKM_LAYOUT_INST | |
63 | #undef NVKM_LAYOUT_ONCE | |
54d10db1 | 64 | struct list_head subdev; |
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65 | |
66 | struct { | |
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67 | struct list_head intr; |
68 | struct list_head prio[NVKM_INTR_PRIO_NR]; | |
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69 | spinlock_t lock; |
70 | int irq; | |
71 | bool alloc; | |
72 | bool armed; | |
a7ab200a | 73 | bool legacy_done; |
727fd72f | 74 | } intr; |
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75 | }; |
76 | ||
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77 | struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int type, int inst); |
78 | struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int type, int inst); | |
6cf813fb | 79 | |
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80 | struct nvkm_device_func { |
81 | struct nvkm_device_pci *(*pci)(struct nvkm_device *); | |
82 | struct nvkm_device_tegra *(*tegra)(struct nvkm_device *); | |
83 | void *(*dtor)(struct nvkm_device *); | |
84 | int (*preinit)(struct nvkm_device *); | |
2b700825 | 85 | int (*init)(struct nvkm_device *); |
7974dd1b | 86 | void (*fini)(struct nvkm_device *, bool suspend); |
727fd72f | 87 | int (*irq)(struct nvkm_device *); |
7e8820fe BS |
88 | resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar); |
89 | resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar); | |
bad3d80f | 90 | bool cpu_coherent; |
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91 | }; |
92 | ||
93 | struct nvkm_device_quirk { | |
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94 | u8 tv_pin_mask; |
95 | u8 tv_gpio; | |
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96 | }; |
97 | ||
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98 | struct nvkm_device_chip { |
99 | const char *name; | |
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100 | #define NVKM_LAYOUT_ONCE(type,data,ptr,...) \ |
101 | struct { \ | |
102 | u32 inst; \ | |
103 | int (*ctor)(struct nvkm_device *, enum nvkm_subdev_type, int inst, data **); \ | |
104 | } ptr; | |
105 | #define NVKM_LAYOUT_INST(A...) NVKM_LAYOUT_ONCE(A) | |
106 | #include <core/layout.h> | |
107 | #undef NVKM_LAYOUT_INST | |
108 | #undef NVKM_LAYOUT_ONCE | |
6cf813fb BS |
109 | }; |
110 | ||
5025407b | 111 | struct nvkm_device *nvkm_device_find(u64 name); |
803c1787 | 112 | |
dd646942 | 113 | /* privileged register interface accessor macros */ |
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114 | #define nvkm_rd08(d,a) ioread8((d)->pri + (a)) |
115 | #define nvkm_rd16(d,a) ioread16_native((d)->pri + (a)) | |
116 | #define nvkm_rd32(d,a) ioread32_native((d)->pri + (a)) | |
117 | #define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a)) | |
118 | #define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a)) | |
119 | #define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a)) | |
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120 | #define nvkm_mask(d,a,m,v) ({ \ |
121 | struct nvkm_device *_device = (d); \ | |
122 | u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \ | |
123 | nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \ | |
124 | _temp; \ | |
125 | }) | |
126 | ||
e781dc8f | 127 | void nvkm_device_del(struct nvkm_device **); |
6594363b | 128 | |
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129 | struct nvkm_device_oclass { |
130 | int (*ctor)(struct nvkm_device *, const struct nvkm_oclass *, | |
131 | void *data, u32 size, struct nvkm_object **); | |
132 | struct nvkm_sclass base; | |
133 | }; | |
134 | ||
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135 | extern const struct nvkm_sclass nvkm_udevice_sclass; |
136 | ||
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137 | /* device logging */ |
138 | #define nvdev_printk_(d,l,p,f,a...) do { \ | |
c1fcb148 | 139 | const struct nvkm_device *_device = (d); \ |
68f3f702 | 140 | if (_device->debug >= (l)) \ |
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141 | dev_##p(_device->dev, f, ##a); \ |
142 | } while(0) | |
143 | #define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a) | |
144 | #define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL, crit, f, ##a) | |
145 | #define nvdev_error(d,f,a...) nvdev_printk((d), ERROR, err, f, ##a) | |
146 | #define nvdev_warn(d,f,a...) nvdev_printk((d), WARN, notice, f, ##a) | |
147 | #define nvdev_info(d,f,a...) nvdev_printk((d), INFO, info, f, ##a) | |
148 | #define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG, info, f, ##a) | |
149 | #define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE, info, f, ##a) | |
150 | #define nvdev_spam(d,f,a...) nvdev_printk((d), SPAM, dbg, f, ##a) | |
9274f4a9 | 151 | #endif |