[linux-2.6-block.git] / drivers / gpu / drm / nouveau / include / nvkm / core / device.h

/* SPDX-License-Identifier: MIT */
#ifndef __NVKM_DEVICE_H__
#define __NVKM_DEVICE_H__
#include <core/oclass.h>
#include <core/event.h>

enum nvkm_devidx {
	NVKM_SUBDEV_PCI,
	NVKM_SUBDEV_VBIOS,
	NVKM_SUBDEV_DEVINIT,
	NVKM_SUBDEV_TOP,
	NVKM_SUBDEV_IBUS,
	NVKM_SUBDEV_GPIO,
	NVKM_SUBDEV_I2C,
	NVKM_SUBDEV_FUSE,
	NVKM_SUBDEV_MXM,
	NVKM_SUBDEV_MC,
	NVKM_SUBDEV_BUS,
	NVKM_SUBDEV_TIMER,
	NVKM_SUBDEV_INSTMEM,
	NVKM_SUBDEV_FB,
	NVKM_SUBDEV_LTC,
	NVKM_SUBDEV_MMU,
	NVKM_SUBDEV_BAR,
	NVKM_SUBDEV_FAULT,
	NVKM_SUBDEV_ACR,
	NVKM_SUBDEV_PMU,
	NVKM_SUBDEV_VOLT,
	NVKM_SUBDEV_ICCSENSE,
	NVKM_SUBDEV_THERM,
	NVKM_SUBDEV_CLK,
	NVKM_SUBDEV_GSP,

	NVKM_ENGINE_BSP,

	NVKM_ENGINE_CE0,
	NVKM_ENGINE_CE1,
	NVKM_ENGINE_CE2,
	NVKM_ENGINE_CE3,
	NVKM_ENGINE_CE4,
	NVKM_ENGINE_CE5,
	NVKM_ENGINE_CE6,
	NVKM_ENGINE_CE7,
	NVKM_ENGINE_CE8,
	NVKM_ENGINE_CE_LAST = NVKM_ENGINE_CE8,

	NVKM_ENGINE_CIPHER,
	NVKM_ENGINE_DISP,
	NVKM_ENGINE_DMAOBJ,
	NVKM_ENGINE_FIFO,
	NVKM_ENGINE_GR,
	NVKM_ENGINE_IFB,
	NVKM_ENGINE_ME,
	NVKM_ENGINE_MPEG,
	NVKM_ENGINE_MSENC,
	NVKM_ENGINE_MSPDEC,
	NVKM_ENGINE_MSPPP,
	NVKM_ENGINE_MSVLD,

	NVKM_ENGINE_NVENC0,
	NVKM_ENGINE_NVENC1,
	NVKM_ENGINE_NVENC2,
	NVKM_ENGINE_NVENC_LAST = NVKM_ENGINE_NVENC2,

	NVKM_ENGINE_NVDEC0,
	NVKM_ENGINE_NVDEC1,
	NVKM_ENGINE_NVDEC2,
	NVKM_ENGINE_NVDEC_LAST = NVKM_ENGINE_NVDEC2,

	NVKM_ENGINE_PM,
	NVKM_ENGINE_SEC,
	NVKM_ENGINE_SEC2,
	NVKM_ENGINE_SW,
	NVKM_ENGINE_VIC,
	NVKM_ENGINE_VP,

	NVKM_SUBDEV_NR
};

enum nvkm_device_type {
	NVKM_DEVICE_PCI,
	NVKM_DEVICE_AGP,
	NVKM_DEVICE_PCIE,
	NVKM_DEVICE_TEGRA,
};

struct nvkm_device {
	const struct nvkm_device_func *func;
	const struct nvkm_device_quirk *quirk;
	struct device *dev;
	enum nvkm_device_type type;
	u64 handle;
	const char *name;
	const char *cfgopt;
	const char *dbgopt;

	struct list_head head;
	struct mutex mutex;
	int refcount;

	void __iomem *pri;

	struct nvkm_event event;

	u64 disable_mask;
	u32 debug;

	const struct nvkm_device_chip *chip;
	enum {
		NV_04    = 0x04,
		NV_10    = 0x10,
		NV_11    = 0x11,
		NV_20    = 0x20,
		NV_30    = 0x30,
		NV_40    = 0x40,
		NV_50    = 0x50,
		NV_C0    = 0xc0,
		NV_E0    = 0xe0,
		GM100    = 0x110,
		GP100    = 0x130,
		GV100    = 0x140,
		TU100    = 0x160,
		GA100    = 0x170,
	} card_type;
	u32 chipset;
	u8  chiprev;
	u32 crystal;

	struct {
		struct notifier_block nb;
	} acpi;

	struct nvkm_acr *acr;
	struct nvkm_bar *bar;
	struct nvkm_bios *bios;
	struct nvkm_bus *bus;
	struct nvkm_clk *clk;
	struct nvkm_devinit *devinit;
	struct nvkm_fault *fault;
	struct nvkm_fb *fb;
	struct nvkm_fuse *fuse;
	struct nvkm_gpio *gpio;
	struct nvkm_gsp *gsp;
	struct nvkm_i2c *i2c;
	struct nvkm_subdev *ibus;
	struct nvkm_iccsense *iccsense;
	struct nvkm_instmem *imem;
	struct nvkm_ltc *ltc;
	struct nvkm_mc *mc;
	struct nvkm_mmu *mmu;
	struct nvkm_subdev *mxm;
	struct nvkm_pci *pci;
	struct nvkm_pmu *pmu;
	struct nvkm_therm *therm;
	struct nvkm_timer *timer;
	struct nvkm_top *top;
	struct nvkm_volt *volt;

	struct nvkm_engine *bsp;
	struct nvkm_engine *ce[9];
	struct nvkm_engine *cipher;
	struct nvkm_disp *disp;
	struct nvkm_dma *dma;
	struct nvkm_fifo *fifo;
	struct nvkm_gr *gr;
	struct nvkm_engine *ifb;
	struct nvkm_engine *me;
	struct nvkm_engine *mpeg;
	struct nvkm_engine *msenc;
	struct nvkm_engine *mspdec;
	struct nvkm_engine *msppp;
	struct nvkm_engine *msvld;
	struct nvkm_nvenc *nvenc[3];
	struct nvkm_nvdec *nvdec[3];
	struct nvkm_pm *pm;
	struct nvkm_engine *sec;
	struct nvkm_sec2 *sec2;
	struct nvkm_sw *sw;
	struct nvkm_engine *vic;
	struct nvkm_engine *vp;
};

struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index);
struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index);

struct nvkm_device_func {
	struct nvkm_device_pci *(*pci)(struct nvkm_device *);
	struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
	void *(*dtor)(struct nvkm_device *);
	int (*preinit)(struct nvkm_device *);
	int (*init)(struct nvkm_device *);
	void (*fini)(struct nvkm_device *, bool suspend);
	resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar);
	resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar);
	bool cpu_coherent;
};

struct nvkm_device_quirk {
	u8 tv_pin_mask;
	u8 tv_gpio;
};

struct nvkm_device_chip {
	const char *name;

	int (*acr     )(struct nvkm_device *, int idx, struct nvkm_acr **);
	int (*bar     )(struct nvkm_device *, int idx, struct nvkm_bar **);
	int (*bios    )(struct nvkm_device *, int idx, struct nvkm_bios **);
	int (*bus     )(struct nvkm_device *, int idx, struct nvkm_bus **);
	int (*clk     )(struct nvkm_device *, int idx, struct nvkm_clk **);
	int (*devinit )(struct nvkm_device *, int idx, struct nvkm_devinit **);
	int (*fault   )(struct nvkm_device *, int idx, struct nvkm_fault **);
	int (*fb      )(struct nvkm_device *, int idx, struct nvkm_fb **);
	int (*fuse    )(struct nvkm_device *, int idx, struct nvkm_fuse **);
	int (*gpio    )(struct nvkm_device *, int idx, struct nvkm_gpio **);
	int (*gsp     )(struct nvkm_device *, int idx, struct nvkm_gsp **);
	int (*i2c     )(struct nvkm_device *, int idx, struct nvkm_i2c **);
	int (*ibus    )(struct nvkm_device *, int idx, struct nvkm_subdev **);
	int (*iccsense)(struct nvkm_device *, int idx, struct nvkm_iccsense **);
	int (*imem    )(struct nvkm_device *, int idx, struct nvkm_instmem **);
	int (*ltc     )(struct nvkm_device *, int idx, struct nvkm_ltc **);
	int (*mc      )(struct nvkm_device *, int idx, struct nvkm_mc **);
	int (*mmu     )(struct nvkm_device *, int idx, struct nvkm_mmu **);
	int (*mxm     )(struct nvkm_device *, int idx, struct nvkm_subdev **);
	int (*pci     )(struct nvkm_device *, int idx, struct nvkm_pci **);
	int (*pmu     )(struct nvkm_device *, int idx, struct nvkm_pmu **);
	int (*therm   )(struct nvkm_device *, int idx, struct nvkm_therm **);
	int (*timer   )(struct nvkm_device *, int idx, struct nvkm_timer **);
	int (*top     )(struct nvkm_device *, int idx, struct nvkm_top **);
	int (*volt    )(struct nvkm_device *, int idx, struct nvkm_volt **);

	int (*bsp     )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*ce[9]   )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*cipher  )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*disp    )(struct nvkm_device *, int idx, struct nvkm_disp **);
	int (*dma     )(struct nvkm_device *, int idx, struct nvkm_dma **);
	int (*fifo    )(struct nvkm_device *, int idx, struct nvkm_fifo **);
	int (*gr      )(struct nvkm_device *, int idx, struct nvkm_gr **);
	int (*ifb     )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*me      )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*mpeg    )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*msenc   )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*mspdec  )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*msppp   )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*msvld   )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **);
	int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **);
	int (*pm      )(struct nvkm_device *, int idx, struct nvkm_pm **);
	int (*sec     )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*sec2    )(struct nvkm_device *, int idx, struct nvkm_sec2 **);
	int (*sw      )(struct nvkm_device *, int idx, struct nvkm_sw **);
	int (*vic     )(struct nvkm_device *, int idx, struct nvkm_engine **);
	int (*vp      )(struct nvkm_device *, int idx, struct nvkm_engine **);
};

struct nvkm_device *nvkm_device_find(u64 name);
int nvkm_device_list(u64 *name, int size);

/* privileged register interface accessor macros */
#define nvkm_rd08(d,a) ioread8((d)->pri + (a))
#define nvkm_rd16(d,a) ioread16_native((d)->pri + (a))
#define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))
#define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
#define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
#define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
#define nvkm_mask(d,a,m,v) ({                                                  \
	struct nvkm_device *_device = (d);                                     \
	u32 _addr = (a), _temp = nvkm_rd32(_device, _addr);                    \
	nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v));                       \
	_temp;                                                                 \
})

void nvkm_device_del(struct nvkm_device **);

struct nvkm_device_oclass {
	int (*ctor)(struct nvkm_device *, const struct nvkm_oclass *,
		    void *data, u32 size, struct nvkm_object **);
	struct nvkm_sclass base;
};

extern const struct nvkm_sclass nvkm_udevice_sclass;

/* device logging */
#define nvdev_printk_(d,l,p,f,a...) do {                                       \
	const struct nvkm_device *_device = (d);                               \
	if (_device->debug >= (l))                                             \
		dev_##p(_device->dev, f, ##a);                                 \
} while(0)
#define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
#define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL,   crit, f, ##a)
#define nvdev_error(d,f,a...) nvdev_printk((d), ERROR,    err, f, ##a)
#define nvdev_warn(d,f,a...)  nvdev_printk((d),  WARN, notice, f, ##a)
#define nvdev_info(d,f,a...)  nvdev_printk((d),  INFO,   info, f, ##a)
#define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG,   info, f, ##a)
#define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE,   info, f, ##a)
#define nvdev_spam(d,f,a...)  nvdev_printk((d),  SPAM,    dbg, f, ##a)
#endif
Commit	Line	Data
b7019ac5	1	/* SPDX-License-Identifier: MIT */
5025407b BS	2	#ifndef __NVKM_DEVICE_H__
5025407b BS	3	#define __NVKM_DEVICE_H__
4246b92c	4	#include <core/oclass.h>
ed76a870	5	#include <core/event.h>
9274f4a9	6
9ace404b	7	enum nvkm_devidx {
0a34fb31	8	NVKM_SUBDEV_PCI,
68f3f702 BS	9	NVKM_SUBDEV_VBIOS,
68f3f702 BS	10	NVKM_SUBDEV_DEVINIT,
eaebfcc3	11	NVKM_SUBDEV_TOP,
68f3f702 BS	12	NVKM_SUBDEV_IBUS,
	13	NVKM_SUBDEV_GPIO,
	14	NVKM_SUBDEV_I2C,
	15	NVKM_SUBDEV_FUSE,
	16	NVKM_SUBDEV_MXM,
	17	NVKM_SUBDEV_MC,
	18	NVKM_SUBDEV_BUS,
	19	NVKM_SUBDEV_TIMER,
77154fd9	20	NVKM_SUBDEV_INSTMEM,
68f3f702 BS	21	NVKM_SUBDEV_FB,
68f3f702 BS	22	NVKM_SUBDEV_LTC,
68f3f702 BS	23	NVKM_SUBDEV_MMU,
68f3f702 BS	24	NVKM_SUBDEV_BAR,
1ce46689	25	NVKM_SUBDEV_FAULT,
31bef57f	26	NVKM_SUBDEV_ACR,
68f3f702 BS	27	NVKM_SUBDEV_PMU,
68f3f702 BS	28	NVKM_SUBDEV_VOLT,
dc06e366	29	NVKM_SUBDEV_ICCSENSE,
68f3f702 BS	30	NVKM_SUBDEV_THERM,
68f3f702 BS	31	NVKM_SUBDEV_CLK,
78cdadb8	32	NVKM_SUBDEV_GSP,
68f3f702	33
68f3f702	34	NVKM_ENGINE_BSP,
7cee0433	35
68f3f702 BS	36	NVKM_ENGINE_CE0,
	37	NVKM_ENGINE_CE1,
	38	NVKM_ENGINE_CE2,
34bf50cd BS	39	NVKM_ENGINE_CE3,
	40	NVKM_ENGINE_CE4,
	41	NVKM_ENGINE_CE5,
890c85f3 BS	42	NVKM_ENGINE_CE6,
	43	NVKM_ENGINE_CE7,
	44	NVKM_ENGINE_CE8,
	45	NVKM_ENGINE_CE_LAST = NVKM_ENGINE_CE8,
7cee0433 BS	46
7cee0433 BS	47	NVKM_ENGINE_CIPHER,
68f3f702	48	NVKM_ENGINE_DISP,
7cee0433 BS	49	NVKM_ENGINE_DMAOBJ,
	50	NVKM_ENGINE_FIFO,
	51	NVKM_ENGINE_GR,
	52	NVKM_ENGINE_IFB,
	53	NVKM_ENGINE_ME,
	54	NVKM_ENGINE_MPEG,
	55	NVKM_ENGINE_MSENC,
	56	NVKM_ENGINE_MSPDEC,
	57	NVKM_ENGINE_MSPPP,
68f3f702	58	NVKM_ENGINE_MSVLD,
294af04b BS	59
	60	NVKM_ENGINE_NVENC0,
	61	NVKM_ENGINE_NVENC1,
cb7b5ea9 BS	62	NVKM_ENGINE_NVENC2,
cb7b5ea9 BS	63	NVKM_ENGINE_NVENC_LAST = NVKM_ENGINE_NVENC2,
294af04b	64
936a1678 BS	65	NVKM_ENGINE_NVDEC0,
936a1678 BS	66	NVKM_ENGINE_NVDEC1,
2d583ade BS	67	NVKM_ENGINE_NVDEC2,
2d583ade BS	68	NVKM_ENGINE_NVDEC_LAST = NVKM_ENGINE_NVDEC2,
936a1678	69
7cee0433	70	NVKM_ENGINE_PM,
68f3f702	71	NVKM_ENGINE_SEC,
b62880f7	72	NVKM_ENGINE_SEC2,
7cee0433 BS	73	NVKM_ENGINE_SW,
	74	NVKM_ENGINE_VIC,
	75	NVKM_ENGINE_VP,
68f3f702	76
26c9e8ef BS	77	NVKM_SUBDEV_NR
	78	};
	79
	80	enum nvkm_device_type {
	81	NVKM_DEVICE_PCI,
	82	NVKM_DEVICE_AGP,
	83	NVKM_DEVICE_PCIE,
	84	NVKM_DEVICE_TEGRA,
9ace404b BS	85	};
9ace404b BS	86
5025407b	87	struct nvkm_device {
7974dd1b BS	88	const struct nvkm_device_func *func;
	89	const struct nvkm_device_quirk *quirk;
	90	struct device *dev;
26c9e8ef	91	enum nvkm_device_type type;
7974dd1b BS	92	u64 handle;
	93	const char *name;
	94	const char *cfgopt;
	95	const char *dbgopt;
	96
9274f4a9	97	struct list_head head;
a1e88736 BS	98	struct mutex mutex;
a1e88736 BS	99	int refcount;
9274f4a9	100
2ebfa1bc BS	101	void __iomem *pri;
2ebfa1bc BS	102
79ca2770	103	struct nvkm_event event;
ed76a870	104
f0d13e3a	105	u64 disable_mask;
68f3f702	106	u32 debug;
9274f4a9	107
6cf813fb	108	const struct nvkm_device_chip *chip;
9274f4a9 BS	109	enum {
	110	NV_04 = 0x04,
	111	NV_10 = 0x10,
4a0ff754	112	NV_11 = 0x11,
9274f4a9 BS	113	NV_20 = 0x20,
	114	NV_30 = 0x30,
	115	NV_40 = 0x40,
	116	NV_50 = 0x50,
	117	NV_C0 = 0xc0,
9274f4a9	118	NV_E0 = 0xe0,
3f204647	119	GM100 = 0x110,
7f53abdb	120	GP100 = 0x130,
c1f856bb	121	GV100 = 0x140,
344d9c8f	122	TU100 = 0x160,
3b050680	123	GA100 = 0x170,
9274f4a9 BS	124	} card_type;
9274f4a9 BS	125	u32 chipset;
3704791d	126	u8 chiprev;
9274f4a9 BS	127	u32 crystal;
9274f4a9 BS	128
ed76a870 BS	129	struct {
	130	struct notifier_block nb;
	131	} acpi;
741d778e	132
31bef57f	133	struct nvkm_acr *acr;
741d778e BS	134	struct nvkm_bar *bar;
	135	struct nvkm_bios *bios;
	136	struct nvkm_bus *bus;
	137	struct nvkm_clk *clk;
	138	struct nvkm_devinit *devinit;
1ce46689	139	struct nvkm_fault *fault;
741d778e BS	140	struct nvkm_fb *fb;
	141	struct nvkm_fuse *fuse;
	142	struct nvkm_gpio *gpio;
78cdadb8	143	struct nvkm_gsp *gsp;
741d778e BS	144	struct nvkm_i2c *i2c;
741d778e BS	145	struct nvkm_subdev *ibus;
dc06e366	146	struct nvkm_iccsense *iccsense;
741d778e BS	147	struct nvkm_instmem *imem;
	148	struct nvkm_ltc *ltc;
	149	struct nvkm_mc *mc;
	150	struct nvkm_mmu *mmu;
	151	struct nvkm_subdev *mxm;
0a34fb31	152	struct nvkm_pci *pci;
741d778e BS	153	struct nvkm_pmu *pmu;
	154	struct nvkm_therm *therm;
	155	struct nvkm_timer *timer;
eaebfcc3	156	struct nvkm_top *top;
741d778e BS	157	struct nvkm_volt *volt;
	158
	159	struct nvkm_engine *bsp;
890c85f3	160	struct nvkm_engine *ce[9];
741d778e BS	161	struct nvkm_engine *cipher;
741d778e BS	162	struct nvkm_disp *disp;
19fef52d	163	struct nvkm_dma *dma;
741d778e BS	164	struct nvkm_fifo *fifo;
	165	struct nvkm_gr *gr;
	166	struct nvkm_engine *ifb;
	167	struct nvkm_engine *me;
	168	struct nvkm_engine *mpeg;
	169	struct nvkm_engine *msenc;
	170	struct nvkm_engine *mspdec;
	171	struct nvkm_engine *msppp;
	172	struct nvkm_engine *msvld;
10e43bfd	173	struct nvkm_nvenc *nvenc[3];
2d583ade	174	struct nvkm_nvdec *nvdec[3];
741d778e BS	175	struct nvkm_pm *pm;
741d778e BS	176	struct nvkm_engine *sec;
b62880f7	177	struct nvkm_sec2 *sec2;
741d778e BS	178	struct nvkm_sw *sw;
	179	struct nvkm_engine *vic;
	180	struct nvkm_engine *vp;
9274f4a9 BS	181	};
9274f4a9 BS	182
6cf813fb BS	183	struct nvkm_subdev nvkm_device_subdev(struct nvkm_device , int index);
	184	struct nvkm_engine nvkm_device_engine(struct nvkm_device , int index);
	185
7974dd1b BS	186	struct nvkm_device_func {
	187	struct nvkm_device_pci (pci)(struct nvkm_device *);
	188	struct nvkm_device_tegra (tegra)(struct nvkm_device *);
	189	void (dtor)(struct nvkm_device *);
	190	int (preinit)(struct nvkm_device );
2b700825	191	int (init)(struct nvkm_device );
7974dd1b	192	void (fini)(struct nvkm_device , bool suspend);
7e8820fe BS	193	resource_size_t (resource_addr)(struct nvkm_device , unsigned bar);
7e8820fe BS	194	resource_size_t (resource_size)(struct nvkm_device , unsigned bar);
bad3d80f	195	bool cpu_coherent;
7974dd1b BS	196	};
	197
	198	struct nvkm_device_quirk {
c7af0ff0 BS	199	u8 tv_pin_mask;
c7af0ff0 BS	200	u8 tv_gpio;
7974dd1b BS	201	};
7974dd1b BS	202
6cf813fb BS	203	struct nvkm_device_chip {
	204	const char *name;
	205
31bef57f	206	int (acr )(struct nvkm_device , int idx, struct nvkm_acr **);
dc06e366 MP	207	int (bar )(struct nvkm_device , int idx, struct nvkm_bar **);
	208	int (bios )(struct nvkm_device , int idx, struct nvkm_bios **);
	209	int (bus )(struct nvkm_device , int idx, struct nvkm_bus **);
	210	int (clk )(struct nvkm_device , int idx, struct nvkm_clk **);
	211	int (devinit )(struct nvkm_device , int idx, struct nvkm_devinit **);
1ce46689	212	int (fault )(struct nvkm_device , int idx, struct nvkm_fault **);
dc06e366 MP	213	int (fb )(struct nvkm_device , int idx, struct nvkm_fb **);
	214	int (fuse )(struct nvkm_device , int idx, struct nvkm_fuse **);
	215	int (gpio )(struct nvkm_device , int idx, struct nvkm_gpio **);
78cdadb8	216	int (gsp )(struct nvkm_device , int idx, struct nvkm_gsp **);
dc06e366 MP	217	int (i2c )(struct nvkm_device , int idx, struct nvkm_i2c **);
	218	int (ibus )(struct nvkm_device , int idx, struct nvkm_subdev **);
	219	int (iccsense)(struct nvkm_device , int idx, struct nvkm_iccsense **);
	220	int (imem )(struct nvkm_device , int idx, struct nvkm_instmem **);
	221	int (ltc )(struct nvkm_device , int idx, struct nvkm_ltc **);
	222	int (mc )(struct nvkm_device , int idx, struct nvkm_mc **);
	223	int (mmu )(struct nvkm_device , int idx, struct nvkm_mmu **);
	224	int (mxm )(struct nvkm_device , int idx, struct nvkm_subdev **);
	225	int (pci )(struct nvkm_device , int idx, struct nvkm_pci **);
	226	int (pmu )(struct nvkm_device , int idx, struct nvkm_pmu **);
dc06e366 MP	227	int (therm )(struct nvkm_device , int idx, struct nvkm_therm **);
dc06e366 MP	228	int (timer )(struct nvkm_device , int idx, struct nvkm_timer **);
eaebfcc3	229	int (top )(struct nvkm_device , int idx, struct nvkm_top **);
dc06e366 MP	230	int (volt )(struct nvkm_device , int idx, struct nvkm_volt **);
	231
	232	int (bsp )(struct nvkm_device , int idx, struct nvkm_engine **);
890c85f3	233	int (ce[9] )(struct nvkm_device , int idx, struct nvkm_engine **);
dc06e366 MP	234	int (cipher )(struct nvkm_device , int idx, struct nvkm_engine **);
	235	int (disp )(struct nvkm_device , int idx, struct nvkm_disp **);
	236	int (dma )(struct nvkm_device , int idx, struct nvkm_dma **);
	237	int (fifo )(struct nvkm_device , int idx, struct nvkm_fifo **);
	238	int (gr )(struct nvkm_device , int idx, struct nvkm_gr **);
	239	int (ifb )(struct nvkm_device , int idx, struct nvkm_engine **);
	240	int (me )(struct nvkm_device , int idx, struct nvkm_engine **);
	241	int (mpeg )(struct nvkm_device , int idx, struct nvkm_engine **);
	242	int (msenc )(struct nvkm_device , int idx, struct nvkm_engine **);
	243	int (mspdec )(struct nvkm_device , int idx, struct nvkm_engine **);
	244	int (msppp )(struct nvkm_device , int idx, struct nvkm_engine **);
	245	int (msvld )(struct nvkm_device , int idx, struct nvkm_engine **);
10e43bfd	246	int (nvenc[3])(struct nvkm_device , int idx, struct nvkm_nvenc **);
2d583ade	247	int (nvdec[3])(struct nvkm_device , int idx, struct nvkm_nvdec **);
dc06e366 MP	248	int (pm )(struct nvkm_device , int idx, struct nvkm_pm **);
dc06e366 MP	249	int (sec )(struct nvkm_device , int idx, struct nvkm_engine **);
b62880f7	250	int (sec2 )(struct nvkm_device , int idx, struct nvkm_sec2 **);
dc06e366 MP	251	int (sw )(struct nvkm_device , int idx, struct nvkm_sw **);
	252	int (vic )(struct nvkm_device , int idx, struct nvkm_engine **);
	253	int (vp )(struct nvkm_device , int idx, struct nvkm_engine **);
6cf813fb BS	254	};
6cf813fb BS	255
5025407b BS	256	struct nvkm_device *nvkm_device_find(u64 name);
5025407b BS	257	int nvkm_device_list(u64 *name, int size);
803c1787	258
dd646942	259	/* privileged register interface accessor macros */
2ebfa1bc BS	260	#define nvkm_rd08(d,a) ioread8((d)->pri + (a))
	261	#define nvkm_rd16(d,a) ioread16_native((d)->pri + (a))
	262	#define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))
	263	#define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
	264	#define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
	265	#define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
dd646942 BS	266	#define nvkm_mask(d,a,m,v) ({ \
	267	struct nvkm_device *_device = (d); \
	268	u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \
	269	nvkm_wr32(_device, _addr, (_temp & ~(m)) \| (v)); \
	270	_temp; \
	271	})
	272
e781dc8f	273	void nvkm_device_del(struct nvkm_device **);
6594363b	274
0e29998a BS	275	struct nvkm_device_oclass {
	276	int (ctor)(struct nvkm_device , const struct nvkm_oclass *,
	277	void data, u32 size, struct nvkm_object *);
	278	struct nvkm_sclass base;
	279	};
	280
2a9f847f BS	281	extern const struct nvkm_sclass nvkm_udevice_sclass;
2a9f847f BS	282
6594363b BS	283	/* device logging */
6594363b BS	284	#define nvdev_printk_(d,l,p,f,a...) do { \
c1fcb148	285	const struct nvkm_device *_device = (d); \
68f3f702	286	if (_device->debug >= (l)) \
6594363b BS	287	dev_##p(_device->dev, f, ##a); \
	288	} while(0)
	289	#define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
	290	#define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL, crit, f, ##a)
	291	#define nvdev_error(d,f,a...) nvdev_printk((d), ERROR, err, f, ##a)
	292	#define nvdev_warn(d,f,a...) nvdev_printk((d), WARN, notice, f, ##a)
	293	#define nvdev_info(d,f,a...) nvdev_printk((d), INFO, info, f, ##a)
	294	#define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG, info, f, ##a)
	295	#define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE, info, f, ##a)
	296	#define nvdev_spam(d,f,a...) nvdev_printk((d), SPAM, dbg, f, ##a)
9274f4a9	297	#endif