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Merge tag 'm68k-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert...
[linux-block.git] / drivers / gpu / drm / nouveau / dispnv50 / disp.c
CommitLineData
56d237d2 1/*
26f6d88b
BS		 2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
1590700d
BS		 24#include "disp.h"
25#include "atom.h"
26#include "core.h"
27#include "head.h"
28#include "wndw.h"
0bc8ffe0 29#include "handles.h"
26f6d88b 30
51beb428 31#include <linux/dma-mapping.h>
34fd3e5d 32#include <linux/hdmi.h>
742db30c 33#include <linux/component.h>
6eca310e 34#include <linux/iopoll.h>
83fc083c 35
da68386d 36#include <drm/display/drm_dp_helper.h>
644edf52 37#include <drm/display/drm_scdc_helper.h>
eca22edb 38#include <drm/drm_atomic.h>
973f10c2 39#include <drm/drm_atomic_helper.h>
690ae20c 40#include <drm/drm_edid.h>
b516a9ef 41#include <drm/drm_fb_helper.h>
fcd70cd3 42#include <drm/drm_probe_helper.h>
690ae20c 43#include <drm/drm_vblank.h>
26f6d88b 44
0a960996
BS		 45#include <nvif/push507c.h>
46
1590700d
BS		 47#include <nvif/class.h>
48#include <nvif/cl0002.h>
1590700d 49#include <nvif/event.h>
f530bc60 50#include <nvif/if0012.h>
889fcbe9 51#include <nvif/if0014.h>
ed3d1489 52#include <nvif/timer.h>
f4778f08 53
0a960996 54#include <nvhw/class/cl507c.h>
344c2e5a
BS		 55#include <nvhw/class/cl507d.h>
56#include <nvhw/class/cl837d.h>
57#include <nvhw/class/cl887d.h>
58#include <nvhw/class/cl907d.h>
59#include <nvhw/class/cl917d.h>
0a960996 60
1590700d
BS		 61#include "nouveau_drv.h"
62#include "nouveau_dma.h"
63#include "nouveau_gem.h"
64#include "nouveau_connector.h"
65#include "nouveau_encoder.h"
66#include "nouveau_fence.h"
f4778f08 67
34508f9d
BS		 68#include <subdev/bios/dp.h>
69
1590700d
BS		 70/******************************************************************************
71 * EVO channel
72 *****************************************************************************/
3dbd036b
BS		 73
74static int
1590700d
BS		 75nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
76 const s32 *oclass, u8 head, void *data, u32 size,
77 struct nv50_chan *chan)
3dbd036b 78{
1590700d
BS		 79 struct nvif_sclass *sclass;
80 int ret, i, n;
839ca903 81
1590700d 82 chan->device = device;
ad633619 83
1590700d
BS		 84 ret = n = nvif_object_sclass_get(disp, &sclass);
85 if (ret < 0)
86 return ret;
ea8ee390 87
1590700d
BS		 88 while (oclass[0]) {
89 for (i = 0; i < n; i++) {
90 if (sclass[i].oclass == oclass[0]) {
9ac596a4
BS		 91 ret = nvif_object_ctor(disp, "kmsChan", 0,
92 oclass[0], data, size,
93 &chan->user);
1590700d
BS		 94 if (ret == 0)
95 nvif_object_map(&chan->user, NULL, 0);
96 nvif_object_sclass_put(&sclass);
97 return ret;
98 }
ea8ee390 99 }
1590700d 100 oclass++;
3dbd036b
BS		 101 }
102
1590700d
BS		 103 nvif_object_sclass_put(&sclass);
104 return -ENOSYS;
3dbd036b
BS		 105}
106
839ca903 107static void
1590700d 108nv50_chan_destroy(struct nv50_chan *chan)
839ca903 109{
9ac596a4 110 nvif_object_dtor(&chan->user);
839ca903
BS		 111}
112
1590700d
BS		 113/******************************************************************************
114 * DMA EVO channel
115 *****************************************************************************/
839ca903 116
1590700d
BS		 117void
118nv50_dmac_destroy(struct nv50_dmac *dmac)
839ca903 119{
9ac596a4
BS		 120 nvif_object_dtor(&dmac->vram);
121 nvif_object_dtor(&dmac->sync);
839ca903 122
1590700d 123 nv50_chan_destroy(&dmac->base);
839ca903 124
2853ccf0
BS		 125 nvif_mem_dtor(&dmac->_push.mem);
126}
127
128static void
129nv50_dmac_kick(struct nvif_push *push)
130{
131 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
0a960996 132
9cf06d6e 133 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
0a960996
BS		 134 if (dmac->put != dmac->cur) {
135 /* Push buffer fetches are not coherent with BAR1, we need to ensure
136 * writes have been flushed right through to VRAM before writing PUT.
137 */
138 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
139 struct nvif_device *device = dmac->base.device;
140 nvif_wr32(&device->object, 0x070000, 0x00000001);
141 nvif_msec(device, 2000,
142 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
143 break;
144 );
145 }
146
147 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
148 dmac->put = dmac->cur;
149 }
150
151 push->bgn = push->cur;
152}
153
154static int
155nv50_dmac_free(struct nv50_dmac *dmac)
156{
157 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
158 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
159 return get - dmac->cur - 5;
160 return dmac->max - dmac->cur;
161}
162
163static int
164nv50_dmac_wind(struct nv50_dmac *dmac)
165{
166 /* Wait for GET to depart from the beginning of the push buffer to
167 * prevent writing PUT == GET, which would be ignored by HW.
168 */
169 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
170 if (get == 0) {
171 /* Corner-case, HW idle, but non-committed work pending. */
172 if (dmac->put == 0)
173 nv50_dmac_kick(dmac->push);
174
175 if (nvif_msec(dmac->base.device, 2000,
176 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
177 break;
178 ) < 0)
179 return -ETIMEDOUT;
180 }
181
182 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
183 dmac->cur = 0;
184 return 0;
2853ccf0
BS		 185}
186
187static int
188nv50_dmac_wait(struct nvif_push *push, u32 size)
189{
190 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
0a960996
BS		 191 int free;
192
193 if (WARN_ON(size > dmac->max))
194 return -EINVAL;
195
9cf06d6e 196 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
0a960996
BS		 197 if (dmac->cur + size >= dmac->max) {
198 int ret = nv50_dmac_wind(dmac);
199 if (ret)
200 return ret;
201
202 push->cur = dmac->_push.mem.object.map.ptr;
203 push->cur = push->cur + dmac->cur;
204 nv50_dmac_kick(push);
205 }
206
207 if (nvif_msec(dmac->base.device, 2000,
208 if ((free = nv50_dmac_free(dmac)) >= size)
209 break;
210 ) < 0) {
211 WARN_ON(1);
2853ccf0 212 return -ETIMEDOUT;
0a960996 213 }
2853ccf0 214
0a960996
BS		 215 push->bgn = dmac->_push.mem.object.map.ptr;
216 push->bgn = push->bgn + dmac->cur;
217 push->cur = push->bgn;
218 push->end = push->cur + free;
2853ccf0 219 return 0;
839ca903
BS		 220}
221
a708d8a7
BS		 222MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)");
223static int nv50_dmac_vram_pushbuf = -1;
224module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400);
225
1590700d
BS		 226int
227nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
caeb6ab8 228 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
1590700d 229 struct nv50_dmac *dmac)
9bfdee9a 230{
1590700d 231 struct nouveau_cli *cli = (void *)device->object.client;
889fcbe9 232 struct nvif_disp_chan_v0 *args = data;
d00ddd9d 233 u8 type = NVIF_MEM_COHERENT;
1590700d 234 int ret;
9bfdee9a 235
1590700d 236 mutex_init(&dmac->lock);
9bfdee9a 237
d00ddd9d
BS		 238 /* Pascal added support for 47-bit physical addresses, but some
239 * parts of EVO still only accept 40-bit PAs.
240 *
241 * To avoid issues on systems with large amounts of RAM, and on
242 * systems where an IOMMU maps pages at a high address, we need
243 * to allocate push buffers in VRAM instead.
244 *
245 * This appears to match NVIDIA's behaviour on Pascal.
246 */
a708d8a7
BS		 247 if ((nv50_dmac_vram_pushbuf > 0) ||
248 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
d00ddd9d
BS		 249 type |= NVIF_MEM_VRAM;
250
e79c9a0b 251 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
2853ccf0 252 &dmac->_push.mem);
1590700d
BS		 253 if (ret)
254 return ret;
438d99e3 255
2853ccf0
BS		 256 dmac->ptr = dmac->_push.mem.object.map.ptr;
257 dmac->_push.wait = nv50_dmac_wait;
258 dmac->_push.kick = nv50_dmac_kick;
259 dmac->push = &dmac->_push;
0a960996
BS		 260 dmac->push->bgn = dmac->_push.mem.object.map.ptr;
261 dmac->push->cur = dmac->push->bgn;
262 dmac->push->end = dmac->push->bgn;
263 dmac->max = 0x1000/4 - 1;
438d99e3 264
ca386aa7
BS		 265 /* EVO channels are affected by a HW bug where the last 12 DWORDs
266 * of the push buffer aren't able to be used safely.
267 */
268 if (disp->oclass < GV100_DISP)
269 dmac->max -= 12;
270
2853ccf0 271 args->pushbuf = nvif_handle(&dmac->_push.mem.object);
438d99e3 272
1590700d
BS		 273 ret = nv50_chan_create(device, disp, oclass, head, data, size,
274 &dmac->base);
275 if (ret)
973f10c2 276 return ret;
973f10c2 277
caeb6ab8 278 if (syncbuf < 0)
facaed62
BS		 279 return 0;
280
9ac596a4 281 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
0bc8ffe0 282 NV_DMA_IN_MEMORY,
1590700d
BS		 283 &(struct nv_dma_v0) {
284 .target = NV_DMA_V0_TARGET_VRAM,
285 .access = NV_DMA_V0_ACCESS_RDWR,
286 .start = syncbuf + 0x0000,
287 .limit = syncbuf + 0x0fff,
288 }, sizeof(struct nv_dma_v0),
289 &dmac->sync);
290 if (ret)
291 return ret;
b5a794b0 292
9ac596a4 293 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
0bc8ffe0 294 NV_DMA_IN_MEMORY,
1590700d
BS		 295 &(struct nv_dma_v0) {
296 .target = NV_DMA_V0_TARGET_VRAM,
297 .access = NV_DMA_V0_ACCESS_RDWR,
298 .start = 0,
299 .limit = device->info.ram_user - 1,
300 }, sizeof(struct nv_dma_v0),
301 &dmac->vram);
438d99e3 302 if (ret)
1590700d
BS		 303 return ret;
304
438d99e3
BS		 305 return ret;
306}
307
a91d3221 308/******************************************************************************
d92c8adf 309 * Output path helpers
a91d3221 310 *****************************************************************************/
36dc1777
LP		 311static void
312nv50_outp_dump_caps(struct nouveau_drm *drm,
313 struct nouveau_encoder *outp)
314{
315 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n",
316 outp->base.base.name, outp->caps.dp_interlace);
317}
318
d92c8adf
BS		 319static int
320nv50_outp_atomic_check_view(struct drm_encoder *encoder,
321 struct drm_crtc_state *crtc_state,
322 struct drm_connector_state *conn_state,
323 struct drm_display_mode *native_mode)
324{
325 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
326 struct drm_display_mode *mode = &crtc_state->mode;
327 struct drm_connector *connector = conn_state->connector;
328 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
329 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
330
331 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
332 asyc->scaler.full = false;
333 if (!native_mode)
334 return 0;
335
336 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
337 switch (connector->connector_type) {
338 case DRM_MODE_CONNECTOR_LVDS:
339 case DRM_MODE_CONNECTOR_eDP:
f8d6211a
IM		 340 /* Don't force scaler for EDID modes with
341 * same size as the native one (e.g. different
342 * refresh rate)
343 */
3d1890ef
BS		 344 if (mode->hdisplay == native_mode->hdisplay &&
345 mode->vdisplay == native_mode->vdisplay &&
346 mode->type & DRM_MODE_TYPE_DRIVER)
d92c8adf
BS		 347 break;
348 mode = native_mode;
349 asyc->scaler.full = true;
350 break;
351 default:
352 break;
353 }
354 } else {
355 mode = native_mode;
356 }
357
358 if (!drm_mode_equal(adjusted_mode, mode)) {
359 drm_mode_copy(adjusted_mode, mode);
360 crtc_state->mode_changed = true;
361 }
362
363 return 0;
364}
365
7f67aa09
KH		 366static void
367nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
368{
369 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
370 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
371 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
372 unsigned int max_rate, mode_rate;
373
374 switch (nv_encoder->dcb->type) {
375 case DCB_OUTPUT_DP:
376 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
377
378 /* we don't support more than 10 anyway */
379 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
380
381 /* reduce the bpc until it works out */
382 while (asyh->or.bpc > 6) {
383 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
384 if (mode_rate <= max_rate)
385 break;
386
387 asyh->or.bpc -= 2;
388 }
389 break;
390 default:
391 break;
392 }
393}
394
839ca903
BS		 395static int
396nv50_outp_atomic_check(struct drm_encoder *encoder,
397 struct drm_crtc_state *crtc_state,
398 struct drm_connector_state *conn_state)
a91d3221 399{
ac2d9275
LP		 400 struct drm_connector *connector = conn_state->connector;
401 struct nouveau_connector *nv_connector = nouveau_connector(connector);
402 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
403 int ret;
404
405 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
406 nv_connector->native_mode);
407 if (ret)
408 return ret;
409
410 if (crtc_state->mode_changed || crtc_state->connectors_changed)
411 asyh->or.bpc = connector->display_info.bpc;
412
7f67aa09
KH		 413 /* We might have to reduce the bpc */
414 nv50_outp_atomic_fix_depth(encoder, crtc_state);
415
ac2d9275 416 return 0;
a91d3221
BS		 417}
418
09838c4e 419struct nouveau_connector *
cd5609f7 420nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
09838c4e
LP		 421{
422 struct drm_connector *connector;
423 struct drm_connector_state *connector_state;
424 struct drm_encoder *encoder = to_drm_encoder(outp);
425 int i;
426
427 for_each_new_connector_in_state(state, connector, connector_state, i) {
428 if (connector_state->best_encoder == encoder)
429 return nouveau_connector(connector);
430 }
431
432 return NULL;
433}
434
435struct nouveau_connector *
cd5609f7 436nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
09838c4e
LP		 437{
438 struct drm_connector *connector;
439 struct drm_connector_state *connector_state;
440 struct drm_encoder *encoder = to_drm_encoder(outp);
441 int i;
442
443 for_each_old_connector_in_state(state, connector, connector_state, i) {
444 if (connector_state->best_encoder == encoder)
445 return nouveau_connector(connector);
446 }
447
448 return NULL;
449}
450
1b38cf6b
LP		 451static struct nouveau_crtc *
452nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp)
453{
454 struct drm_crtc *crtc;
455 struct drm_crtc_state *crtc_state;
456 const u32 mask = drm_encoder_mask(&outp->base.base);
457 int i;
458
459 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
460 if (crtc_state->encoder_mask & mask)
461 return nouveau_crtc(crtc);
462 }
463
464 return NULL;
465}
466
26f6d88b
BS		 467/******************************************************************************
468 * DAC
469 *****************************************************************************/
0a368771 470static void
fa9f9489 471nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
0a368771
BS		 472{
473 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
474 struct nv50_core *core = nv50_disp(encoder->dev)->core;
344c2e5a 475 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
f575f2bd 476
ea6143a8 477 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
f20c665c 478 nv_encoder->crtc = NULL;
ea6143a8 479 nvif_outp_release(&nv_encoder->outp);
8eaa9669
BS		 480}
481
482static void
fa9f9489 483nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
8eaa9669
BS		 484{
485 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1b38cf6b
LP		 486 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
487 struct nv50_head_atom *asyh =
488 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
0a368771 489 struct nv50_core *core = nv50_disp(encoder->dev)->core;
344c2e5a
BS		 490 u32 ctrl = 0;
491
492 switch (nv_crtc->index) {
493 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
494 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
495 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
496 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
497 default:
498 WARN_ON(1);
499 break;
500 }
501
502 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
8eaa9669 503
ea6143a8 504 nvif_outp_acquire_rgb_crt(&nv_encoder->outp);
6c22ea37 505
ea6143a8 506 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
2ca7fb5c 507 asyh->or.depth = 0;
8eaa9669 508
1b38cf6b 509 nv_encoder->crtc = &nv_crtc->base;
8eaa9669
BS		 510}
511
b6d8e7ec 512static enum drm_connector_status
e225f446 513nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
b6d8e7ec 514{
c4abd317 515 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
dfc4005f 516 u32 loadval;
c4abd317
BS		 517 int ret;
518
dfc4005f
BS		 519 loadval = nouveau_drm(encoder->dev)->vbios.dactestval;
520 if (loadval == 0)
521 loadval = 340;
b681993f 522
dfc4005f
BS		 523 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval);
524 if (ret <= 0)
35b21d39 525 return connector_status_disconnected;
b681993f 526
35b21d39 527 return connector_status_connected;
b6d8e7ec
BS		 528}
529
f20c665c
BS		 530static const struct drm_encoder_helper_funcs
531nv50_dac_help = {
839ca903 532 .atomic_check = nv50_outp_atomic_check,
fa9f9489
LP		 533 .atomic_enable = nv50_dac_atomic_enable,
534 .atomic_disable = nv50_dac_atomic_disable,
e225f446 535 .detect = nv50_dac_detect
8eaa9669
BS		 536};
537
f20c665c
BS		 538static void
539nv50_dac_destroy(struct drm_encoder *encoder)
540{
1b255f1c
BS		 541 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
542
543 nvif_outp_dtor(&nv_encoder->outp);
544
f20c665c
BS		 545 drm_encoder_cleanup(encoder);
546 kfree(encoder);
547}
548
549static const struct drm_encoder_funcs
550nv50_dac_func = {
e225f446 551 .destroy = nv50_dac_destroy,
8eaa9669
BS		 552};
553
554static int
e225f446 555nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
8eaa9669 556{
5ed50209 557 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1b255f1c 558 struct nv50_disp *disp = nv50_disp(connector->dev);
1167c6bc 559 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2aa5eac5 560 struct nvkm_i2c_bus *bus;
8eaa9669
BS		 561 struct nouveau_encoder *nv_encoder;
562 struct drm_encoder *encoder;
5ed50209 563 int type = DRM_MODE_ENCODER_DAC;
8eaa9669
BS		 564
565 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
566 if (!nv_encoder)
567 return -ENOMEM;
568 nv_encoder->dcb = dcbe;
2aa5eac5
BS		 569
570 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
571 if (bus)
572 nv_encoder->i2c = &bus->i2c;
8eaa9669
BS		 573
574 encoder = to_drm_encoder(nv_encoder);
575 encoder->possible_crtcs = dcbe->heads;
576 encoder->possible_clones = 0;
5a223dac
BS		 577 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
578 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
f20c665c 579 drm_encoder_helper_add(encoder, &nv50_dac_help);
8eaa9669 580
cde4c44d 581 drm_connector_attach_encoder(connector, encoder);
1b255f1c 582 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
8eaa9669 583}
26f6d88b 584
742db30c
TI		 585/*
586 * audio component binding for ELD notification
587 */
588static void
61a41097
TI		 589nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
590 int dev_id)
742db30c
TI		 591{
592 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
593 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
61a41097 594 port, dev_id);
742db30c
TI		 595}
596
597static int
61a41097 598nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
742db30c
TI		 599 bool *enabled, unsigned char *buf, int max_bytes)
600{
601 struct drm_device *drm_dev = dev_get_drvdata(kdev);
602 struct nouveau_drm *drm = nouveau_drm(drm_dev);
603 struct drm_encoder *encoder;
604 struct nouveau_encoder *nv_encoder;
742db30c
TI		 605 struct nouveau_crtc *nv_crtc;
606 int ret = 0;
607
608 *enabled = false;
09838c4e 609
9125e242
LP		 610 mutex_lock(&drm->audio.lock);
611
742db30c 612 drm_for_each_encoder(encoder, drm->dev) {
09838c4e
LP		 613 struct nouveau_connector *nv_connector = NULL;
614
9125e242
LP		 615 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
616 continue; /* TODO */
617
742db30c 618 nv_encoder = nouveau_encoder(encoder);
9125e242
LP		 619 nv_connector = nouveau_connector(nv_encoder->audio.connector);
620 nv_crtc = nouveau_crtc(nv_encoder->crtc);
09838c4e 621
ea6143a8 622 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id)
09838c4e
LP		 623 continue;
624
9125e242 625 *enabled = nv_encoder->audio.enabled;
742db30c
TI		 626 if (*enabled) {
627 ret = drm_eld_size(nv_connector->base.eld);
628 memcpy(buf, nv_connector->base.eld,
629 min(max_bytes, ret));
630 }
631 break;
632 }
09838c4e 633
9125e242
LP		 634 mutex_unlock(&drm->audio.lock);
635
742db30c
TI		 636 return ret;
637}
638
639static const struct drm_audio_component_ops nv50_audio_component_ops = {
640 .get_eld = nv50_audio_component_get_eld,
641};
642
643static int
644nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
645 void *data)
646{
647 struct drm_device *drm_dev = dev_get_drvdata(kdev);
648 struct nouveau_drm *drm = nouveau_drm(drm_dev);
649 struct drm_audio_component *acomp = data;
650
651 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
652 return -ENOMEM;
653
7a154d5b 654 drm_modeset_lock_all(drm_dev);
742db30c
TI		 655 acomp->ops = &nv50_audio_component_ops;
656 acomp->dev = kdev;
657 drm->audio.component = acomp;
7a154d5b
SP		 658 drm_modeset_unlock_all(drm_dev);
659 return 0;
742db30c
TI		 660}
661
662static void
663nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
664 void *data)
665{
666 struct drm_device *drm_dev = dev_get_drvdata(kdev);
667 struct nouveau_drm *drm = nouveau_drm(drm_dev);
668 struct drm_audio_component *acomp = data;
669
7a154d5b 670 drm_modeset_lock_all(drm_dev);
742db30c
TI		 671 drm->audio.component = NULL;
672 acomp->ops = NULL;
673 acomp->dev = NULL;
7a154d5b 674 drm_modeset_unlock_all(drm_dev);
742db30c
TI		 675}
676
677static const struct component_ops nv50_audio_component_bind_ops = {
678 .bind = nv50_audio_component_bind,
679 .unbind = nv50_audio_component_unbind,
680};
681
682static void
683nv50_audio_component_init(struct nouveau_drm *drm)
684{
9125e242
LP		 685 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
686 return;
687
688 drm->audio.component_registered = true;
689 mutex_init(&drm->audio.lock);
742db30c
TI		 690}
691
692static void
693nv50_audio_component_fini(struct nouveau_drm *drm)
694{
9125e242
LP		 695 if (!drm->audio.component_registered)
696 return;
697
698 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
699 drm->audio.component_registered = false;
700 mutex_destroy(&drm->audio.lock);
742db30c
TI		 701}
702
78951d22
BS		 703/******************************************************************************
704 * Audio
705 *****************************************************************************/
a9f5d772
BS		 706static bool
707nv50_audio_supported(struct drm_encoder *encoder)
708{
709 struct nv50_disp *disp = nv50_disp(encoder->dev);
710
711 if (disp->disp->object.oclass <= GT200_DISP ||
712 disp->disp->object.oclass == GT206_DISP)
713 return false;
714
715 return true;
716}
717
78951d22 718static void
f20c665c
BS		 719nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
720{
742db30c 721 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
f20c665c 722 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
ea6143a8 723 struct nvif_outp *outp = &nv_encoder->outp;
a9f5d772
BS		 724
725 if (!nv50_audio_supported(encoder))
726 return;
f20c665c 727
9125e242
LP		 728 mutex_lock(&drm->audio.lock);
729 if (nv_encoder->audio.enabled) {
730 nv_encoder->audio.enabled = false;
731 nv_encoder->audio.connector = NULL;
a9f5d772 732 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0);
9125e242
LP		 733 }
734 mutex_unlock(&drm->audio.lock);
742db30c 735
ea6143a8 736 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
f20c665c
BS		 737}
738
739static void
1b38cf6b
LP		 740nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
741 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
09838c4e 742 struct drm_display_mode *mode)
78951d22 743{
742db30c 744 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
78951d22 745 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
ea6143a8 746 struct nvif_outp *outp = &nv_encoder->outp;
a9f5d772
BS		 747
748 if (!nv50_audio_supported(encoder) || !drm_detect_monitor_audio(nv_connector->edid))
78951d22
BS		 749 return;
750
9125e242
LP		 751 mutex_lock(&drm->audio.lock);
752
a9f5d772
BS		 753 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld,
754 drm_eld_size(nv_connector->base.eld));
9125e242
LP		 755 nv_encoder->audio.enabled = true;
756 nv_encoder->audio.connector = &nv_connector->base;
757
758 mutex_unlock(&drm->audio.lock);
742db30c 759
ea6143a8 760 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
78951d22
BS		 761}
762
f20c665c
BS		 763/******************************************************************************
764 * HDMI
765 *****************************************************************************/
78951d22 766static void
1b38cf6b
LP		 767nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
768 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
f530bc60 769 struct drm_display_mode *mode, bool hda)
78951d22 770{
7a406f8a 771 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
64d9cc04 772 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
f530bc60 773 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
c02f20d3 774 union hdmi_infoframe infoframe = { 0 };
f530bc60 775 const u8 rekey = 56; /* binary driver, and tegra, constant */
c02f20d3 776 u8 scdc = 0;
64d9cc04 777 u32 max_ac_packet;
f530bc60
BS		 778 struct {
779 struct nvif_outp_infoframe_v0 infoframe;
780 u8 data[17];
c02f20d3 781 } args = { 0 };
f530bc60 782 int ret, size;
34fd3e5d 783
64d9cc04 784 max_ac_packet = mode->htotal - mode->hdisplay;
f530bc60 785 max_ac_packet -= rekey;
64d9cc04 786 max_ac_packet -= 18; /* constant from tegra */
f530bc60 787 max_ac_packet /= 32;
091e40cd 788
7a406f8a 789 if (hdmi->scdc.scrambling.supported) {
f530bc60 790 const bool high_tmds_clock_ratio = mode->clock > 340000;
7a406f8a 791
c02f20d3 792 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc);
f530bc60
BS		 793 if (ret < 0) {
794 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
795 return;
796 }
7a406f8a 797
c02f20d3 798 scdc &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
f530bc60 799 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
c02f20d3 800 scdc |= SCDC_SCRAMBLING_ENABLE;
f530bc60 801 if (high_tmds_clock_ratio)
c02f20d3 802 scdc |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
7a406f8a 803
c02f20d3 804 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc);
f530bc60
BS		 805 if (ret < 0)
806 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
c02f20d3 807 scdc, ret);
f530bc60 808 }
7a406f8a 809
f530bc60
BS		 810 ret = nvif_outp_acquire_tmds(&nv_encoder->outp, nv_crtc->index, true,
811 max_ac_packet, rekey, scdc, hda);
812 if (ret)
7a406f8a 813 return;
f530bc60
BS		 814
815 /* AVI InfoFrame. */
816 args.infoframe.version = 0;
817 args.infoframe.head = nv_crtc->index;
818
819 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) {
820 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode,
821 HDMI_QUANTIZATION_RANGE_FULL);
822
c02f20d3 823 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
f530bc60
BS		 824 } else {
825 size = 0;
7a406f8a 826 }
f530bc60
BS		 827
828 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size);
829
830 /* Vendor InfoFrame. */
c02f20d3 831 memset(&args.data, 0, sizeof(args.data));
f530bc60
BS		 832 if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi,
833 &nv_connector->base, mode))
c02f20d3 834 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
f530bc60
BS		 835 else
836 size = 0;
837
838 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size);
839
840 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
78951d22
BS		 841}
842
52aa30f2
BS		 843/******************************************************************************
844 * MST
845 *****************************************************************************/
f479c0ba
BS		 846#define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
847#define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
848#define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
849
f479c0ba
BS		 850struct nv50_mstc {
851 struct nv50_mstm *mstm;
852 struct drm_dp_mst_port *port;
853 struct drm_connector connector;
854
855 struct drm_display_mode *native;
856 struct edid *edid;
52aa30f2
BS		 857};
858
f479c0ba
BS		 859struct nv50_msto {
860 struct drm_encoder encoder;
861
1b38cf6b 862 /* head is statically assigned on msto creation */
f479c0ba
BS		 863 struct nv50_head *head;
864 struct nv50_mstc *mstc;
865 bool disabled;
4d07b0bc 866 bool enabled;
f479c0ba
BS		 867};
868
12885ecb
LP		 869struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
870{
871 struct nv50_msto *msto;
872
873 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
874 return nouveau_encoder(encoder);
875
876 msto = nv50_msto(encoder);
877 if (!msto->mstc)
878 return NULL;
879 return msto->mstc->mstm->outp;
880}
881
f479c0ba 882static void
4d07b0bc
LP		 883nv50_msto_cleanup(struct drm_atomic_state *state,
884 struct drm_dp_mst_topology_state *mst_state,
885 struct drm_dp_mst_topology_mgr *mgr,
886 struct nv50_msto *msto)
f479c0ba
BS		 887{
888 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
4d07b0bc
LP		 889 struct drm_dp_mst_atomic_payload *payload =
890 drm_atomic_get_mst_payload_state(mst_state, msto->mstc->port);
5e292e76 891
f479c0ba 892 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
5e292e76 893
4d07b0bc
LP		 894 if (msto->disabled) {
895 msto->mstc = NULL;
896 msto->disabled = false;
897 } else if (msto->enabled) {
898 drm_dp_add_payload_part2(mgr, state, payload);
899 msto->enabled = false;
900 }
f479c0ba
BS		 901}
902
903static void
4d07b0bc
LP		 904nv50_msto_prepare(struct drm_atomic_state *state,
905 struct drm_dp_mst_topology_state *mst_state,
906 struct drm_dp_mst_topology_mgr *mgr,
907 struct nv50_msto *msto)
f479c0ba
BS		 908{
909 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
910 struct nv50_mstc *mstc = msto->mstc;
911 struct nv50_mstm *mstm = mstc->mstm;
4d07b0bc 912 struct drm_dp_mst_atomic_payload *payload;
f479c0ba
BS		 913
914 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
4d07b0bc
LP		 915
916 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
917
918 // TODO: Figure out if we want to do a better job of handling VCPI allocation failures here?
919 if (msto->disabled) {
e761cc20 920 drm_dp_remove_payload(mgr, mst_state, payload, payload);
8c7d980d
BS		 921
922 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
4d07b0bc
LP		 923 } else {
924 if (msto->enabled)
925 drm_dp_add_payload_part1(mgr, mst_state, payload);
926
8c7d980d
BS		 927 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index,
928 payload->vc_start_slot, payload->time_slots,
929 payload->pbn, payload->time_slots * mst_state->pbn_div);
f479c0ba 930 }
f479c0ba
BS		 931}
932
933static int
934nv50_msto_atomic_check(struct drm_encoder *encoder,
935 struct drm_crtc_state *crtc_state,
936 struct drm_connector_state *conn_state)
937{
232c9eec
LP		 938 struct drm_atomic_state *state = crtc_state->state;
939 struct drm_connector *connector = conn_state->connector;
4d07b0bc 940 struct drm_dp_mst_topology_state *mst_state;
232c9eec 941 struct nv50_mstc *mstc = nv50_mstc(connector);
f479c0ba 942 struct nv50_mstm *mstm = mstc->mstm;
88ec89ad 943 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
f479c0ba 944 int slots;
310d3577 945 int ret;
f479c0ba 946
310d3577
LP		 947 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
948 mstc->native);
949 if (ret)
950 return ret;
f479c0ba 951
21167510 952 if (!drm_atomic_crtc_needs_modeset(crtc_state))
310d3577 953 return 0;
88ec89ad 954
310d3577
LP		 955 /*
956 * When restoring duplicated states, we need to make sure that the bw
957 * remains the same and avoid recalculating it, as the connector's bpc
958 * may have changed after the state was duplicated
959 */
960 if (!state->duplicated) {
310d3577
LP		 961 const int clock = crtc_state->adjusted_mode.clock;
962
bbdf6a58
LP		 963 asyh->or.bpc = connector->display_info.bpc;
964 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
965 false);
232c9eec 966 }
f479c0ba 967
4d07b0bc
LP		 968 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
969 if (IS_ERR(mst_state))
970 return PTR_ERR(mst_state);
971
972 if (!mst_state->pbn_div) {
973 struct nouveau_encoder *outp = mstc->mstm->outp;
974
975 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
976 outp->dp.link_bw, outp->dp.link_nr);
977 }
978
979 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
310d3577
LP		 980 if (slots < 0)
981 return slots;
982
983 asyh->dp.tu = slots;
984
985 return 0;
f479c0ba
BS		 986}
987
ac2d9275
LP		 988static u8
989nv50_dp_bpc_to_depth(unsigned int bpc)
990{
991 switch (bpc) {
344c2e5a
BS		 992 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
993 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
f6e7393e 994 case 10:
344c2e5a 995 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
ac2d9275
LP		 996 }
997}
998
f479c0ba 999static void
fa9f9489 1000nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
f479c0ba 1001{
f479c0ba 1002 struct nv50_msto *msto = nv50_msto(encoder);
1b38cf6b
LP		 1003 struct nv50_head *head = msto->head;
1004 struct nv50_head_atom *asyh =
1005 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
f479c0ba
BS		 1006 struct nv50_mstc *mstc = NULL;
1007 struct nv50_mstm *mstm = NULL;
1008 struct drm_connector *connector;
875dd626 1009 struct drm_connector_list_iter conn_iter;
ac2d9275 1010 u8 proto;
f479c0ba 1011
875dd626
GP		 1012 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1013 drm_for_each_connector_iter(connector, &conn_iter) {
f479c0ba
BS		 1014 if (connector->state->best_encoder == &msto->encoder) {
1015 mstc = nv50_mstc(connector);
1016 mstm = mstc->mstm;
1017 break;
1018 }
1019 }
875dd626 1020 drm_connector_list_iter_end(&conn_iter);
f479c0ba
BS		 1021
1022 if (WARN_ON(!mstc))
1023 return;
1024
ea6143a8
BS		 1025 if (!mstm->links++) {
1026 /*XXX: MST audio. */
81344372 1027 nvif_outp_acquire_dp(&mstm->outp->outp, mstm->outp->dp.dpcd, 0, 0, false, true);
ea6143a8 1028 }
6c22ea37 1029
ea6143a8 1030 if (mstm->outp->outp.or.link & 1)
344c2e5a 1031 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
f479c0ba 1032 else
344c2e5a 1033 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
f479c0ba 1034
f60f8705
LP		 1035 mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1036 nv50_dp_bpc_to_depth(asyh->or.bpc));
f479c0ba 1037
f479c0ba 1038 msto->mstc = mstc;
4d07b0bc 1039 msto->enabled = true;
f479c0ba
BS		 1040 mstm->modified = true;
1041}
1042
1043static void
fa9f9489 1044nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
f479c0ba
BS		 1045{
1046 struct nv50_msto *msto = nv50_msto(encoder);
1047 struct nv50_mstc *mstc = msto->mstc;
1048 struct nv50_mstm *mstm = mstc->mstm;
1049
f479c0ba
BS		 1050 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1051 mstm->modified = true;
6c22ea37
BS		 1052 if (!--mstm->links)
1053 mstm->disabled = true;
f479c0ba
BS		 1054 msto->disabled = true;
1055}
1056
1057static const struct drm_encoder_helper_funcs
1058nv50_msto_help = {
fa9f9489
LP		 1059 .atomic_disable = nv50_msto_atomic_disable,
1060 .atomic_enable = nv50_msto_atomic_enable,
f479c0ba
BS		 1061 .atomic_check = nv50_msto_atomic_check,
1062};
1063
1064static void
1065nv50_msto_destroy(struct drm_encoder *encoder)
1066{
1067 struct nv50_msto *msto = nv50_msto(encoder);
1068 drm_encoder_cleanup(&msto->encoder);
1069 kfree(msto);
1070}
1071
1072static const struct drm_encoder_funcs
1073nv50_msto = {
1074 .destroy = nv50_msto_destroy,
1075};
1076
5ff0cb1c
LP		 1077static struct nv50_msto *
1078nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
f479c0ba
BS		 1079{
1080 struct nv50_msto *msto;
1081 int ret;
1082
5ff0cb1c
LP		 1083 msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1084 if (!msto)
1085 return ERR_PTR(-ENOMEM);
f479c0ba
BS		 1086
1087 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
5ff0cb1c 1088 DRM_MODE_ENCODER_DPMST, "mst-%d", id);
f479c0ba 1089 if (ret) {
5ff0cb1c
LP		 1090 kfree(msto);
1091 return ERR_PTR(ret);
f479c0ba
BS		 1092 }
1093
1094 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
5ff0cb1c
LP		 1095 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1096 msto->head = head;
1097 return msto;
f479c0ba
BS		 1098}
1099
1100static struct drm_encoder *
1101nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
eca22edb 1102 struct drm_atomic_state *state)
f479c0ba 1103{
eca22edb
MR		 1104 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1105 connector);
f479c0ba 1106 struct nv50_mstc *mstc = nv50_mstc(connector);
5ff0cb1c 1107 struct drm_crtc *crtc = connector_state->crtc;
7b0f61e9 1108
5ff0cb1c
LP		 1109 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1110 return NULL;
1111
1112 return &nv50_head(crtc)->msto->encoder;
f479c0ba
BS		 1113}
1114
f479c0ba
BS		 1115static enum drm_mode_status
1116nv50_mstc_mode_valid(struct drm_connector *connector,
1117 struct drm_display_mode *mode)
1118{
d6a9efec
LP		 1119 struct nv50_mstc *mstc = nv50_mstc(connector);
1120 struct nouveau_encoder *outp = mstc->mstm->outp;
1121
1122 /* TODO: calculate the PBN from the dotclock and validate against the
1123 * MSTB's max possible PBN
1124 */
1125
1126 return nv50_dp_mode_valid(connector, outp, mode, NULL);
f479c0ba
BS		 1127}
1128
1129static int
1130nv50_mstc_get_modes(struct drm_connector *connector)
1131{
1132 struct nv50_mstc *mstc = nv50_mstc(connector);
1133 int ret = 0;
1134
1135 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
c555f023 1136 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
d471ed04 1137 if (mstc->edid)
f479c0ba 1138 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
f479c0ba 1139
bbdf6a58
LP		 1140 /*
1141 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1142 * to 8 to save bandwidth on the topology. In the future, we'll want
1143 * to properly fix this by dynamically selecting the highest possible
1144 * bpc that would fit in the topology
1145 */
1146 if (connector->display_info.bpc)
1147 connector->display_info.bpc =
1148 clamp(connector->display_info.bpc, 6U, 8U);
1149 else
1150 connector->display_info.bpc = 8;
f479c0ba
BS		 1151
1152 if (mstc->native)
1153 drm_mode_destroy(mstc->connector.dev, mstc->native);
1154 mstc->native = nouveau_conn_native_mode(&mstc->connector);
1155 return ret;
1156}
1157
232c9eec
LP		 1158static int
1159nv50_mstc_atomic_check(struct drm_connector *connector,
6f3b6278 1160 struct drm_atomic_state *state)
232c9eec 1161{
232c9eec
LP		 1162 struct nv50_mstc *mstc = nv50_mstc(connector);
1163 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
232c9eec 1164
df78f7f6 1165 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port);
232c9eec
LP		 1166}
1167
3f9b3f02
LP		 1168static int
1169nv50_mstc_detect(struct drm_connector *connector,
1170 struct drm_modeset_acquire_ctx *ctx, bool force)
f479c0ba
BS		 1171{
1172 struct nv50_mstc *mstc = nv50_mstc(connector);
e46368cf
LP		 1173 int ret;
1174
d79a3c52 1175 if (drm_connector_is_unregistered(connector))
f479c0ba 1176 return connector_status_disconnected;
e46368cf
LP		 1177
1178 ret = pm_runtime_get_sync(connector->dev->dev);
dc455f4c
DL		 1179 if (ret < 0 && ret != -EACCES) {
1180 pm_runtime_put_autosuspend(connector->dev->dev);
e46368cf 1181 return connector_status_disconnected;
dc455f4c 1182 }
e46368cf 1183
3f9b3f02
LP		 1184 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1185 mstc->port);
409d3813
LP		 1186 if (ret != connector_status_connected)
1187 goto out;
e46368cf 1188
409d3813 1189out:
e46368cf
LP		 1190 pm_runtime_mark_last_busy(connector->dev->dev);
1191 pm_runtime_put_autosuspend(connector->dev->dev);
3f9b3f02 1192 return ret;
f479c0ba
BS		 1193}
1194
3f9b3f02
LP		 1195static const struct drm_connector_helper_funcs
1196nv50_mstc_help = {
1197 .get_modes = nv50_mstc_get_modes,
1198 .mode_valid = nv50_mstc_mode_valid,
3f9b3f02
LP		 1199 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1200 .atomic_check = nv50_mstc_atomic_check,
1201 .detect_ctx = nv50_mstc_detect,
1202};
1203
f479c0ba
BS		 1204static void
1205nv50_mstc_destroy(struct drm_connector *connector)
1206{
1207 struct nv50_mstc *mstc = nv50_mstc(connector);
81640f01 1208
f479c0ba 1209 drm_connector_cleanup(&mstc->connector);
d79a3c52 1210 drm_dp_mst_put_port_malloc(mstc->port);
81640f01 1211
f479c0ba
BS		 1212 kfree(mstc);
1213}
1214
1215static const struct drm_connector_funcs
1216nv50_mstc = {
f479c0ba 1217 .reset = nouveau_conn_reset,
f479c0ba 1218 .fill_modes = drm_helper_probe_single_connector_modes,
f479c0ba
BS		 1219 .destroy = nv50_mstc_destroy,
1220 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1221 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1222 .atomic_set_property = nouveau_conn_atomic_set_property,
1223 .atomic_get_property = nouveau_conn_atomic_get_property,
1224};
1225
1226static int
1227nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1228 const char *path, struct nv50_mstc **pmstc)
1229{
1230 struct drm_device *dev = mstm->outp->base.base.dev;
5ff0cb1c 1231 struct drm_crtc *crtc;
f479c0ba 1232 struct nv50_mstc *mstc;
5ff0cb1c 1233 int ret;
f479c0ba
BS		 1234
1235 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1236 return -ENOMEM;
1237 mstc->mstm = mstm;
1238 mstc->port = port;
1239
1240 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1241 DRM_MODE_CONNECTOR_DisplayPort);
1242 if (ret) {
1243 kfree(*pmstc);
1244 *pmstc = NULL;
1245 return ret;
1246 }
1247
1248 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1249
1250 mstc->connector.funcs->reset(&mstc->connector);
1251 nouveau_conn_attach_properties(&mstc->connector);
1252
5ff0cb1c
LP		 1253 drm_for_each_crtc(crtc, dev) {
1254 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1255 continue;
1256
1257 drm_connector_attach_encoder(&mstc->connector,
1258 &nv50_head(crtc)->msto->encoder);
1259 }
f479c0ba
BS		 1260
1261 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1262 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
97e14fbe 1263 drm_connector_set_path_property(&mstc->connector, path);
81640f01 1264 drm_dp_mst_get_port_malloc(port);
f479c0ba
BS		 1265 return 0;
1266}
1267
1268static void
4d07b0bc
LP		 1269nv50_mstm_cleanup(struct drm_atomic_state *state,
1270 struct drm_dp_mst_topology_state *mst_state,
1271 struct nv50_mstm *mstm)
f479c0ba
BS		 1272{
1273 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1274 struct drm_encoder *encoder;
f479c0ba
BS		 1275
1276 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
606be062 1277 drm_dp_check_act_status(&mstm->mgr);
f479c0ba 1278
f479c0ba
BS		 1279 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1280 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1281 struct nv50_msto *msto = nv50_msto(encoder);
1282 struct nv50_mstc *mstc = msto->mstc;
1283 if (mstc && mstc->mstm == mstm)
4d07b0bc 1284 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto);
f479c0ba
BS		 1285 }
1286 }
1287
1288 mstm->modified = false;
1289}
1290
1291static void
4d07b0bc
LP		 1292nv50_mstm_prepare(struct drm_atomic_state *state,
1293 struct drm_dp_mst_topology_state *mst_state,
1294 struct nv50_mstm *mstm)
f479c0ba
BS		 1295{
1296 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1297 struct drm_encoder *encoder;
f479c0ba
BS		 1298
1299 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
f479c0ba 1300
4d07b0bc 1301 /* Disable payloads first */
f479c0ba
BS		 1302 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1303 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1304 struct nv50_msto *msto = nv50_msto(encoder);
1305 struct nv50_mstc *mstc = msto->mstc;
4d07b0bc
LP		 1306 if (mstc && mstc->mstm == mstm && msto->disabled)
1307 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1308 }
1309 }
1310
1311 /* Add payloads for new heads, while also updating the start slots of any unmodified (but
1312 * active) heads that may have had their VC slots shifted left after the previous step
1313 */
1314 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1315 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1316 struct nv50_msto *msto = nv50_msto(encoder);
1317 struct nv50_mstc *mstc = msto->mstc;
1318 if (mstc && mstc->mstm == mstm && !msto->disabled)
1319 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
f479c0ba
BS		 1320 }
1321 }
6c22ea37
BS		 1322
1323 if (mstm->disabled) {
1324 if (!mstm->links)
ea6143a8 1325 nvif_outp_release(&mstm->outp->outp);
6c22ea37
BS		 1326 mstm->disabled = false;
1327 }
f479c0ba
BS		 1328}
1329
f479c0ba
BS		 1330static struct drm_connector *
1331nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1332 struct drm_dp_mst_port *port, const char *path)
1333{
1334 struct nv50_mstm *mstm = nv50_mstm(mgr);
1335 struct nv50_mstc *mstc;
1336 int ret;
1337
1338 ret = nv50_mstc_new(mstm, port, path, &mstc);
01324093 1339 if (ret)
f479c0ba 1340 return NULL;
f479c0ba
BS		 1341
1342 return &mstc->connector;
1343}
1344
1345static const struct drm_dp_mst_topology_cbs
1346nv50_mstm = {
1347 .add_connector = nv50_mstm_add_connector,
f479c0ba
BS		 1348};
1349
a0922278
LP		 1350bool
1351nv50_mstm_service(struct nouveau_drm *drm,
1352 struct nouveau_connector *nv_connector,
1353 struct nv50_mstm *mstm)
f479c0ba 1354{
a0922278
LP		 1355 struct drm_dp_aux *aux = &nv_connector->aux;
1356 bool handled = true, ret = true;
1357 int rc;
f479c0ba
BS		 1358 u8 esi[8] = {};
1359
1360 while (handled) {
a0922278
LP		 1361 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1362 if (rc != 8) {
1363 ret = false;
1364 break;
f479c0ba
BS		 1365 }
1366
1367 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1368 if (!handled)
1369 break;
1370
a0922278
LP		 1371 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
1372 3);
1373 if (rc != 3) {
1374 ret = false;
1375 break;
1376 }
f479c0ba 1377 }
a0922278
LP		 1378
1379 if (!ret)
1380 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1381 nv_connector->base.name, rc);
1382
1383 return ret;
f479c0ba
BS		 1384}
1385
1386void
1387nv50_mstm_remove(struct nv50_mstm *mstm)
1388{
a0922278
LP		 1389 mstm->is_mst = false;
1390 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
f479c0ba
BS		 1391}
1392
52aa30f2 1393int
a0922278 1394nv50_mstm_detect(struct nouveau_encoder *outp)
52aa30f2 1395{
a0922278 1396 struct nv50_mstm *mstm = outp->dp.mstm;
b26b4590
LP		 1397 struct drm_dp_aux *aux;
1398 int ret;
52aa30f2 1399
a0922278 1400 if (!mstm || !mstm->can_mst)
52aa30f2
BS		 1401 return 0;
1402
b26b4590
LP		 1403 aux = mstm->mgr.aux;
1404
a0922278
LP		 1405 /* Clear any leftover MST state we didn't set ourselves by first
1406 * disabling MST if it was already enabled
1407 */
1408 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1409 if (ret < 0)
1410 return ret;
52aa30f2 1411
a0922278 1412 /* And start enabling */
a0922278 1413 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
81344372 1414 if (ret)
a0922278 1415 return ret;
b26b4590 1416
a0922278
LP		 1417 mstm->is_mst = true;
1418 return 1;
52aa30f2
BS		 1419}
1420
f479c0ba 1421static void
a0922278 1422nv50_mstm_fini(struct nouveau_encoder *outp)
f479c0ba 1423{
a0922278
LP		 1424 struct nv50_mstm *mstm = outp->dp.mstm;
1425
1426 if (!mstm)
1427 return;
1428
1429 /* Don't change the MST state of this connector until we've finished
1430 * resuming, since we can't safely grab hpd_irq_lock in our resume
1431 * path to protect mstm->is_mst without potentially deadlocking
1432 */
1433 mutex_lock(&outp->dp.hpd_irq_lock);
1434 mstm->suspended = true;
1435 mutex_unlock(&outp->dp.hpd_irq_lock);
1436
1437 if (mstm->is_mst)
f479c0ba
BS		 1438 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1439}
1440
1441static void
a0922278 1442nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
f479c0ba 1443{
a0922278
LP		 1444 struct nv50_mstm *mstm = outp->dp.mstm;
1445 int ret = 0;
b89fdf7a 1446
a0922278 1447 if (!mstm)
b89fdf7a
LP		 1448 return;
1449
a0922278
LP		 1450 if (mstm->is_mst) {
1451 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1452 if (ret == -1)
1453 nv50_mstm_remove(mstm);
b89fdf7a 1454 }
a0922278
LP		 1455
1456 mutex_lock(&outp->dp.hpd_irq_lock);
1457 mstm->suspended = false;
1458 mutex_unlock(&outp->dp.hpd_irq_lock);
1459
1460 if (ret == -1)
1461 drm_kms_helper_hotplug_event(mstm->mgr.dev);
f479c0ba
BS		 1462}
1463
52aa30f2
BS		 1464static void
1465nv50_mstm_del(struct nv50_mstm **pmstm)
1466{
1467 struct nv50_mstm *mstm = *pmstm;
1468 if (mstm) {
24199c54 1469 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
52aa30f2
BS		 1470 kfree(*pmstm);
1471 *pmstm = NULL;
1472 }
1473}
1474
1475static int
1476nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1477 int conn_base_id, struct nv50_mstm **pmstm)
1478{
1479 const int max_payloads = hweight8(outp->dcb->heads);
1480 struct drm_device *dev = outp->base.base.dev;
1481 struct nv50_mstm *mstm;
5ff0cb1c 1482 int ret;
52aa30f2
BS		 1483
1484 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1485 return -ENOMEM;
1486 mstm->outp = outp;
f479c0ba 1487 mstm->mgr.cbs = &nv50_mstm;
52aa30f2 1488
7b0a89a6 1489 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
4d07b0bc 1490 max_payloads, conn_base_id);
52aa30f2
BS		 1491 if (ret)
1492 return ret;
1493
1494 return 0;
1495}
1496
26f6d88b
BS		 1497/******************************************************************************
1498 * SOR
1499 *****************************************************************************/
4cbb0f8d 1500static void
d665c7e9 1501nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
2ca7fb5c 1502 struct nv50_head_atom *asyh, u8 proto, u8 depth)
4cbb0f8d 1503{
9ca6f1eb 1504 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
0a368771 1505 struct nv50_core *core = disp->core;
d665c7e9 1506
2ca7fb5c 1507 if (!asyh) {
d665c7e9 1508 nv_encoder->ctrl &= ~BIT(head);
344c2e5a 1509 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
d665c7e9
BS		 1510 nv_encoder->ctrl = 0;
1511 } else {
344c2e5a 1512 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
d665c7e9 1513 nv_encoder->ctrl |= BIT(head);
2ca7fb5c 1514 asyh->or.depth = depth;
d665c7e9
BS		 1515 }
1516
ea6143a8 1517 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
e84a35a8
BS		 1518}
1519
6eca310e
LP		 1520/* TODO: Should we extend this to PWM-only backlights?
1521 * As well, should we add a DRM helper for waiting for the backlight to acknowledge
1522 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
1523 * fixed time delay from the vbios…
1524 */
e84a35a8 1525static void
fa9f9489 1526nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
e84a35a8
BS		 1527{
1528 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1529 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
cd5609f7 1530 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
98c9644f
RD		 1531#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1532 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
6eca310e 1533 struct nouveau_backlight *backlight = nv_connector->backlight;
98c9644f 1534#endif
f575f2bd 1535 struct drm_dp_aux *aux = &nv_connector->aux;
6eca310e 1536 int ret;
f575f2bd 1537 u8 pwr;
839ca903 1538
98c9644f 1539#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
6eca310e
LP		 1540 if (backlight && backlight->uses_dpcd) {
1541 ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
1542 if (ret < 0)
1543 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
1544 nv_connector->base.base.id, nv_connector->base.name, ret);
1545 }
98c9644f 1546#endif
6eca310e 1547
f575f2bd 1548 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
98c9644f 1549 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
4944245c 1550
f575f2bd
LP		 1551 if (ret == 0) {
1552 pwr &= ~DP_SET_POWER_MASK;
1553 pwr |= DP_SET_POWER_D3;
1554 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
839ca903 1555 }
e84a35a8 1556 }
f575f2bd
LP		 1557
1558 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1559 nv50_audio_disable(encoder, nv_crtc);
ea6143a8 1560 nvif_outp_release(&nv_encoder->outp);
9125e242 1561 nv_encoder->crtc = NULL;
4cbb0f8d
BS		 1562}
1563
83fc083c 1564static void
fa9f9489 1565nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
83fc083c 1566{
a3761fa2 1567 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1b38cf6b
LP		 1568 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1569 struct nv50_head_atom *asyh =
1570 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
2ca7fb5c 1571 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
e225f446 1572 struct nv50_disp *disp = nv50_disp(encoder->dev);
f530bc60 1573 struct nvif_outp *outp = &nv_encoder->outp;
78951d22 1574 struct drm_device *dev = encoder->dev;
77145f1c 1575 struct nouveau_drm *drm = nouveau_drm(dev);
3b6d83d1 1576 struct nouveau_connector *nv_connector;
6eca310e
LP		 1577#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1578 struct nouveau_backlight *backlight;
1579#endif
77145f1c 1580 struct nvbios *bios = &drm->vbios;
9793083f 1581 bool lvds_dual = false, lvds_8bpc = false, hda = false;
344c2e5a
BS		 1582 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1583 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
83fc083c 1584
cd5609f7 1585 nv_connector = nv50_outp_get_new_connector(state, nv_encoder);
1b38cf6b 1586 nv_encoder->crtc = &nv_crtc->base;
6f8dbcf1
BS		 1587
1588 if ((disp->disp->object.oclass == GT214_DISP ||
1589 disp->disp->object.oclass >= GF110_DISP) &&
1590 drm_detect_monitor_audio(nv_connector->edid))
1591 hda = true;
e84a35a8 1592
3b6d83d1 1593 switch (nv_encoder->dcb->type) {
cb75d97e 1594 case DCB_OUTPUT_TMDS:
f530bc60
BS		 1595 if (disp->disp->object.oclass == NV50_DISP ||
1596 !drm_detect_hdmi_monitor(nv_connector->edid))
1597 nvif_outp_acquire_tmds(outp, nv_crtc->index, false, 0, 0, 0, false);
1598 else
1599 nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
1600
ea6143a8 1601 if (nv_encoder->outp.or.link & 1) {
344c2e5a 1602 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
16ef53a9
HM		 1603 /* Only enable dual-link if:
1604 * - Need to (i.e. rate > 165MHz)
1605 * - DCB says we can
1606 * - Not an HDMI monitor, since there's no dual-link
1607 * on HDMI.
1608 */
1609 if (mode->clock >= 165000 &&
1610 nv_encoder->dcb->duallink_possible &&
1611 !drm_detect_hdmi_monitor(nv_connector->edid))
344c2e5a 1612 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
3b6d83d1 1613 } else {
344c2e5a 1614 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
3b6d83d1 1615 }
3b6d83d1 1616 break;
cb75d97e 1617 case DCB_OUTPUT_LVDS:
344c2e5a 1618 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
419e8dc0 1619
3b6d83d1 1620 if (bios->fp_no_ddc) {
9793083f
BS		 1621 lvds_dual = bios->fp.dual_link;
1622 lvds_8bpc = bios->fp.if_is_24bit;
3b6d83d1 1623 } else {
befb51e9 1624 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3b6d83d1 1625 if (((u8 *)nv_connector->edid)[121] == 2)
9793083f 1626 lvds_dual = true;
3b6d83d1
BS		 1627 } else
1628 if (mode->clock >= bios->fp.duallink_transition_clk) {
9793083f 1629 lvds_dual = true;
3b6d83d1 1630 }
83fc083c 1631
9793083f 1632 if (lvds_dual) {
3b6d83d1 1633 if (bios->fp.strapless_is_24bit & 2)
9793083f 1634 lvds_8bpc = true;
3b6d83d1
BS		 1635 } else {
1636 if (bios->fp.strapless_is_24bit & 1)
9793083f 1637 lvds_8bpc = true;
3b6d83d1
BS		 1638 }
1639
ac2d9275 1640 if (asyh->or.bpc == 8)
9793083f 1641 lvds_8bpc = true;
3b6d83d1 1642 }
4a230fa6 1643
9793083f 1644 nvif_outp_acquire_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc);
3b6d83d1 1645 break;
cb75d97e 1646 case DCB_OUTPUT_DP:
81344372 1647 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, hda, false);
ac2d9275 1648 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
6e83fda2 1649
ea6143a8 1650 if (nv_encoder->outp.or.link & 1)
344c2e5a 1651 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
6e83fda2 1652 else
344c2e5a 1653 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
f20c665c 1654
1b38cf6b 1655 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
6eca310e
LP		 1656
1657#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1658 backlight = nv_connector->backlight;
1659 if (backlight && backlight->uses_dpcd)
1660 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
1661 (u16)backlight->dev->props.brightness);
1662#endif
1663
6e83fda2 1664 break;
3b6d83d1 1665 default:
af7db03e 1666 BUG();
3b6d83d1
BS		 1667 break;
1668 }
ff8ff503 1669
2ca7fb5c 1670 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
83fc083c
BS		 1671}
1672
f20c665c
BS		 1673static const struct drm_encoder_helper_funcs
1674nv50_sor_help = {
839ca903 1675 .atomic_check = nv50_outp_atomic_check,
fa9f9489
LP		 1676 .atomic_enable = nv50_sor_atomic_enable,
1677 .atomic_disable = nv50_sor_atomic_disable,
f20c665c
BS		 1678};
1679
83fc083c 1680static void
e225f446 1681nv50_sor_destroy(struct drm_encoder *encoder)
83fc083c 1682{
52aa30f2 1683 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1b255f1c
BS		 1684
1685 nvif_outp_dtor(&nv_encoder->outp);
1686
52aa30f2 1687 nv50_mstm_del(&nv_encoder->dp.mstm);
83fc083c 1688 drm_encoder_cleanup(encoder);
a0922278
LP		 1689
1690 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1691 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1692
83fc083c
BS		 1693 kfree(encoder);
1694}
1695
f20c665c
BS		 1696static const struct drm_encoder_funcs
1697nv50_sor_func = {
e225f446 1698 .destroy = nv50_sor_destroy,
83fc083c
BS		 1699};
1700
a76eb429 1701bool nv50_has_mst(struct nouveau_drm *drm)
5ff0cb1c
LP		 1702{
1703 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1704 u32 data;
1705 u8 ver, hdr, cnt, len;
1706
1707 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1708 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1709}
1710
83fc083c 1711static int
e225f446 1712nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
83fc083c 1713{
52aa30f2 1714 struct nouveau_connector *nv_connector = nouveau_connector(connector);
5ed50209 1715 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1167c6bc 1716 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
83fc083c
BS		 1717 struct nouveau_encoder *nv_encoder;
1718 struct drm_encoder *encoder;
4a2cb418 1719 struct nv50_disp *disp = nv50_disp(connector->dev);
52aa30f2 1720 int type, ret;
5ed50209
BS		 1721
1722 switch (dcbe->type) {
1723 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1724 case DCB_OUTPUT_TMDS:
1725 case DCB_OUTPUT_DP:
1726 default:
1727 type = DRM_MODE_ENCODER_TMDS;
1728 break;
1729 }
83fc083c
BS		 1730
1731 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1732 if (!nv_encoder)
1733 return -ENOMEM;
1734 nv_encoder->dcb = dcbe;
d665c7e9 1735 nv_encoder->update = nv50_sor_update;
83fc083c 1736
52aa30f2
BS		 1737 encoder = to_drm_encoder(nv_encoder);
1738 encoder->possible_crtcs = dcbe->heads;
1739 encoder->possible_clones = 0;
5a223dac
BS		 1740 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1741 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
f20c665c 1742 drm_encoder_helper_add(encoder, &nv50_sor_help);
52aa30f2 1743
cde4c44d 1744 drm_connector_attach_encoder(connector, encoder);
52aa30f2 1745
4a2cb418 1746 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
36dc1777 1747 nv50_outp_dump_caps(drm, nv_encoder);
4a2cb418 1748
2aa5eac5
BS		 1749 if (dcbe->type == DCB_OUTPUT_DP) {
1750 struct nvkm_i2c_aux *aux =
1751 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
4a2cb418 1752
a0922278
LP		 1753 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1754
2aa5eac5 1755 if (aux) {
0d4a2c57 1756 if (disp->disp->object.oclass < GF110_DISP) {
13a86519
BS		 1757 /* HW has no support for address-only
1758 * transactions, so we're required to
1759 * use custom I2C-over-AUX code.
1760 */
1761 nv_encoder->i2c = &aux->i2c;
1762 } else {
1763 nv_encoder->i2c = &nv_connector->aux.ddc;
1764 }
2aa5eac5
BS		 1765 nv_encoder->aux = aux;
1766 }
52aa30f2 1767
698c1aa9 1768 if (nv_connector->type != DCB_CONNECTOR_eDP &&
5ff0cb1c
LP		 1769 nv50_has_mst(drm)) {
1770 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1771 16, nv_connector->base.base.id,
52aa30f2
BS		 1772 &nv_encoder->dp.mstm);
1773 if (ret)
1774 return ret;
1775 }
2aa5eac5
BS		 1776 } else {
1777 struct nvkm_i2c_bus *bus =
1778 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1779 if (bus)
1780 nv_encoder->i2c = &bus->i2c;
1781 }
1782
1b255f1c 1783 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
83fc083c 1784}
26f6d88b 1785
eb6313ad
BS		 1786/******************************************************************************
1787 * PIOR
1788 *****************************************************************************/
839ca903
BS		 1789static int
1790nv50_pior_atomic_check(struct drm_encoder *encoder,
1791 struct drm_crtc_state *crtc_state,
1792 struct drm_connector_state *conn_state)
eb6313ad 1793{
839ca903
BS		 1794 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1795 if (ret)
1796 return ret;
1797 crtc_state->adjusted_mode.clock *= 2;
1798 return 0;
eb6313ad
BS		 1799}
1800
1801static void
fa9f9489 1802nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
eb6313ad 1803{
f20c665c 1804 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
0a368771 1805 struct nv50_core *core = nv50_disp(encoder->dev)->core;
344c2e5a 1806 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
f575f2bd 1807
ea6143a8 1808 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
f20c665c 1809 nv_encoder->crtc = NULL;
ea6143a8 1810 nvif_outp_release(&nv_encoder->outp);
eb6313ad
BS		 1811}
1812
1813static void
fa9f9489 1814nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
eb6313ad 1815{
eb6313ad 1816 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1b38cf6b
LP		 1817 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1818 struct nv50_head_atom *asyh =
1819 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
0a368771 1820 struct nv50_core *core = nv50_disp(encoder->dev)->core;
344c2e5a
BS		 1821 u32 ctrl = 0;
1822
1823 switch (nv_crtc->index) {
1824 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1825 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1826 default:
1827 WARN_ON(1);
1828 break;
1829 }
eb6313ad 1830
ac2d9275 1831 switch (asyh->or.bpc) {
344c2e5a
BS		 1832 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1833 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1834 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1835 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
eb6313ad
BS		 1836 }
1837
1838 switch (nv_encoder->dcb->type) {
1839 case DCB_OUTPUT_TMDS:
ea6143a8 1840 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
f530bc60 1841 nvif_outp_acquire_tmds(&nv_encoder->outp, false, false, 0, 0, 0, false);
ea6143a8 1842 break;
eb6313ad 1843 case DCB_OUTPUT_DP:
344c2e5a 1844 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
81344372 1845 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, false, false);
eb6313ad
BS		 1846 break;
1847 default:
af7db03e 1848 BUG();
eb6313ad
BS		 1849 break;
1850 }
1851
ea6143a8 1852 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
5c6fb4b2 1853 nv_encoder->crtc = &nv_crtc->base;
eb6313ad
BS		 1854}
1855
f20c665c
BS		 1856static const struct drm_encoder_helper_funcs
1857nv50_pior_help = {
839ca903 1858 .atomic_check = nv50_pior_atomic_check,
fa9f9489
LP		 1859 .atomic_enable = nv50_pior_atomic_enable,
1860 .atomic_disable = nv50_pior_atomic_disable,
eb6313ad
BS		 1861};
1862
f20c665c
BS		 1863static void
1864nv50_pior_destroy(struct drm_encoder *encoder)
1865{
1b255f1c
BS		 1866 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1867
1868 nvif_outp_dtor(&nv_encoder->outp);
1869
f20c665c
BS		 1870 drm_encoder_cleanup(encoder);
1871 kfree(encoder);
1872}
1873
1874static const struct drm_encoder_funcs
1875nv50_pior_func = {
eb6313ad
BS		 1876 .destroy = nv50_pior_destroy,
1877};
1878
1879static int
1880nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1881{
4a2cb418
LP		 1882 struct drm_device *dev = connector->dev;
1883 struct nouveau_drm *drm = nouveau_drm(dev);
1884 struct nv50_disp *disp = nv50_disp(dev);
1167c6bc 1885 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2aa5eac5
BS		 1886 struct nvkm_i2c_bus *bus = NULL;
1887 struct nvkm_i2c_aux *aux = NULL;
1888 struct i2c_adapter *ddc;
eb6313ad
BS		 1889 struct nouveau_encoder *nv_encoder;
1890 struct drm_encoder *encoder;
1891 int type;
1892
1893 switch (dcbe->type) {
1894 case DCB_OUTPUT_TMDS:
2aa5eac5
BS		 1895 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1896 ddc = bus ? &bus->i2c : NULL;
eb6313ad
BS		 1897 type = DRM_MODE_ENCODER_TMDS;
1898 break;
1899 case DCB_OUTPUT_DP:
2aa5eac5 1900 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
62b290fc 1901 ddc = aux ? &aux->i2c : NULL;
eb6313ad
BS		 1902 type = DRM_MODE_ENCODER_TMDS;
1903 break;
1904 default:
1905 return -ENODEV;
1906 }
1907
1908 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1909 if (!nv_encoder)
1910 return -ENOMEM;
1911 nv_encoder->dcb = dcbe;
eb6313ad 1912 nv_encoder->i2c = ddc;
2aa5eac5 1913 nv_encoder->aux = aux;
eb6313ad
BS		 1914
1915 encoder = to_drm_encoder(nv_encoder);
1916 encoder->possible_crtcs = dcbe->heads;
1917 encoder->possible_clones = 0;
5a223dac
BS		 1918 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1919 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
f20c665c 1920 drm_encoder_helper_add(encoder, &nv50_pior_help);
eb6313ad 1921
cde4c44d 1922 drm_connector_attach_encoder(connector, encoder);
4a2cb418
LP		 1923
1924 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
36dc1777 1925 nv50_outp_dump_caps(drm, nv_encoder);
4a2cb418 1926
1b255f1c 1927 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
eb6313ad
BS		 1928}
1929
839ca903
BS		 1930/******************************************************************************
1931 * Atomic
1932 *****************************************************************************/
1933
1934static void
df0c97e2 1935nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
839ca903 1936{
4d07b0bc
LP		 1937 struct drm_dp_mst_topology_mgr *mgr;
1938 struct drm_dp_mst_topology_state *mst_state;
df0c97e2 1939 struct nouveau_drm *drm = nouveau_drm(state->dev);
839ca903 1940 struct nv50_disp *disp = nv50_disp(drm->dev);
09e1b78a 1941 struct nv50_core *core = disp->core;
f479c0ba 1942 struct nv50_mstm *mstm;
4d07b0bc 1943 int i;
839ca903 1944
53e0a3e7 1945 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
839ca903 1946
4d07b0bc
LP		 1947 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
1948 mstm = nv50_mstm(mgr);
1949 if (mstm->modified)
1950 nv50_mstm_prepare(state, mst_state, mstm);
f479c0ba
BS		 1951 }
1952
09e1b78a
BS		 1953 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1954 core->func->update(core, interlock, true);
1955 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1956 disp->core->chan.base.device))
1957 NV_ERROR(drm, "core notifier timeout\n");
f479c0ba 1958
4d07b0bc
LP		 1959 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
1960 mstm = nv50_mstm(mgr);
1961 if (mstm->modified)
1962 nv50_mstm_cleanup(state, mst_state, mstm);
f479c0ba 1963 }
839ca903
BS		 1964}
1965
df0c97e2
BS		 1966static void
1967nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1968{
1969 struct drm_plane_state *new_plane_state;
1970 struct drm_plane *plane;
1971 int i;
1972
1973 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1974 struct nv50_wndw *wndw = nv50_wndw(plane);
1975 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1976 if (wndw->func->update)
1977 wndw->func->update(wndw, interlock);
1978 }
1979 }
1980}
1981
839ca903
BS		 1982static void
1983nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1984{
1985 struct drm_device *dev = state->dev;
efa47935 1986 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
839ca903 1987 struct drm_crtc *crtc;
3c847d6c 1988 struct drm_plane_state *new_plane_state;
839ca903
BS		 1989 struct drm_plane *plane;
1990 struct nouveau_drm *drm = nouveau_drm(dev);
1991 struct nv50_disp *disp = nv50_disp(dev);
1992 struct nv50_atom *atom = nv50_atom(state);
5bb88d07 1993 struct nv50_core *core = disp->core;
839ca903 1994 struct nv50_outp_atom *outp, *outt;
53e0a3e7 1995 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
839ca903 1996 int i;
2d786508 1997 bool flushed = false;
839ca903
BS		 1998
1999 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
12885ecb 2000 nv50_crc_atomic_stop_reporting(state);
839ca903
BS		 2001 drm_atomic_helper_wait_for_fences(dev, state, false);
2002 drm_atomic_helper_wait_for_dependencies(state);
a5c2c0d1 2003 drm_dp_mst_atomic_wait_for_dependencies(state);
839ca903 2004 drm_atomic_helper_update_legacy_modeset_state(dev, state);
441959eb 2005 drm_atomic_helper_calc_timestamping_constants(state);
839ca903
BS		 2006
2007 if (atom->lock_core)
2008 mutex_lock(&disp->mutex);
2009
2010 /* Disable head(s). */
efa47935 2011 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
3c847d6c 2012 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
839ca903
BS		 2013 struct nv50_head *head = nv50_head(crtc);
2014
2015 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2016 asyh->clr.mask, asyh->set.mask);
ed22eb56
LP		 2017
2018 if (old_crtc_state->active && !new_crtc_state->active) {
2019 pm_runtime_put_noidle(dev->dev);
4a5431af 2020 drm_crtc_vblank_off(crtc);
ed22eb56 2021 }
839ca903
BS		 2022
2023 if (asyh->clr.mask) {
2024 nv50_head_flush_clr(head, asyh, atom->flush_disable);
53e0a3e7 2025 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
839ca903
BS		 2026 }
2027 }
2028
2029 /* Disable plane(s). */
3c847d6c
ML		 2030 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2031 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
839ca903
BS		 2032 struct nv50_wndw *wndw = nv50_wndw(plane);
2033
2034 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2035 asyw->clr.mask, asyw->set.mask);
2036 if (!asyw->clr.mask)
2037 continue;
2038
53e0a3e7 2039 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
839ca903
BS		 2040 }
2041
2042 /* Disable output path(s). */
2043 list_for_each_entry(outp, &atom->outp, head) {
2044 const struct drm_encoder_helper_funcs *help;
2045 struct drm_encoder *encoder;
2046
2047 encoder = outp->encoder;
2048 help = encoder->helper_private;
2049
2050 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2051 outp->clr.mask, outp->set.mask);
2052
2053 if (outp->clr.mask) {
09838c4e 2054 help->atomic_disable(encoder, state);
53e0a3e7 2055 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
839ca903 2056 if (outp->flush_disable) {
df0c97e2
BS		 2057 nv50_disp_atomic_commit_wndw(state, interlock);
2058 nv50_disp_atomic_commit_core(state, interlock);
53e0a3e7 2059 memset(interlock, 0x00, sizeof(interlock));
2d786508
LP		 2060
2061 flushed = true;
839ca903
BS		 2062 }
2063 }
2064 }
2065
2066 /* Flush disable. */
53e0a3e7 2067 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
839ca903 2068 if (atom->flush_disable) {
df0c97e2
BS		 2069 nv50_disp_atomic_commit_wndw(state, interlock);
2070 nv50_disp_atomic_commit_core(state, interlock);
53e0a3e7 2071 memset(interlock, 0x00, sizeof(interlock));
2d786508
LP		 2072
2073 flushed = true;
839ca903
BS		 2074 }
2075 }
2076
2d786508
LP		 2077 if (flushed)
2078 nv50_crc_atomic_release_notifier_contexts(state);
2079 nv50_crc_atomic_init_notifier_contexts(state);
12885ecb 2080
839ca903
BS		 2081 /* Update output path(s). */
2082 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2083 const struct drm_encoder_helper_funcs *help;
2084 struct drm_encoder *encoder;
2085
2086 encoder = outp->encoder;
2087 help = encoder->helper_private;
2088
2089 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2090 outp->set.mask, outp->clr.mask);
2091
2092 if (outp->set.mask) {
09838c4e 2093 help->atomic_enable(encoder, state);
53e0a3e7 2094 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
839ca903
BS		 2095 }
2096
2097 list_del(&outp->head);
2098 kfree(outp);
2099 }
2100
2101 /* Update head(s). */
efa47935 2102 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
3c847d6c 2103 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
839ca903
BS		 2104 struct nv50_head *head = nv50_head(crtc);
2105
2106 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2107 asyh->set.mask, asyh->clr.mask);
2108
2109 if (asyh->set.mask) {
2110 nv50_head_flush_set(head, asyh);
53e0a3e7 2111 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
839ca903 2112 }
839ca903 2113
efa47935 2114 if (new_crtc_state->active) {
ed22eb56 2115 if (!old_crtc_state->active) {
4a5431af 2116 drm_crtc_vblank_on(crtc);
ed22eb56
LP		 2117 pm_runtime_get_noresume(dev->dev);
2118 }
efa47935 2119 if (new_crtc_state->event)
4a5431af
BS		 2120 drm_crtc_vblank_get(crtc);
2121 }
2b507893
BS		 2122 }
2123
5bb88d07
BS		 2124 /* Update window->head assignment.
2125 *
2126 * This has to happen in an update that's not interlocked with
2127 * any window channels to avoid hitting HW error checks.
2128 *
2129 *TODO: Proper handling of window ownership (Turing apparently
2130 * supports non-fixed mappings).
2131 */
2132 if (core->assign_windows) {
2133 core->func->wndw.owner(core);
705d9d02 2134 nv50_disp_atomic_commit_core(state, interlock);
5bb88d07
BS		 2135 core->assign_windows = false;
2136 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2137 }
2138
e78b1b54
BS		 2139 /* Finish updating head(s)...
2140 *
2141 * NVD is rather picky about both where window assignments can change,
2142 * *and* about certain core and window channel states matching.
2143 *
2144 * The EFI GOP driver on newer GPUs configures window channels with a
2145 * different output format to what we do, and the core channel update
2146 * in the assign_windows case above would result in a state mismatch.
2147 *
2148 * Delay some of the head update until after that point to workaround
2149 * the issue. This only affects the initial modeset.
2150 *
2151 * TODO: handle this better when adding flexible window mapping
2152 */
2153 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2154 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2155 struct nv50_head *head = nv50_head(crtc);
2156
2157 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2158 asyh->set.mask, asyh->clr.mask);
2159
2160 if (asyh->set.mask) {
2161 nv50_head_flush_set_wndw(head, asyh);
2162 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2163 }
2164 }
2165
839ca903 2166 /* Update plane(s). */
3c847d6c
ML		 2167 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2168 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
839ca903
BS		 2169 struct nv50_wndw *wndw = nv50_wndw(plane);
2170
2171 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2172 asyw->set.mask, asyw->clr.mask);
2173 if ( !asyw->set.mask &&
2174 (!asyw->clr.mask || atom->flush_disable))
2175 continue;
2176
53e0a3e7 2177 nv50_wndw_flush_set(wndw, interlock, asyw);
839ca903
BS		 2178 }
2179
2180 /* Flush update. */
df0c97e2 2181 nv50_disp_atomic_commit_wndw(state, interlock);
04fc14be 2182
53e0a3e7
BS		 2183 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2184 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
df0c97e2
BS		 2185 interlock[NV50_DISP_INTERLOCK_OVLY] ||
2186 interlock[NV50_DISP_INTERLOCK_WNDW] ||
53e0a3e7 2187 !atom->state.legacy_cursor_update)
df0c97e2 2188 nv50_disp_atomic_commit_core(state, interlock);
09e1b78a 2189 else
53e0a3e7 2190 disp->core->func->update(disp->core, interlock, false);
839ca903
BS		 2191 }
2192
2193 if (atom->lock_core)
2194 mutex_unlock(&disp->mutex);
2195
2196 /* Wait for HW to signal completion. */
3c847d6c
ML		 2197 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2198 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
839ca903
BS		 2199 struct nv50_wndw *wndw = nv50_wndw(plane);
2200 int ret = nv50_wndw_wait_armed(wndw, asyw);
2201 if (ret)
2202 NV_ERROR(drm, "%s: timeout\n", plane->name);
2203 }
2204
3c847d6c
ML		 2205 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2206 if (new_crtc_state->event) {
839ca903 2207 unsigned long flags;
bd9f6605 2208 /* Get correct count/ts if racing with vblank irq */
efa47935 2209 if (new_crtc_state->active)
0c697faf 2210 drm_crtc_accurate_vblank_count(crtc);
839ca903 2211 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3c847d6c 2212 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
839ca903 2213 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
efa47935 2214
3c847d6c 2215 new_crtc_state->event = NULL;
efa47935 2216 if (new_crtc_state->active)
4a5431af 2217 drm_crtc_vblank_put(crtc);
839ca903
BS		 2218 }
2219 }
2220
12885ecb 2221 nv50_crc_atomic_start_reporting(state);
2d786508
LP		 2222 if (!flushed)
2223 nv50_crc_atomic_release_notifier_contexts(state);
6eca310e 2224
839ca903
BS		 2225 drm_atomic_helper_commit_hw_done(state);
2226 drm_atomic_helper_cleanup_planes(dev, state);
2227 drm_atomic_helper_commit_cleanup_done(state);
2228 drm_atomic_state_put(state);
ed22eb56
LP		 2229
2230 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2231 pm_runtime_mark_last_busy(dev->dev);
2232 pm_runtime_put_autosuspend(dev->dev);
839ca903
BS		 2233}
2234
2235static void
2236nv50_disp_atomic_commit_work(struct work_struct *work)
2237{
2238 struct drm_atomic_state *state =
2239 container_of(work, typeof(*state), commit_work);
2240 nv50_disp_atomic_commit_tail(state);
2241}
2242
2243static int
2244nv50_disp_atomic_commit(struct drm_device *dev,
2245 struct drm_atomic_state *state, bool nonblock)
2246{
d324c5bc 2247 struct drm_plane_state *new_plane_state;
839ca903 2248 struct drm_plane *plane;
839ca903
BS		 2249 int ret, i;
2250
2251 ret = pm_runtime_get_sync(dev->dev);
a2cdf395
AP		 2252 if (ret < 0 && ret != -EACCES) {
2253 pm_runtime_put_autosuspend(dev->dev);
839ca903 2254 return ret;
a2cdf395 2255 }
839ca903
BS		 2256
2257 ret = drm_atomic_helper_setup_commit(state, nonblock);
2258 if (ret)
2259 goto done;
2260
2261 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2262
2263 ret = drm_atomic_helper_prepare_planes(dev, state);
2264 if (ret)
2265 goto done;
2266
2267 if (!nonblock) {
2268 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2269 if (ret)
813a7e16 2270 goto err_cleanup;
839ca903
BS		 2271 }
2272
8572636e
ML		 2273 ret = drm_atomic_helper_swap_state(state, true);
2274 if (ret)
2275 goto err_cleanup;
2276
d324c5bc
BS		 2277 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2278 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
839ca903 2279 struct nv50_wndw *wndw = nv50_wndw(plane);
3c847d6c 2280
ccd27db8
BS		 2281 if (asyw->set.image)
2282 nv50_wndw_ntfy_enable(wndw, asyw);
839ca903
BS		 2283 }
2284
839ca903
BS		 2285 drm_atomic_state_get(state);
2286
ed22eb56
LP		 2287 /*
2288 * Grab another RPM ref for the commit tail, which will release the
2289 * ref when it's finished
2290 */
2291 pm_runtime_get_noresume(dev->dev);
2292
839ca903
BS		 2293 if (nonblock)
2294 queue_work(system_unbound_wq, &state->commit_work);
2295 else
2296 nv50_disp_atomic_commit_tail(state);
2297
813a7e16
ML		 2298err_cleanup:
2299 if (ret)
2300 drm_atomic_helper_cleanup_planes(dev, state);
839ca903
BS		 2301done:
2302 pm_runtime_put_autosuspend(dev->dev);
2303 return ret;
2304}
2305
2306static struct nv50_outp_atom *
2307nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2308{
2309 struct nv50_outp_atom *outp;
2310
2311 list_for_each_entry(outp, &atom->outp, head) {
2312 if (outp->encoder == encoder)
2313 return outp;
2314 }
2315
2316 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2317 if (!outp)
2318 return ERR_PTR(-ENOMEM);
2319
2320 list_add(&outp->head, &atom->outp);
2321 outp->encoder = encoder;
2322 return outp;
2323}
2324
2325static int
2326nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
3c847d6c 2327 struct drm_connector_state *old_connector_state)
839ca903 2328{
3c847d6c
ML		 2329 struct drm_encoder *encoder = old_connector_state->best_encoder;
2330 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
839ca903
BS		 2331 struct drm_crtc *crtc;
2332 struct nv50_outp_atom *outp;
2333
3c847d6c 2334 if (!(crtc = old_connector_state->crtc))
839ca903
BS		 2335 return 0;
2336
3c847d6c
ML		 2337 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2338 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2339 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
839ca903
BS		 2340 outp = nv50_disp_outp_atomic_add(atom, encoder);
2341 if (IS_ERR(outp))
2342 return PTR_ERR(outp);
2343
2344 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2345 outp->flush_disable = true;
2346 atom->flush_disable = true;
2347 }
2348 outp->clr.ctrl = true;
2349 atom->lock_core = true;
2350 }
2351
2352 return 0;
2353}
2354
2355static int
2356nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2357 struct drm_connector_state *connector_state)
2358{
2359 struct drm_encoder *encoder = connector_state->best_encoder;
3c847d6c 2360 struct drm_crtc_state *new_crtc_state;
839ca903
BS		 2361 struct drm_crtc *crtc;
2362 struct nv50_outp_atom *outp;
2363
2364 if (!(crtc = connector_state->crtc))
2365 return 0;
2366
3c847d6c
ML		 2367 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2368 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
839ca903
BS		 2369 outp = nv50_disp_outp_atomic_add(atom, encoder);
2370 if (IS_ERR(outp))
2371 return PTR_ERR(outp);
2372
2373 outp->set.ctrl = true;
2374 atom->lock_core = true;
2375 }
2376
2377 return 0;
2378}
2379
2380static int
2381nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2382{
2383 struct nv50_atom *atom = nv50_atom(state);
dbdaf719 2384 struct nv50_core *core = nv50_disp(dev)->core;
3c847d6c 2385 struct drm_connector_state *old_connector_state, *new_connector_state;
839ca903 2386 struct drm_connector *connector;
119608a7
BS		 2387 struct drm_crtc_state *new_crtc_state;
2388 struct drm_crtc *crtc;
dbdaf719
LP		 2389 struct nv50_head *head;
2390 struct nv50_head_atom *asyh;
839ca903
BS		 2391 int ret, i;
2392
dbdaf719
LP		 2393 if (core->assign_windows && core->func->head->static_wndw_map) {
2394 drm_for_each_crtc(crtc, dev) {
2395 new_crtc_state = drm_atomic_get_crtc_state(state,
2396 crtc);
2397 if (IS_ERR(new_crtc_state))
2398 return PTR_ERR(new_crtc_state);
2399
2400 head = nv50_head(crtc);
2401 asyh = nv50_head_atom(new_crtc_state);
2402 core->func->head->static_wndw_map(head, asyh);
2403 }
2404 }
2405
119608a7
BS		 2406 /* We need to handle colour management on a per-plane basis. */
2407 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2408 if (new_crtc_state->color_mgmt_changed) {
2409 ret = drm_atomic_add_affected_planes(state, crtc);
2410 if (ret)
2411 return ret;
2412 }
2413 }
2414
839ca903
BS		 2415 ret = drm_atomic_helper_check(dev, state);
2416 if (ret)
2417 return ret;
2418
3c847d6c
ML		 2419 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2420 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
839ca903
BS		 2421 if (ret)
2422 return ret;
2423
3c847d6c 2424 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
839ca903
BS		 2425 if (ret)
2426 return ret;
2427 }
2428
232c9eec
LP		 2429 ret = drm_dp_mst_atomic_check(state);
2430 if (ret)
2431 return ret;
2432
2d786508
LP		 2433 nv50_crc_atomic_check_outp(atom);
2434
839ca903
BS		 2435 return 0;
2436}
2437
2438static void
2439nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2440{
2441 struct nv50_atom *atom = nv50_atom(state);
2442 struct nv50_outp_atom *outp, *outt;
2443
2444 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2445 list_del(&outp->head);
2446 kfree(outp);
2447 }
2448
2449 drm_atomic_state_default_clear(state);
2450}
2451
2452static void
2453nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2454{
2455 struct nv50_atom *atom = nv50_atom(state);
2456 drm_atomic_state_default_release(&atom->state);
2457 kfree(atom);
2458}
2459
2460static struct drm_atomic_state *
2461nv50_disp_atomic_state_alloc(struct drm_device *dev)
2462{
2463 struct nv50_atom *atom;
2464 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2465 drm_atomic_state_init(dev, &atom->state) < 0) {
2466 kfree(atom);
2467 return NULL;
2468 }
2469 INIT_LIST_HEAD(&atom->outp);
2470 return &atom->state;
2471}
2472
2473static const struct drm_mode_config_funcs
2474nv50_disp_func = {
2475 .fb_create = nouveau_user_framebuffer_create,
4a16dd9d 2476 .output_poll_changed = drm_fb_helper_output_poll_changed,
839ca903
BS		 2477 .atomic_check = nv50_disp_atomic_check,
2478 .atomic_commit = nv50_disp_atomic_commit,
2479 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2480 .atomic_state_clear = nv50_disp_atomic_state_clear,
2481 .atomic_state_free = nv50_disp_atomic_state_free,
2482};
2483
a5c2c0d1
LP		 2484static const struct drm_mode_config_helper_funcs
2485nv50_disp_helper_func = {
2486 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2487};
2488
26f6d88b
BS		 2489/******************************************************************************
2490 * Init
2491 *****************************************************************************/
ab0af559 2492
ba801ef0 2493static void
a0922278 2494nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
26f6d88b 2495{
a0922278 2496 struct nouveau_drm *drm = nouveau_drm(dev);
f479c0ba 2497 struct drm_encoder *encoder;
f479c0ba
BS		 2498
2499 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a0922278
LP		 2500 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2501 nv50_mstm_fini(nouveau_encoder(encoder));
f479c0ba 2502 }
a0922278
LP		 2503
2504 if (!runtime)
2505 cancel_work_sync(&drm->hpd_work);
26f6d88b
BS		 2506}
2507
ba801ef0 2508static int
0f9976dd 2509nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
26f6d88b 2510{
09e1b78a 2511 struct nv50_core *core = nv50_disp(dev)->core;
354d3508 2512 struct drm_encoder *encoder;
9f9bdaaf 2513
fa1232ea
LP		 2514 if (resume || runtime)
2515 core->func->init(core);
973f10c2 2516
354d3508
BS		 2517 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2518 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
9c5753bc
BS		 2519 struct nouveau_encoder *nv_encoder =
2520 nouveau_encoder(encoder);
a0922278 2521 nv50_mstm_init(nv_encoder, runtime);
354d3508
BS		 2522 }
2523 }
2524
9f9bdaaf 2525 return 0;
26f6d88b
BS		 2526}
2527
ba801ef0 2528static void
e225f446 2529nv50_display_destroy(struct drm_device *dev)
26f6d88b 2530{
e225f446 2531 struct nv50_disp *disp = nv50_disp(dev);
bdb8c212 2532
742db30c
TI		 2533 nv50_audio_component_fini(nouveau_drm(dev));
2534
4a2cb418 2535 nvif_object_unmap(&disp->caps);
9ac596a4 2536 nvif_object_dtor(&disp->caps);
9ca6f1eb 2537 nv50_core_del(&disp->core);
26f6d88b 2538
816af2f2 2539 nouveau_bo_unmap(disp->sync);
04c8c210
MS		 2540 if (disp->sync)
2541 nouveau_bo_unpin(disp->sync);
816af2f2 2542 nouveau_bo_ref(NULL, &disp->sync);
51beb428 2543
77145f1c 2544 nouveau_display(dev)->priv = NULL;
26f6d88b
BS		 2545 kfree(disp);
2546}
2547
2548int
e225f446 2549nv50_display_create(struct drm_device *dev)
26f6d88b 2550{
1167c6bc 2551 struct nvif_device *device = &nouveau_drm(dev)->client.device;
77145f1c 2552 struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c 2553 struct dcb_table *dcb = &drm->vbios.dcb;
83fc083c 2554 struct drm_connector *connector, *tmp;
e225f446 2555 struct nv50_disp *disp;
cb75d97e 2556 struct dcb_output *dcbe;
7c5f6a87 2557 int crtcs, ret, i;
5ff0cb1c 2558 bool has_mst = nv50_has_mst(drm);
26f6d88b
BS		 2559
2560 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2561 if (!disp)
2562 return -ENOMEM;
77145f1c 2563
839ca903
BS		 2564 mutex_init(&disp->mutex);
2565
77145f1c 2566 nouveau_display(dev)->priv = disp;
e225f446
BS		 2567 nouveau_display(dev)->dtor = nv50_display_destroy;
2568 nouveau_display(dev)->init = nv50_display_init;
2569 nouveau_display(dev)->fini = nv50_display_fini;
0ad72863 2570 disp->disp = &nouveau_display(dev)->disp;
839ca903 2571 dev->mode_config.funcs = &nv50_disp_func;
a5c2c0d1 2572 dev->mode_config.helper_private = &nv50_disp_helper_func;
0e94043e 2573 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
7a962f2b 2574 dev->mode_config.normalize_zpos = true;
26f6d88b 2575
b5a794b0 2576 /* small shared memory area we use for notifiers and semaphores */
81b61579
CK		 2577 ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2578 NOUVEAU_GEM_DOMAIN_VRAM,
bb6178b0 2579 0, 0x0000, NULL, NULL, &disp->sync);
b5a794b0 2580 if (!ret) {
81b61579 2581 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
04c8c210 2582 if (!ret) {
b5a794b0 2583 ret = nouveau_bo_map(disp->sync);
04c8c210
MS		 2584 if (ret)
2585 nouveau_bo_unpin(disp->sync);
2586 }
b5a794b0
BS		 2587 if (ret)
2588 nouveau_bo_ref(NULL, &disp->sync);
2589 }
2590
b5a794b0
BS		 2591 if (ret)
2592 goto out;
2593
2594 /* allocate master evo channel */
9ca6f1eb 2595 ret = nv50_core_new(drm, &disp->core);
b5a794b0
BS		 2596 if (ret)
2597 goto out;
2598
fa1232ea 2599 disp->core->func->init(disp->core);
4a2cb418
LP		 2600 if (disp->core->func->caps_init) {
2601 ret = disp->core->func->caps_init(drm, disp);
2602 if (ret)
2603 goto out;
2604 }
fa1232ea 2605
c586f30b
JJ		 2606 /* Assign the correct format modifiers */
2607 if (disp->disp->object.oclass >= TU102_DISP)
2608 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2609 else
05088314 2610 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
c586f30b
JJ		 2611 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2612 else
2613 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2614
d3999c1f
LP		 2615 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later
2616 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The
2617 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to
2618 * small page allocations in prepare_fb(). When this is implemented, we should also force
2619 * large pages (128K) for ovly fbs in order to fix Kepler ovlys.
2620 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2621 * large pages.
2622 */
2623 if (disp->disp->object.oclass >= GM107_DISP) {
d3b2f0f7
LP		 2624 dev->mode_config.cursor_width = 256;
2625 dev->mode_config.cursor_height = 256;
d3999c1f
LP		 2626 } else if (disp->disp->object.oclass >= GK104_DISP) {
2627 dev->mode_config.cursor_width = 128;
2628 dev->mode_config.cursor_height = 128;
d3b2f0f7
LP		 2629 } else {
2630 dev->mode_config.cursor_width = 64;
2631 dev->mode_config.cursor_height = 64;
2632 }
2633
438d99e3 2634 /* create crtc objects to represent the hw heads */
facaed62
BS		 2635 if (disp->disp->object.oclass >= GV100_DISP)
2636 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2637 else
0d4a2c57 2638 if (disp->disp->object.oclass >= GF110_DISP)
eba5e56d 2639 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
63718a07 2640 else
eba5e56d 2641 crtcs = 0x3;
63718a07 2642
eba5e56d 2643 for (i = 0; i < fls(crtcs); i++) {
5ff0cb1c
LP		 2644 struct nv50_head *head;
2645
eba5e56d
IM		 2646 if (!(crtcs & (1 << i)))
2647 continue;
5ff0cb1c
LP		 2648
2649 head = nv50_head_create(dev, i);
2650 if (IS_ERR(head)) {
2651 ret = PTR_ERR(head);
438d99e3 2652 goto out;
5ff0cb1c
LP		 2653 }
2654
2655 if (has_mst) {
2656 head->msto = nv50_msto_new(dev, head, i);
2657 if (IS_ERR(head->msto)) {
2658 ret = PTR_ERR(head->msto);
2659 head->msto = NULL;
2660 goto out;
2661 }
48140495
LP		 2662
2663 /*
2664 * FIXME: This is a hack to workaround the following
2665 * issues:
2666 *
2667 * https://gitlab.gnome.org/GNOME/mutter/issues/759
2668 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2669 *
2670 * Once these issues are closed, this should be
2671 * removed
2672 */
2673 head->msto->encoder.possible_crtcs = crtcs;
5ff0cb1c 2674 }
438d99e3
BS		 2675 }
2676
83fc083c
BS		 2677 /* create encoder/connector objects based on VBIOS DCB table */
2678 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
3c7fc252 2679 connector = nouveau_connector_create(dev, dcbe);
83fc083c
BS		 2680 if (IS_ERR(connector))
2681 continue;
2682
eb6313ad
BS		 2683 if (dcbe->location == DCB_LOC_ON_CHIP) {
2684 switch (dcbe->type) {
2685 case DCB_OUTPUT_TMDS:
2686 case DCB_OUTPUT_LVDS:
2687 case DCB_OUTPUT_DP:
2688 ret = nv50_sor_create(connector, dcbe);
2689 break;
2690 case DCB_OUTPUT_ANALOG:
2691 ret = nv50_dac_create(connector, dcbe);
2692 break;
2693 default:
2694 ret = -ENODEV;
2695 break;
2696 }
2697 } else {
2698 ret = nv50_pior_create(connector, dcbe);
83fc083c
BS		 2699 }
2700
eb6313ad
BS		 2701 if (ret) {
2702 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2703 dcbe->location, dcbe->type,
2704 ffs(dcbe->or) - 1, ret);
94f54f53 2705 ret = 0;
83fc083c
BS		 2706 }
2707 }
2708
2709 /* cull any connectors we created that don't have an encoder */
2710 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
62afb4ad 2711 if (connector->possible_encoders)
83fc083c
BS		 2712 continue;
2713
77145f1c 2714 NV_WARN(drm, "%s has no encoders, removing\n",
8c6c361a 2715 connector->name);
83fc083c
BS		 2716 connector->funcs->destroy(connector);
2717 }
2718
2ae4c5f6
MK		 2719 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2720 dev->vblank_disable_immediate = true;
2721
742db30c
TI		 2722 nv50_audio_component_init(drm);
2723
26f6d88b
BS		 2724out:
2725 if (ret)
e225f446 2726 nv50_display_destroy(dev);
26f6d88b
BS		 2727 return ret;
2728}
c586f30b
JJ		 2729
2730/******************************************************************************
2731 * Format modifiers
2732 *****************************************************************************/
2733
2734/****************************************************************
2735 * Log2(block height) ----------------------------+ *
2736 * Page Kind ----------------------------------+ | *
2737 * Gob Height/Page Kind Generation ------+ | | *
2738 * Sector layout -------+ | | | *
2739 * Compression ------+ | | | | */
2740const u64 disp50xx_modifiers[] = { /* | | | | | */
2741 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2742 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2743 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2744 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2745 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2746 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2747 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2748 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2749 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2750 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2751 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2752 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2753 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2754 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2755 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2756 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2757 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2758 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2759 DRM_FORMAT_MOD_LINEAR,
2760 DRM_FORMAT_MOD_INVALID
2761};
2762
2763/****************************************************************
2764 * Log2(block height) ----------------------------+ *
2765 * Page Kind ----------------------------------+ | *
2766 * Gob Height/Page Kind Generation ------+ | | *
2767 * Sector layout -------+ | | | *
2768 * Compression ------+ | | | | */
2769const u64 disp90xx_modifiers[] = { /* | | | | | */
2770 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2771 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2772 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2773 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2774 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2775 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2776 DRM_FORMAT_MOD_LINEAR,
2777 DRM_FORMAT_MOD_INVALID
2778};
Linux 6.x block layer and io_uring tree(s)