[linux-block.git] / drivers / gpu / drm / nouveau / dispnv04 / disp.h

#ifndef __NV04_DISPLAY_H__
#define __NV04_DISPLAY_H__

#include <subdev/bios/pll.h>

#include "nouveau_display.h"

enum nv04_fp_display_regs {
	FP_DISPLAY_END,
	FP_TOTAL,
	FP_CRTC,
	FP_SYNC_START,
	FP_SYNC_END,
	FP_VALID_START,
	FP_VALID_END
};

struct nv04_crtc_reg {
	unsigned char MiscOutReg;
	uint8_t CRTC[0xa0];
	uint8_t CR58[0x10];
	uint8_t Sequencer[5];
	uint8_t Graphics[9];
	uint8_t Attribute[21];
	unsigned char DAC[768];

	/* PCRTC regs */
	uint32_t fb_start;
	uint32_t crtc_cfg;
	uint32_t cursor_cfg;
	uint32_t gpio_ext;
	uint32_t crtc_830;
	uint32_t crtc_834;
	uint32_t crtc_850;
	uint32_t crtc_eng_ctrl;

	/* PRAMDAC regs */
	uint32_t nv10_cursync;
	struct nouveau_pll_vals pllvals;
	uint32_t ramdac_gen_ctrl;
	uint32_t ramdac_630;
	uint32_t ramdac_634;
	uint32_t tv_setup;
	uint32_t tv_vtotal;
	uint32_t tv_vskew;
	uint32_t tv_vsync_delay;
	uint32_t tv_htotal;
	uint32_t tv_hskew;
	uint32_t tv_hsync_delay;
	uint32_t tv_hsync_delay2;
	uint32_t fp_horiz_regs[7];
	uint32_t fp_vert_regs[7];
	uint32_t dither;
	uint32_t fp_control;
	uint32_t dither_regs[6];
	uint32_t fp_debug_0;
	uint32_t fp_debug_1;
	uint32_t fp_debug_2;
	uint32_t fp_margin_color;
	uint32_t ramdac_8c0;
	uint32_t ramdac_a20;
	uint32_t ramdac_a24;
	uint32_t ramdac_a34;
	uint32_t ctv_regs[38];
};

struct nv04_output_reg {
	uint32_t output;
	int head;
};

struct nv04_mode_state {
	struct nv04_crtc_reg crtc_reg[2];
	uint32_t pllsel;
	uint32_t sel_clk;
};

struct nv04_display {
	struct nv04_mode_state mode_reg;
	struct nv04_mode_state saved_reg;
	uint32_t saved_vga_font[4][16384];
	uint32_t dac_users[4];
	struct nouveau_object *core;
	struct nouveau_bo *image[2];
};

static inline struct nv04_display *
nv04_display(struct drm_device *dev)
{
	return nouveau_display(dev)->priv;
}

/* nv04_display.c */
int nv04_display_early_init(struct drm_device *);
void nv04_display_late_takedown(struct drm_device *);
int nv04_display_create(struct drm_device *);
void nv04_display_destroy(struct drm_device *);
int nv04_display_init(struct drm_device *);
void nv04_display_fini(struct drm_device *);

/* nv04_crtc.c */
int nv04_crtc_create(struct drm_device *, int index);

/* nv04_dac.c */
int nv04_dac_create(struct drm_connector *, struct dcb_output *);
uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
int nv04_dac_output_offset(struct drm_encoder *encoder);
void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
bool nv04_dac_in_use(struct drm_encoder *encoder);

/* nv04_dfp.c */
int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
			       int head, bool dl);
void nv04_dfp_disable(struct drm_device *dev, int head);
void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);

/* nv04_tv.c */
int nv04_tv_identify(struct drm_device *dev, int i2c_index);
int nv04_tv_create(struct drm_connector *, struct dcb_output *);

/* nv17_tv.c */
int nv17_tv_create(struct drm_connector *, struct dcb_output *);

static inline bool
nv_two_heads(struct drm_device *dev)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	const int impl = dev->pci_device & 0x0ff0;

	if (nv_device(drm->device)->card_type >= NV_10 && impl != 0x0100 &&
	    impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
		return true;

	return false;
}

static inline bool
nv_gf4_disp_arch(struct drm_device *dev)
{
	return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
}

static inline bool
nv_two_reg_pll(struct drm_device *dev)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	const int impl = dev->pci_device & 0x0ff0;

	if (impl == 0x0310 || impl == 0x0340 || nv_device(drm->device)->card_type >= NV_40)
		return true;
	return false;
}

static inline bool
nv_match_device(struct drm_device *dev, unsigned device,
		unsigned sub_vendor, unsigned sub_device)
{
	return dev->pdev->device == device &&
		dev->pdev->subsystem_vendor == sub_vendor &&
		dev->pdev->subsystem_device == sub_device;
}

#include <subdev/bios.h>
#include <subdev/bios/init.h>

static inline void
nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
			    struct dcb_output *outp, int crtc)
{
	struct nouveau_device *device = nouveau_dev(dev);
	struct nouveau_bios *bios = nouveau_bios(device);
	struct nvbios_init init = {
		.subdev = nv_subdev(bios),
		.bios = bios,
		.offset = table,
		.outp = outp,
		.crtc = crtc,
		.execute = 1,
	};

	nvbios_exec(&init);
}

#endif
Commit	Line	Data
017e6e29 BS	1	#ifndef __NV04_DISPLAY_H__
	2	#define __NV04_DISPLAY_H__
	3
51a3d342 BS	4	#include <subdev/bios/pll.h>
51a3d342 BS	5
77145f1c BS	6	#include "nouveau_display.h"
77145f1c BS	7
017e6e29 BS	8	enum nv04_fp_display_regs {
	9	FP_DISPLAY_END,
	10	FP_TOTAL,
	11	FP_CRTC,
	12	FP_SYNC_START,
	13	FP_SYNC_END,
	14	FP_VALID_START,
	15	FP_VALID_END
	16	};
	17
	18	struct nv04_crtc_reg {
	19	unsigned char MiscOutReg;
	20	uint8_t CRTC[0xa0];
	21	uint8_t CR58[0x10];
	22	uint8_t Sequencer[5];
	23	uint8_t Graphics[9];
	24	uint8_t Attribute[21];
	25	unsigned char DAC[768];
	26
	27	/* PCRTC regs */
	28	uint32_t fb_start;
	29	uint32_t crtc_cfg;
	30	uint32_t cursor_cfg;
	31	uint32_t gpio_ext;
	32	uint32_t crtc_830;
	33	uint32_t crtc_834;
	34	uint32_t crtc_850;
	35	uint32_t crtc_eng_ctrl;
	36
	37	/* PRAMDAC regs */
	38	uint32_t nv10_cursync;
	39	struct nouveau_pll_vals pllvals;
	40	uint32_t ramdac_gen_ctrl;
	41	uint32_t ramdac_630;
	42	uint32_t ramdac_634;
	43	uint32_t tv_setup;
	44	uint32_t tv_vtotal;
	45	uint32_t tv_vskew;
	46	uint32_t tv_vsync_delay;
	47	uint32_t tv_htotal;
	48	uint32_t tv_hskew;
	49	uint32_t tv_hsync_delay;
	50	uint32_t tv_hsync_delay2;
	51	uint32_t fp_horiz_regs[7];
	52	uint32_t fp_vert_regs[7];
	53	uint32_t dither;
	54	uint32_t fp_control;
	55	uint32_t dither_regs[6];
	56	uint32_t fp_debug_0;
	57	uint32_t fp_debug_1;
	58	uint32_t fp_debug_2;
	59	uint32_t fp_margin_color;
	60	uint32_t ramdac_8c0;
	61	uint32_t ramdac_a20;
	62	uint32_t ramdac_a24;
	63	uint32_t ramdac_a34;
	64	uint32_t ctv_regs[38];
	65	};
	66
	67	struct nv04_output_reg {
	68	uint32_t output;
	69	int head;
	70	};
	71
72	struct nv04_mode_state {
73	struct nv04_crtc_reg crtc_reg[2];
74	uint32_t pllsel;
75	uint32_t sel_clk;
76	};
77
78	struct nv04_display {
79	struct nv04_mode_state mode_reg;
80	struct nv04_mode_state saved_reg;
81	uint32_t saved_vga_font[4][16384];
82	uint32_t dac_users[4];
21a5ace0	83	struct nouveau_object *core;
78ae0ad4	84	struct nouveau_bo *image[2];
017e6e29 BS	85	};
017e6e29 BS	86
77145f1c BS	87	static inline struct nv04_display *
	88	nv04_display(struct drm_device *dev)
	89	{
	90	return nouveau_display(dev)->priv;
	91	}
	92
017e6e29 BS	93	/* nv04_display.c */
	94	int nv04_display_early_init(struct drm_device *);
	95	void nv04_display_late_takedown(struct drm_device *);
	96	int nv04_display_create(struct drm_device *);
	97	void nv04_display_destroy(struct drm_device *);
	98	int nv04_display_init(struct drm_device *);
	99	void nv04_display_fini(struct drm_device *);
	100
	101	/* nv04_crtc.c */
	102	int nv04_crtc_create(struct drm_device *, int index);
	103
	104	/* nv04_dac.c */
	105	int nv04_dac_create(struct drm_connector , struct dcb_output );
	106	uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
	107	int nv04_dac_output_offset(struct drm_encoder *encoder);
	108	void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
	109	bool nv04_dac_in_use(struct drm_encoder *encoder);
	110
	111	/* nv04_dfp.c */
	112	int nv04_dfp_create(struct drm_connector , struct dcb_output );
	113	int nv04_dfp_get_bound_head(struct drm_device dev, struct dcb_output dcbent);
	114	void nv04_dfp_bind_head(struct drm_device dev, struct dcb_output dcbent,
	115	int head, bool dl);
	116	void nv04_dfp_disable(struct drm_device *dev, int head);
	117	void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
	118
	119	/* nv04_tv.c */
	120	int nv04_tv_identify(struct drm_device *dev, int i2c_index);
	121	int nv04_tv_create(struct drm_connector , struct dcb_output );
	122
	123	/* nv17_tv.c */
	124	int nv17_tv_create(struct drm_connector , struct dcb_output );
	125
77145f1c BS	126	static inline bool
	127	nv_two_heads(struct drm_device *dev)
	128	{
	129	struct nouveau_drm *drm = nouveau_drm(dev);
	130	const int impl = dev->pci_device & 0x0ff0;
	131
	132	if (nv_device(drm->device)->card_type >= NV_10 && impl != 0x0100 &&
	133	impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
	134	return true;
	135
	136	return false;
	137	}
	138
	139	static inline bool
	140	nv_gf4_disp_arch(struct drm_device *dev)
	141	{
	142	return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
	143	}
	144
	145	static inline bool
	146	nv_two_reg_pll(struct drm_device *dev)
	147	{
	148	struct nouveau_drm *drm = nouveau_drm(dev);
	149	const int impl = dev->pci_device & 0x0ff0;
	150
	151	if (impl == 0x0310 \|\| impl == 0x0340 \|\| nv_device(drm->device)->card_type >= NV_40)
	152	return true;
	153	return false;
	154	}
	155
	156	static inline bool
	157	nv_match_device(struct drm_device *dev, unsigned device,
	158	unsigned sub_vendor, unsigned sub_device)
	159	{
	160	return dev->pdev->device == device &&
	161	dev->pdev->subsystem_vendor == sub_vendor &&
	162	dev->pdev->subsystem_device == sub_device;
	163	}
	164
	165	#include <subdev/bios.h>
	166	#include <subdev/bios/init.h>
	167
	168	static inline void
	169	nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
	170	struct dcb_output *outp, int crtc)
	171	{
	172	struct nouveau_device *device = nouveau_dev(dev);
	173	struct nouveau_bios *bios = nouveau_bios(device);
	174	struct nvbios_init init = {
	175	.subdev = nv_subdev(bios),
	176	.bios = bios,
	177	.offset = table,
	178	.outp = outp,
	179	.crtc = crtc,
	180	.execute = 1,
	181	};
	182
	183	nvbios_exec(&init);
	184	}
	185
017e6e29	186	#endif