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Merge tag 'bcachefs-2024-10-05' of git://evilpiepirate.org/bcachefs
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / dispnv04 / crtc.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
760285e7 25#include <drm/drm_crtc_helper.h>
690ae20c 26#include <drm/drm_fourcc.h>
874ee2d6 27#include <drm/drm_modeset_helper_vtables.h>
3cb9ae4f 28#include <drm/drm_plane_helper.h>
690ae20c 29#include <drm/drm_vblank.h>
6ee73861 30
4dc28134 31#include "nouveau_drv.h"
77145f1c 32#include "nouveau_reg.h"
4dc28134 33#include "nouveau_ttm.h"
77145f1c
BS		 34#include "nouveau_bo.h"
35#include "nouveau_gem.h"
6ee73861
BS		 36#include "nouveau_encoder.h"
37#include "nouveau_connector.h"
38#include "nouveau_crtc.h"
1a646342 39#include "hw.h"
6ee73861 40#include "nvreg.h"
1a646342 41#include "disp.h"
fcd6f048 42#include "nouveau_dma.h"
77145f1c
BS		 43
44#include <subdev/bios/pll.h>
f3867f43 45#include <subdev/clk.h>
6ee73861 46
105f756c
BS		 47#include <nvif/push006c.h>
48
12885ecb
LP		 49#include <nvif/event.h>
50#include <nvif/cl0046.h>
51
6ee73861
BS		 52static int
53nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
54 struct drm_framebuffer *old_fb);
55
56static void
57crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
58{
59 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
60 crtcstate->CRTC[index]);
61}
62
63static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
64{
65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 66 struct drm_device *dev = crtc->dev;
67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 68
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
70 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
73 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
74 }
75 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
76}
77
78static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
79{
80 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 81 struct drm_device *dev = crtc->dev;
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 83
84 nv_crtc->sharpness = level;
85 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
86 level += 0x40;
87 regp->ramdac_634 = level;
88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
89}
90
91#define PLLSEL_VPLL1_MASK \
92 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
93 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
94#define PLLSEL_VPLL2_MASK \
95 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
96 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
97#define PLLSEL_TV_MASK \
98 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
99 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
100 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
101 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
102
103/* NV4x 0x40.. pll notes:
104 * gpu pll: 0x4000 + 0x4004
105 * ?gpu? pll: 0x4008 + 0x400c
106 * vpll1: 0x4010 + 0x4014
107 * vpll2: 0x4018 + 0x401c
108 * mpll: 0x4020 + 0x4024
109 * mpll: 0x4038 + 0x403c
110 *
111 * the first register of each pair has some unknown details:
112 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
113 * bits 20-23: (mpll) something to do with post divider?
114 * bits 28-31: related to single stage mode? (bit 8/12)
115 */
116
117static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
118{
119 struct drm_device *dev = crtc->dev;
77145f1c 120 struct nouveau_drm *drm = nouveau_drm(dev);
6901f1d6
BS		 121 struct nvkm_bios *bios = nvxx_bios(drm);
122 struct nvkm_clk *clk = nvxx_clk(drm);
6ee73861 123 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
6ee73861 125 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
be83cd4e 126 struct nvkm_pll_vals *pv = &regp->pllvals;
70790f4f 127 struct nvbios_pll pll_lim;
6ee73861 128
77145f1c
BS		 129 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
130 &pll_lim))
6ee73861
BS		 131 return;
132
133 /* NM2 == 0 is used to determine single stage mode on two stage plls */
134 pv->NM2 = 0;
135
136 /* for newer nv4x the blob uses only the first stage of the vpll below a
137 * certain clock. for a certain nv4b this is 150MHz. since the max
138 * output frequency of the first stage for this card is 300MHz, it is
139 * assumed the threshold is given by vco1 maxfreq/2
140 */
141 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
142 * not 8, others unknown), the blob always uses both plls. no problem
143 * has yet been observed in allowing the use a single stage pll on all
144 * nv43 however. the behaviour of single stage use is untested on nv40
145 */
1167c6bc 146 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
6ee73861
BS		 147 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
148
77145f1c
BS		 149
150 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
6ee73861
BS		 151 return;
152
153 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
154
155 /* The blob uses this always, so let's do the same */
1167c6bc 156 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
6ee73861
BS		 157 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
158 /* again nv40 and some nv43 act more like nv3x as described above */
1167c6bc 159 if (drm->client.device.info.chipset < 0x41)
6ee73861
BS		 160 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
161 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
162 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
163
164 if (pv->NM2)
77145f1c 165 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
6ee73861
BS		 166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
167 else
77145f1c 168 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
6ee73861
BS		 169 pv->N1, pv->M1, pv->log2P);
170
171 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
172}
173
174static void
175nv_crtc_dpms(struct drm_crtc *crtc, int mode)
176{
177 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
77145f1c 179 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861
BS		 180 unsigned char seq1 = 0, crtc17 = 0;
181 unsigned char crtc1A;
182
77145f1c 183 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
6ee73861
BS		 184 nv_crtc->index);
185
25985edc 186 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
6ee73861
BS		 187 return;
188
189 nv_crtc->last_dpms = mode;
190
191 if (nv_two_heads(dev))
192 NVSetOwner(dev, nv_crtc->index);
193
194 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
195 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
196 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
197 switch (mode) {
198 case DRM_MODE_DPMS_STANDBY:
199 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
200 seq1 = 0x20;
201 crtc17 = 0x80;
202 crtc1A |= 0x80;
203 break;
204 case DRM_MODE_DPMS_SUSPEND:
205 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
206 seq1 = 0x20;
207 crtc17 = 0x80;
208 crtc1A |= 0x40;
209 break;
210 case DRM_MODE_DPMS_OFF:
211 /* Screen: Off; HSync: Off, VSync: Off */
212 seq1 = 0x20;
213 crtc17 = 0x00;
214 crtc1A |= 0xC0;
215 break;
216 case DRM_MODE_DPMS_ON:
217 default:
218 /* Screen: On; HSync: On, VSync: On */
219 seq1 = 0x00;
220 crtc17 = 0x80;
221 break;
222 }
223
224 NVVgaSeqReset(dev, nv_crtc->index, true);
225 /* Each head has it's own sequencer, so we can turn it off when we want */
226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
228 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
229 mdelay(10);
230 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
231 NVVgaSeqReset(dev, nv_crtc->index, false);
232
233 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
234}
235
6ee73861
BS		 236static void
237nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
238{
239 struct drm_device *dev = crtc->dev;
6ee73861 240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
f4510a27 242 struct drm_framebuffer *fb = crtc->primary->fb;
6ee73861
BS		 243
244 /* Calculate our timings */
e5ec882c
FJ		 245 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
246 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
247 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
6ee73861
BS		 248 int horizTotal = (mode->crtc_htotal >> 3) - 5;
249 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
250 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
251 int vertDisplay = mode->crtc_vdisplay - 1;
252 int vertStart = mode->crtc_vsync_start - 1;
253 int vertEnd = mode->crtc_vsync_end - 1;
254 int vertTotal = mode->crtc_vtotal - 2;
255 int vertBlankStart = mode->crtc_vdisplay - 1;
256 int vertBlankEnd = mode->crtc_vtotal - 1;
257
258 struct drm_encoder *encoder;
259 bool fp_output = false;
260
261 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
262 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
263
264 if (encoder->crtc == crtc &&
cb75d97e
BS		 265 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
266 nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
6ee73861
BS		 267 fp_output = true;
268 }
269
270 if (fp_output) {
271 vertStart = vertTotal - 3;
272 vertEnd = vertTotal - 2;
273 vertBlankStart = vertStart;
274 horizStart = horizTotal - 5;
275 horizEnd = horizTotal - 2;
276 horizBlankEnd = horizTotal + 4;
277#if 0
1167c6bc 278 if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
6ee73861
BS		 279 /* This reportedly works around some video overlay bandwidth problems */
280 horizTotal += 2;
281#endif
282 }
283
284 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
285 vertTotal |= 1;
286
287#if 0
288 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
289 ErrorF("horizStart: 0x%X \n", horizStart);
290 ErrorF("horizEnd: 0x%X \n", horizEnd);
291 ErrorF("horizTotal: 0x%X \n", horizTotal);
292 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
293 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
294 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
295 ErrorF("vertStart: 0x%X \n", vertStart);
296 ErrorF("vertEnd: 0x%X \n", vertEnd);
297 ErrorF("vertTotal: 0x%X \n", vertTotal);
298 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
299 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
300#endif
301
302 /*
303 * compute correct Hsync & Vsync polarity
304 */
305 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
306 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
307
308 regp->MiscOutReg = 0x23;
309 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
310 regp->MiscOutReg |= 0x40;
311 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
312 regp->MiscOutReg |= 0x80;
313 } else {
314 int vdisplay = mode->vdisplay;
315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
316 vdisplay *= 2;
317 if (mode->vscan > 1)
318 vdisplay *= mode->vscan;
319 if (vdisplay < 400)
320 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
321 else if (vdisplay < 480)
322 regp->MiscOutReg = 0x63; /* -hsync +vsync */
323 else if (vdisplay < 768)
324 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
325 else
326 regp->MiscOutReg = 0x23; /* +hsync +vsync */
327 }
328
6ee73861
BS		 329 /*
330 * Time Sequencer
331 */
332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
333 /* 0x20 disables the sequencer */
334 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
336 else
337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
341
342 /*
343 * CRTC
344 */
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
349 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
352 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
353 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
354 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
355 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
356 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
357 (1 << 4) |
358 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
359 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
360 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
361 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
364 1 << 6 |
365 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
372 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
374 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
375 /* framebuffer can be larger than crtc scanout area. */
01f2c773 376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
6ee73861
BS		 377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
378 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
379 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
382
383 /*
384 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
385 */
386
387 /* framebuffer can be larger than crtc scanout area. */
c1003d9c 388 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
01f2c773 389 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
c1003d9c 390 regp->CRTC[NV_CIO_CRE_42] =
01f2c773 391 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
393 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
394 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
395 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
396 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
397 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
398 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
399 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
400 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
401 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
402 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
403 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
404 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
405 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
406 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
407
408 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
409 horizTotal = (horizTotal >> 1) & ~1;
410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
411 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
412 } else
413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
414
415 /*
416 * Graphics Display Controller
417 */
418 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
419 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
420 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
421 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
422 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
425 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
426 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
427
428 regp->Attribute[0] = 0x00; /* standard colormap translation */
429 regp->Attribute[1] = 0x01;
430 regp->Attribute[2] = 0x02;
431 regp->Attribute[3] = 0x03;
432 regp->Attribute[4] = 0x04;
433 regp->Attribute[5] = 0x05;
434 regp->Attribute[6] = 0x06;
435 regp->Attribute[7] = 0x07;
436 regp->Attribute[8] = 0x08;
437 regp->Attribute[9] = 0x09;
438 regp->Attribute[10] = 0x0A;
439 regp->Attribute[11] = 0x0B;
440 regp->Attribute[12] = 0x0C;
441 regp->Attribute[13] = 0x0D;
442 regp->Attribute[14] = 0x0E;
443 regp->Attribute[15] = 0x0F;
444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
445 /* Non-vga */
446 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
447 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
448 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
449 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
450}
451
648c3814 452/*
6ee73861
BS		 453 * Sets up registers for the given mode/adjusted_mode pair.
454 *
455 * The clocks, CRTCs and outputs attached to this CRTC must be off.
456 *
457 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
458 * be easily turned on/off after this.
459 */
460static void
461nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
462{
463 struct drm_device *dev = crtc->dev;
77145f1c 464 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 465 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
d92df868 468 const struct drm_framebuffer *fb = crtc->primary->fb;
6ee73861
BS		 469 struct drm_encoder *encoder;
470 bool lvds_output = false, tmds_output = false, tv_output = false,
471 off_chip_digital = false;
472
473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
474 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
475 bool digital = false;
476
477 if (encoder->crtc != crtc)
478 continue;
479
cb75d97e 480 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
6ee73861 481 digital = lvds_output = true;
cb75d97e 482 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
6ee73861 483 tv_output = true;
cb75d97e 484 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
6ee73861
BS		 485 digital = tmds_output = true;
486 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
487 off_chip_digital = true;
488 }
489
490 /* Registers not directly related to the (s)vga mode */
491
492 /* What is the meaning of this register? */
493 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
495
496 regp->crtc_eng_ctrl = 0;
497 /* Except for rare conditions I2C is enabled on the primary crtc */
498 if (nv_crtc->index == 0)
499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
500#if 0
501 /* Set overlay to desired crtc. */
502 if (dev->overlayAdaptor) {
503 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
504 if (pPriv->overlayCRTC == nv_crtc->index)
505 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
506 }
507#endif
508
509 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
510 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
511 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
512 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
1167c6bc 513 if (drm->client.device.info.chipset >= 0x11)
6ee73861
BS		 514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
515 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
516 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
517
518 /* Unblock some timings */
519 regp->CRTC[NV_CIO_CRE_53] = 0;
520 regp->CRTC[NV_CIO_CRE_54] = 0;
521
522 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
523 if (lvds_output)
524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
525 else if (tmds_output)
526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
527 else
528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
529
530 /* These values seem to vary */
531 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
533
534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
535
536 /* probably a scratch reg, but kept for cargo-cult purposes:
537 * bit0: crtc0?, head A
538 * bit6: lvds, head A
539 * bit7: (only in X), head A
540 */
541 if (nv_crtc->index == 0)
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
543
544 /* The blob seems to take the current value from crtc 0, add 4 to that
545 * and reuse the old value for crtc 1 */
017e6e29 546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
6ee73861
BS		 547 if (!nv_crtc->index)
548 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
549
550 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
551 * 1 << 30 on 0x60.830), for no apparent reason */
552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
553
1167c6bc 554 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
4a9f822f
FJ		 555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
556
6ee73861
BS		 557 regp->crtc_830 = mode->crtc_vdisplay - 3;
558 regp->crtc_834 = mode->crtc_vdisplay - 1;
559
1167c6bc 560 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
6ee73861
BS		 561 /* This is what the blob does */
562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
563
1167c6bc 564 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
6ee73861
BS		 565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
566
1167c6bc 567 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
63f7fcfe
FJ		 568 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
569 else
570 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
6ee73861
BS		 571
572 /* Some misc regs */
1167c6bc 573 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
6ee73861
BS		 574 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
575 regp->CRTC[NV_CIO_CRE_86] = 0x1;
576 }
577
b00c600e 578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;
6ee73861
BS		 579 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
580 if (lvds_output || tmds_output || tv_output)
581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
582
583 /* Generic PRAMDAC regs */
584
1167c6bc 585 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
6ee73861
BS		 586 /* Only bit that bios and blob set. */
587 regp->nv10_cursync = (1 << 25);
588
589 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
590 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
591 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
b00c600e 592 if (fb->format->depth == 16)
6ee73861 593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
1167c6bc 594 if (drm->client.device.info.chipset >= 0x11)
6ee73861
BS		 595 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
596
597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
598 regp->tv_setup = 0;
599
600 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
601
602 /* Some values the blob sets */
603 regp->ramdac_8c0 = 0x100;
604 regp->ramdac_a20 = 0x0;
605 regp->ramdac_a24 = 0xfffff;
606 regp->ramdac_a34 = 0x1;
607}
608
78ae0ad4
BS		 609static int
610nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
611{
612 struct nv04_display *disp = nv04_display(crtc->dev);
18340587
TZ		 613 struct drm_framebuffer *fb = crtc->primary->fb;
614 struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]);
78ae0ad4
BS		 615 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
616 int ret;
617
81b61579 618 ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, false);
78ae0ad4 619 if (ret == 0) {
bf32a3a1
DK		 620 if (disp->image[nv_crtc->index]) {
621 struct nouveau_bo *bo = disp->image[nv_crtc->index];
622
623 nouveau_bo_unpin(bo);
624 drm_gem_object_put(&bo->bo.base);
625 }
626
627 drm_gem_object_get(&nvbo->bo.base);
628 disp->image[nv_crtc->index] = nvbo;
78ae0ad4
BS		 629 }
630
631 return ret;
632}
633
648c3814 634/*
6ee73861
BS		 635 * Sets up registers for the given mode/adjusted_mode pair.
636 *
637 * The clocks, CRTCs and outputs attached to this CRTC must be off.
638 *
639 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
640 * be easily turned on/off after this.
641 */
642static int
643nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
644 struct drm_display_mode *adjusted_mode,
645 int x, int y, struct drm_framebuffer *old_fb)
646{
647 struct drm_device *dev = crtc->dev;
648 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
77145f1c 649 struct nouveau_drm *drm = nouveau_drm(dev);
78ae0ad4 650 int ret;
6ee73861 651
77145f1c 652 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
6ee73861
BS		 653 drm_mode_debug_printmodeline(adjusted_mode);
654
78ae0ad4
BS		 655 ret = nv_crtc_swap_fbs(crtc, old_fb);
656 if (ret)
657 return ret;
658
6ee73861
BS		 659 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
660 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
661
662 nv_crtc_mode_set_vga(crtc, adjusted_mode);
663 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
1167c6bc 664 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
017e6e29 665 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
6ee73861
BS		 666 nv_crtc_mode_set_regs(crtc, adjusted_mode);
667 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
668 return 0;
669}
670
671static void nv_crtc_save(struct drm_crtc *crtc)
672{
673 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 674 struct drm_device *dev = crtc->dev;
675 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
6ee73861 676 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
017e6e29 677 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
6ee73861
BS		 678 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
679
680 if (nv_two_heads(crtc->dev))
681 NVSetOwner(crtc->dev, nv_crtc->index);
682
683 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
684
685 /* init some state to saved value */
686 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
687 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
688 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
689 crtc_state->gpio_ext = crtc_saved->gpio_ext;
690}
691
692static void nv_crtc_restore(struct drm_crtc *crtc)
693{
694 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 695 struct drm_device *dev = crtc->dev;
6ee73861 696 int head = nv_crtc->index;
017e6e29 697 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
6ee73861
BS		 698
699 if (nv_two_heads(crtc->dev))
700 NVSetOwner(crtc->dev, head);
701
017e6e29 702 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
6ee73861
BS		 703 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
704
705 nv_crtc->last_dpms = NV_DPMS_CLEARED;
706}
707
708static void nv_crtc_prepare(struct drm_crtc *crtc)
709{
710 struct drm_device *dev = crtc->dev;
77145f1c 711 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 712 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
d58ded76 713 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
6ee73861
BS		 714
715 if (nv_two_heads(dev))
716 NVSetOwner(dev, nv_crtc->index);
717
9bc6db0d 718 drm_crtc_vblank_off(crtc);
6ee73861
BS		 719 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
720
721 NVBlankScreen(dev, nv_crtc->index, true);
722
25985edc 723 /* Some more preparation. */
6ee73861 724 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
1167c6bc 725 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
6ee73861
BS		 726 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
727 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
728 }
729}
730
731static void nv_crtc_commit(struct drm_crtc *crtc)
732{
733 struct drm_device *dev = crtc->dev;
d58ded76 734 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
6ee73861
BS		 735 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
736
017e6e29 737 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
6ee73861
BS		 738 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
739
740#ifdef __BIG_ENDIAN
741 /* turn on LFB swapping */
742 {
743 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
744 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
745 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
746 }
747#endif
748
749 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
9bc6db0d 750 drm_crtc_vblank_on(crtc);
6ee73861
BS		 751}
752
753static void nv_crtc_destroy(struct drm_crtc *crtc)
754{
78ae0ad4 755 struct nv04_display *disp = nv04_display(crtc->dev);
6ee73861
BS		 756 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
757
6ee73861
BS		 758 if (!nv_crtc)
759 return;
760
761 drm_crtc_cleanup(crtc);
762
bf32a3a1
DK		 763 if (disp->image[nv_crtc->index]) {
764 struct nouveau_bo *bo = disp->image[nv_crtc->index];
765
766 nouveau_bo_unpin(bo);
767 drm_gem_object_put(&bo->bo.base);
768 disp->image[nv_crtc->index] = NULL;
769 }
78ae0ad4 770
9d59e8a1 771 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
04c8c210 772 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
bf32a3a1 773 nouveau_bo_fini(nv_crtc->cursor.nvbo);
ffd26641 774 nvif_event_dtor(&nv_crtc->vblank);
a2b7eadf 775 nvif_head_dtor(&nv_crtc->head);
6ee73861
BS		 776 kfree(nv_crtc);
777}
778
779static void
780nv_crtc_gamma_load(struct drm_crtc *crtc)
781{
782 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
783 struct drm_device *dev = nv_crtc->base.dev;
6ee73861 784 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
804ea3ec 785 u16 *r, *g, *b;
6ee73861
BS		 786 int i;
787
017e6e29 788 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
804ea3ec
PR		 789 r = crtc->gamma_store;
790 g = r + crtc->gamma_size;
791 b = g + crtc->gamma_size;
792
6ee73861 793 for (i = 0; i < 256; i++) {
804ea3ec
PR		 794 rgbs[i].r = *r++ >> 8;
795 rgbs[i].g = *g++ >> 8;
796 rgbs[i].b = *b++ >> 8;
6ee73861
BS		 797 }
798
017e6e29 799 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
6ee73861
BS		 800}
801
78ae0ad4
BS		 802static void
803nv_crtc_disable(struct drm_crtc *crtc)
804{
805 struct nv04_display *disp = nv04_display(crtc->dev);
806 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
bf32a3a1
DK		 807
808 if (disp->image[nv_crtc->index]) {
809 struct nouveau_bo *bo = disp->image[nv_crtc->index];
810
811 nouveau_bo_unpin(bo);
812 drm_gem_object_put(&bo->bo.base);
813 disp->image[nv_crtc->index] = NULL;
814 }
78ae0ad4
BS		 815}
816
7ea77283
ML		 817static int
818nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
6d124ff8
DV		 819 uint32_t size,
820 struct drm_modeset_acquire_ctx *ctx)
6ee73861
BS		 821{
822 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
6ee73861
BS		 823
824 /* We need to know the depth before we upload, but it's possible to
825 * get called before a framebuffer is bound. If this is the case,
826 * mark the lut values as dirty by setting depth==0, and it'll be
827 * uploaded on the first mode_set_base()
828 */
f4510a27 829 if (!nv_crtc->base.primary->fb) {
6ee73861 830 nv_crtc->lut.depth = 0;
7ea77283 831 return 0;
6ee73861
BS		 832 }
833
834 nv_crtc_gamma_load(crtc);
7ea77283
ML		 835
836 return 0;
6ee73861
BS		 837}
838
839static int
be64c2bb
CB		 840nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
841 struct drm_framebuffer *passed_fb,
842 int x, int y, bool atomic)
6ee73861
BS		 843{
844 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
845 struct drm_device *dev = crtc->dev;
77145f1c 846 struct nouveau_drm *drm = nouveau_drm(dev);
017e6e29 847 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
18340587 848 struct nouveau_bo *nvbo;
0e83bb4e 849 struct drm_framebuffer *drm_fb;
6ee73861 850 int arb_burst, arb_lwm;
6ee73861 851
77145f1c 852 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
0e83bb4e
EV		 853
854 /* no fb bound */
f4510a27 855 if (!atomic && !crtc->primary->fb) {
77145f1c 856 NV_DEBUG(drm, "No FB bound\n");
0e83bb4e
EV		 857 return 0;
858 }
859
be64c2bb 860 /* If atomic, we want to switch to the fb we were passed, so
78ae0ad4 861 * now we update pointers to do that.
be64c2bb
CB		 862 */
863 if (atomic) {
864 drm_fb = passed_fb;
f9ec8f6c 865 } else {
f4510a27 866 drm_fb = crtc->primary->fb;
6ee73861
BS		 867 }
868
18340587 869 nvbo = nouveau_gem_object(drm_fb->obj[0]);
60e9eabf 870 nv_crtc->fb.offset = nvbo->offset;
6ee73861 871
b00c600e
VS		 872 if (nv_crtc->lut.depth != drm_fb->format->depth) {
873 nv_crtc->lut.depth = drm_fb->format->depth;
6ee73861
BS		 874 nv_crtc_gamma_load(crtc);
875 }
876
877 /* Update the framebuffer format. */
878 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
b00c600e 879 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8;
6ee73861 880 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
b00c600e 881 if (drm_fb->format->depth == 16)
6ee73861
BS		 882 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
883 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
884 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
885 regp->ramdac_gen_ctrl);
886
01f2c773 887 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
6ee73861 888 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
01f2c773 889 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
c1003d9c 890 regp->CRTC[NV_CIO_CRE_42] =
01f2c773 891 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 892 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
893 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
c1003d9c 894 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
6ee73861
BS		 895
896 /* Update the framebuffer location. */
897 regp->fb_start = nv_crtc->fb.offset & ~3;
272725c7 898 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]);
5794b5fd 899 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
6ee73861
BS		 900
901 /* Update the arbitration parameters. */
272725c7 902 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8,
6ee73861
BS		 903 &arb_burst, &arb_lwm);
904
905 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
906 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
907 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
908 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
909
1167c6bc 910 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
6ee73861
BS		 911 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
912 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
913 }
914
915 return 0;
916}
917
be64c2bb
CB		 918static int
919nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
920 struct drm_framebuffer *old_fb)
921{
78ae0ad4
BS		 922 int ret = nv_crtc_swap_fbs(crtc, old_fb);
923 if (ret)
924 return ret;
be64c2bb
CB		 925 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
926}
927
928static int
929nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
930 struct drm_framebuffer *fb,
21c74a8e 931 int x, int y, enum mode_set_atomic state)
be64c2bb
CB		 932{
933 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
934}
935
6ee73861
BS		 936static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
937 struct nouveau_bo *dst)
938{
939 int width = nv_cursor_width(dev);
940 uint32_t pixel;
941 int i, j;
942
943 for (i = 0; i < width; i++) {
944 for (j = 0; j < width; j++) {
945 pixel = nouveau_bo_rd32(src, i*64 + j);
946
947 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
948 | (pixel & 0xf80000) >> 9
949 | (pixel & 0xf800) >> 6
950 | (pixel & 0xf8) >> 3);
951 }
952 }
953}
954
955static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
956 struct nouveau_bo *dst)
957{
958 uint32_t pixel;
959 int alpha, i;
960
961 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
962 * cursors (though NPM in combination with fp dithering may not work on
963 * nv11, from "nv" driver history)
964 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
965 * blob uses, however we get given PM cursors so we use PM mode
966 */
967 for (i = 0; i < 64 * 64; i++) {
968 pixel = nouveau_bo_rd32(src, i);
969
970 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
971 * than" shouldn't happen; fix "equal to" case by adding one to
972 * alpha channel (slightly inaccurate, but so is attempting to
973 * get back to NPM images, due to limits of integer precision)
974 */
975 alpha = pixel >> 24;
976 if (alpha > 0 && alpha < 255)
977 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
978
979#ifdef __BIG_ENDIAN
980 {
77145f1c 981 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 982
1167c6bc 983 if (drm->client.device.info.chipset == 0x11) {
6ee73861
BS		 984 pixel = ((pixel & 0x000000ff) << 24) |
985 ((pixel & 0x0000ff00) << 8) |
986 ((pixel & 0x00ff0000) >> 8) |
987 ((pixel & 0xff000000) >> 24);
988 }
989 }
990#endif
991
992 nouveau_bo_wr32(dst, i, pixel);
993 }
994}
995
996static int
997nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
998 uint32_t buffer_handle, uint32_t width, uint32_t height)
999{
77145f1c
BS		 1000 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1001 struct drm_device *dev = drm->dev;
6ee73861
BS		 1002 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1003 struct nouveau_bo *cursor = NULL;
1004 struct drm_gem_object *gem;
1005 int ret = 0;
1006
6ee73861
BS		 1007 if (!buffer_handle) {
1008 nv_crtc->cursor.hide(nv_crtc, true);
1009 return 0;
1010 }
1011
b4fa9d0f
MS		 1012 if (width != 64 || height != 64)
1013 return -EINVAL;
1014
a8ad0bd8 1015 gem = drm_gem_object_lookup(file_priv, buffer_handle);
6ee73861 1016 if (!gem)
bf79cb91 1017 return -ENOENT;
6ee73861
BS		 1018 cursor = nouveau_gem_object(gem);
1019
1020 ret = nouveau_bo_map(cursor);
1021 if (ret)
1022 goto out;
1023
1167c6bc 1024 if (drm->client.device.info.chipset >= 0x11)
6ee73861
BS		 1025 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1026 else
1027 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1028
1029 nouveau_bo_unmap(cursor);
0dc9b286 1030 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset;
6ee73861
BS		 1031 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1032 nv_crtc->cursor.show(nv_crtc, true);
1033out:
cdc194ce 1034 drm_gem_object_put(gem);
6ee73861
BS		 1035 return ret;
1036}
1037
1038static int
1039nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1040{
1041 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1042
1043 nv_crtc->cursor.set_pos(nv_crtc, x, y);
1044 return 0;
1045}
1046
fcd6f048
BS		 1047struct nv04_page_flip_state {
1048 struct list_head head;
1049 struct drm_pending_vblank_event *event;
1050 struct drm_crtc *crtc;
1051 int bpp, pitch;
1052 u64 offset;
1053};
1054
1055static int
1056nv04_finish_page_flip(struct nouveau_channel *chan,
1057 struct nv04_page_flip_state *ps)
1058{
1059 struct nouveau_fence_chan *fctx = chan->fence;
3543e84e 1060 struct nouveau_drm *drm = chan->cli->drm;
fcd6f048
BS		 1061 struct drm_device *dev = drm->dev;
1062 struct nv04_page_flip_state *s;
1063 unsigned long flags;
1064
1065 spin_lock_irqsave(&dev->event_lock, flags);
1066
1067 if (list_empty(&fctx->flip)) {
1068 NV_ERROR(drm, "unexpected pageflip\n");
1069 spin_unlock_irqrestore(&dev->event_lock, flags);
1070 return -EINVAL;
1071 }
1072
1073 s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head);
1074 if (s->event) {
1075 drm_crtc_arm_vblank_event(s->crtc, s->event);
1076 } else {
1077 /* Give up ownership of vblank for page-flipped crtc */
1078 drm_crtc_vblank_put(s->crtc);
1079 }
1080
1081 list_del(&s->head);
1082 if (ps)
1083 *ps = *s;
1084 kfree(s);
1085
1086 spin_unlock_irqrestore(&dev->event_lock, flags);
1087 return 0;
1088}
1089
1090int
801bc858 1091nv04_flip_complete(struct nvif_event *event, void *argv, u32 argc)
fcd6f048 1092{
801bc858
BS		 1093 struct nv04_display *disp = container_of(event, typeof(*disp), flip);
1094 struct nouveau_drm *drm = disp->drm;
fcd6f048
BS		 1095 struct nouveau_channel *chan = drm->channel;
1096 struct nv04_page_flip_state state;
1097
1098 if (!nv04_finish_page_flip(chan, &state)) {
1099 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc),
1100 state.offset + state.crtc->y *
1101 state.pitch + state.crtc->x *
1102 state.bpp / 8);
1103 }
1104
801bc858 1105 return NVIF_EVENT_KEEP;
fcd6f048
BS		 1106}
1107
1108static int
1109nv04_page_flip_emit(struct nouveau_channel *chan,
1110 struct nouveau_bo *old_bo,
1111 struct nouveau_bo *new_bo,
1112 struct nv04_page_flip_state *s,
1113 struct nouveau_fence **pfence)
1114{
1115 struct nouveau_fence_chan *fctx = chan->fence;
3543e84e 1116 struct nouveau_drm *drm = chan->cli->drm;
fcd6f048 1117 struct drm_device *dev = drm->dev;
0df26c0d 1118 struct nvif_push *push = &chan->chan.push;
fcd6f048
BS		 1119 unsigned long flags;
1120 int ret;
1121
1122 /* Queue it to the pending list */
1123 spin_lock_irqsave(&dev->event_lock, flags);
1124 list_add_tail(&s->head, &fctx->flip);
1125 spin_unlock_irqrestore(&dev->event_lock, flags);
1126
1127 /* Synchronize with the old framebuffer */
1128 ret = nouveau_fence_sync(old_bo, chan, false, false);
1129 if (ret)
1130 goto fail;
1131
1132 /* Emit the pageflip */
105f756c 1133 ret = PUSH_WAIT(push, 2);
fcd6f048
BS		 1134 if (ret)
1135 goto fail;
1136
105f756c
BS		 1137 PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
1138 PUSH_KICK(push);
fcd6f048 1139
978474dc 1140 ret = nouveau_fence_new(pfence, chan);
fcd6f048
BS		 1141 if (ret)
1142 goto fail;
1143
1144 return 0;
1145fail:
1146 spin_lock_irqsave(&dev->event_lock, flags);
1147 list_del(&s->head);
1148 spin_unlock_irqrestore(&dev->event_lock, flags);
1149 return ret;
1150}
1151
1152static int
1153nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1154 struct drm_pending_vblank_event *event, u32 flags,
1155 struct drm_modeset_acquire_ctx *ctx)
1156{
1157 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;
1158 struct drm_device *dev = crtc->dev;
1159 struct nouveau_drm *drm = nouveau_drm(dev);
18340587
TZ		 1160 struct drm_framebuffer *old_fb = crtc->primary->fb;
1161 struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]);
1162 struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]);
fcd6f048
BS		 1163 struct nv04_page_flip_state *s;
1164 struct nouveau_channel *chan;
1165 struct nouveau_cli *cli;
1166 struct nouveau_fence *fence;
1167 struct nv04_display *dispnv04 = nv04_display(dev);
c548b25c 1168 struct nvif_push *push;
fcd6f048
BS		 1169 int head = nouveau_crtc(crtc)->index;
1170 int ret;
1171
1172 chan = drm->channel;
1173 if (!chan)
1174 return -ENODEV;
5cca41ac 1175 cli = chan->cli;
0df26c0d 1176 push = &chan->chan.push;
fcd6f048
BS		 1177
1178 s = kzalloc(sizeof(*s), GFP_KERNEL);
1179 if (!s)
1180 return -ENOMEM;
1181
1182 if (new_bo != old_bo) {
81b61579 1183 ret = nouveau_bo_pin(new_bo, NOUVEAU_GEM_DOMAIN_VRAM, true);
fcd6f048
BS		 1184 if (ret)
1185 goto fail_free;
1186 }
1187
1188 mutex_lock(&cli->mutex);
1189 ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL);
1190 if (ret)
1191 goto fail_unpin;
1192
1193 /* synchronise rendering channel with the kernel's channel */
1194 ret = nouveau_fence_sync(new_bo, chan, false, true);
1195 if (ret) {
1196 ttm_bo_unreserve(&new_bo->bo);
1197 goto fail_unpin;
1198 }
1199
1200 if (new_bo != old_bo) {
1201 ttm_bo_unreserve(&new_bo->bo);
1202
1203 ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL);
1204 if (ret)
1205 goto fail_unpin;
1206 }
1207
1208 /* Initialize a page flip struct */
1209 *s = (struct nv04_page_flip_state)
1210 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0],
0dc9b286 1211 new_bo->offset };
fcd6f048
BS		 1212
1213 /* Keep vblanks on during flip, for the target crtc of this flip */
1214 drm_crtc_vblank_get(crtc);
1215
1216 /* Emit a page flip */
1217 if (swap_interval) {
c548b25c 1218 ret = PUSH_WAIT(push, 8);
fcd6f048
BS		 1219 if (ret)
1220 goto fail_unreserve;
1221
c548b25c
BS		 1222 PUSH_NVSQ(push, NV05F, 0x012c, 0);
1223 PUSH_NVSQ(push, NV05F, 0x0134, head);
1224 PUSH_NVSQ(push, NV05F, 0x0100, 0);
1225 PUSH_NVSQ(push, NV05F, 0x0130, 0);
fcd6f048
BS		 1226 }
1227
bf32a3a1
DK		 1228 if (dispnv04->image[head])
1229 drm_gem_object_put(&dispnv04->image[head]->bo.base);
1230
1231 drm_gem_object_get(&new_bo->bo.base);
1232 dispnv04->image[head] = new_bo;
fcd6f048
BS		 1233
1234 ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence);
1235 if (ret)
1236 goto fail_unreserve;
1237 mutex_unlock(&cli->mutex);
1238
1239 /* Update the crtc struct and cleanup */
1240 crtc->primary->fb = fb;
1241
1242 nouveau_bo_fence(old_bo, fence, false);
1243 ttm_bo_unreserve(&old_bo->bo);
1244 if (old_bo != new_bo)
1245 nouveau_bo_unpin(old_bo);
1246 nouveau_fence_unref(&fence);
1247 return 0;
1248
1249fail_unreserve:
1250 drm_crtc_vblank_put(crtc);
1251 ttm_bo_unreserve(&old_bo->bo);
1252fail_unpin:
1253 mutex_unlock(&cli->mutex);
1254 if (old_bo != new_bo)
1255 nouveau_bo_unpin(new_bo);
1256fail_free:
1257 kfree(s);
1258 return ret;
1259}
1260
6ee73861 1261static const struct drm_crtc_funcs nv04_crtc_funcs = {
6ee73861
BS		 1262 .cursor_set = nv04_crtc_cursor_set,
1263 .cursor_move = nv04_crtc_cursor_move,
1264 .gamma_set = nv_crtc_gamma_set,
2b7e7bb1 1265 .set_config = drm_crtc_helper_set_config,
fcd6f048 1266 .page_flip = nv04_crtc_page_flip,
6ee73861 1267 .destroy = nv_crtc_destroy,
91640a71
TZ		 1268 .enable_vblank = nouveau_display_vblank_enable,
1269 .disable_vblank = nouveau_display_vblank_disable,
1270 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
6ee73861
BS		 1271};
1272
1273static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1274 .dpms = nv_crtc_dpms,
1275 .prepare = nv_crtc_prepare,
1276 .commit = nv_crtc_commit,
6ee73861
BS		 1277 .mode_set = nv_crtc_mode_set,
1278 .mode_set_base = nv04_crtc_mode_set_base,
be64c2bb 1279 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
78ae0ad4 1280 .disable = nv_crtc_disable,
072a26c7 1281 .get_scanout_position = nouveau_display_scanoutpos,
6ee73861
BS		 1282};
1283
85671805
IM		 1284static const uint32_t modeset_formats[] = {
1285 DRM_FORMAT_XRGB8888,
1286 DRM_FORMAT_RGB565,
1287 DRM_FORMAT_XRGB1555,
1288};
1289
30c63715 1290static const struct drm_plane_funcs nv04_primary_plane_funcs = {
02d6f9a1 1291 DRM_PLANE_NON_ATOMIC_FUNCS,
30c63715
TZ		 1292};
1293
ffd26641
BS		 1294static int
1295nv04_crtc_vblank_handler(struct nvif_event *event, void *repv, u32 repc)
12885ecb 1296{
ffd26641 1297 struct nouveau_crtc *nv_crtc = container_of(event, struct nouveau_crtc, vblank);
12885ecb
LP		 1298
1299 drm_crtc_handle_vblank(&nv_crtc->base);
ffd26641 1300 return NVIF_EVENT_KEEP;
12885ecb
LP		 1301}
1302
6ee73861
BS		 1303int
1304nv04_crtc_create(struct drm_device *dev, int crtc_num)
1305{
12885ecb 1306 struct nouveau_display *disp = nouveau_display(dev);
6ee73861 1307 struct nouveau_crtc *nv_crtc;
e71def05 1308 struct drm_plane *primary;
804ea3ec 1309 int ret;
6ee73861
BS		 1310
1311 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1312 if (!nv_crtc)
1313 return -ENOMEM;
1314
6ee73861
BS		 1315 nv_crtc->lut.depth = 0;
1316
1317 nv_crtc->index = crtc_num;
1318 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1319
2c3d7715
DV		 1320 nv_crtc->save = nv_crtc_save;
1321 nv_crtc->restore = nv_crtc_restore;
1322
e71def05
TZ		 1323 primary = __drm_universal_plane_alloc(dev, sizeof(*primary), 0, 0,
1324 &nv04_primary_plane_funcs,
1325 modeset_formats,
1326 ARRAY_SIZE(modeset_formats), NULL,
1327 DRM_PLANE_TYPE_PRIMARY, NULL);
1328 if (IS_ERR(primary)) {
1329 ret = PTR_ERR(primary);
1330 kfree(nv_crtc);
1331 return ret;
1332 }
1333
1334 drm_crtc_init_with_planes(dev, &nv_crtc->base, primary, NULL,
85671805 1335 &nv04_crtc_funcs, NULL);
6ee73861
BS		 1336 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1337 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1338
bab7cc18 1339 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100,
81b61579 1340 NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, NULL, NULL,
bab7cc18 1341 &nv_crtc->cursor.nvbo);
6ee73861 1342 if (!ret) {
81b61579
CK		 1343 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo,
1344 NOUVEAU_GEM_DOMAIN_VRAM, false);
04c8c210 1345 if (!ret) {
6ee73861 1346 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
04c8c210
MS		 1347 if (ret)
1348 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1349 }
6ee73861 1350 if (ret)
bf32a3a1 1351 nouveau_bo_fini(nv_crtc->cursor.nvbo);
6ee73861
BS		 1352 }
1353
1354 nv04_cursor_init(nv_crtc);
1355
a2b7eadf
BS		 1356 ret = nvif_head_ctor(&disp->disp, nv_crtc->base.name, nv_crtc->index, &nv_crtc->head);
1357 if (ret)
1358 return ret;
1359
ffd26641
BS		 1360 return nvif_head_vblank_event_ctor(&nv_crtc->head, "kmsVbl", nv04_crtc_vblank_handler,
1361 false, &nv_crtc->vblank);
6ee73861 1362}
Linux 6.x block layer and io_uring tree(s)