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1 | /* |
2 | * Copyright 2014 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <subdev/fb.h> | |
26 | #include <subdev/timer.h> | |
27 | ||
95484b57 | 28 | #include "priv.h" |
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29 | |
30 | static void | |
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31 | gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) |
32 | { | |
33 | nv_wr32(priv, 0x17e270, start); | |
34 | nv_wr32(priv, 0x17e274, limit); | |
35 | nv_wr32(priv, 0x17e26c, 0x00000004); | |
36 | } | |
37 | ||
38 | static void | |
39 | gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv) | |
40 | { | |
41 | int c, s; | |
42 | for (c = 0; c < priv->ltc_nr; c++) { | |
43 | for (s = 0; s < priv->lts_nr; s++) | |
44 | nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0); | |
45 | } | |
46 | } | |
47 | ||
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48 | static void |
49 | gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4]) | |
50 | { | |
51 | nv_mask(priv, 0x17e338, 0x0000000f, i); | |
52 | nv_wr32(priv, 0x17e33c, color[0]); | |
53 | nv_wr32(priv, 0x17e340, color[1]); | |
54 | nv_wr32(priv, 0x17e344, color[2]); | |
55 | nv_wr32(priv, 0x17e348, color[3]); | |
56 | } | |
57 | ||
58 | static void | |
59 | gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) | |
60 | { | |
61 | nv_mask(priv, 0x17e338, 0x0000000f, i); | |
62 | nv_wr32(priv, 0x17e34c, depth); | |
63 | } | |
64 | ||
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65 | static void |
66 | gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts) | |
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67 | { |
68 | u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400); | |
69 | u32 stat = nv_rd32(priv, base + 0x00c); | |
70 | ||
71 | if (stat) { | |
72 | nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat); | |
73 | nv_wr32(priv, base + 0x00c, stat); | |
74 | } | |
75 | } | |
76 | ||
77 | static void | |
95484b57 | 78 | gm107_ltc_intr(struct nouveau_subdev *subdev) |
f6bad8ab | 79 | { |
95484b57 | 80 | struct nvkm_ltc_priv *priv = (void *)subdev; |
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81 | u32 mask; |
82 | ||
83 | mask = nv_rd32(priv, 0x00017c); | |
84 | while (mask) { | |
85 | u32 lts, ltc = __ffs(mask); | |
86 | for (lts = 0; lts < priv->lts_nr; lts++) | |
95484b57 | 87 | gm107_ltc_lts_isr(priv, ltc, lts); |
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88 | mask &= ~(1 << ltc); |
89 | } | |
90 | ||
91 | /* we do something horribly wrong and upset PMFB a lot, so mask off | |
92 | * interrupts from it after the first one until it's fixed | |
93 | */ | |
94 | nv_mask(priv, 0x000640, 0x02000000, 0x00000000); | |
95 | } | |
96 | ||
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97 | static int |
98 | gm107_ltc_init(struct nouveau_object *object) | |
f6bad8ab | 99 | { |
95484b57 | 100 | struct nvkm_ltc_priv *priv = (void *)object; |
fe3d9c4b | 101 | u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); |
95484b57 | 102 | int ret; |
f6bad8ab | 103 | |
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104 | ret = nvkm_ltc_init(priv); |
105 | if (ret) | |
106 | return ret; | |
f6bad8ab | 107 | |
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108 | nv_wr32(priv, 0x17e27c, priv->ltc_nr); |
109 | nv_wr32(priv, 0x17e278, priv->tag_base); | |
fe3d9c4b | 110 | nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); |
95484b57 | 111 | return 0; |
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112 | } |
113 | ||
114 | static int | |
95484b57 | 115 | gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
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116 | struct nouveau_oclass *oclass, void *data, u32 size, |
117 | struct nouveau_object **pobject) | |
118 | { | |
f6bad8ab | 119 | struct nouveau_fb *pfb = nouveau_fb(parent); |
95484b57 | 120 | struct nvkm_ltc_priv *priv; |
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121 | u32 parts, mask; |
122 | int ret, i; | |
123 | ||
95484b57 | 124 | ret = nvkm_ltc_create(parent, engine, oclass, &priv); |
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125 | *pobject = nv_object(priv); |
126 | if (ret) | |
127 | return ret; | |
128 | ||
129 | parts = nv_rd32(priv, 0x022438); | |
130 | mask = nv_rd32(priv, 0x021c14); | |
131 | for (i = 0; i < parts; i++) { | |
132 | if (!(mask & (1 << i))) | |
133 | priv->ltc_nr++; | |
134 | } | |
135 | priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28; | |
136 | ||
95484b57 | 137 | ret = gf100_ltc_init_tag_ram(pfb, priv); |
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138 | if (ret) |
139 | return ret; | |
140 | ||
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141 | return 0; |
142 | } | |
143 | ||
144 | struct nouveau_oclass * | |
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145 | gm107_ltc_oclass = &(struct nvkm_ltc_impl) { |
146 | .base.handle = NV_SUBDEV(LTC, 0xff), | |
147 | .base.ofuncs = &(struct nouveau_ofuncs) { | |
148 | .ctor = gm107_ltc_ctor, | |
149 | .dtor = gf100_ltc_dtor, | |
150 | .init = gm107_ltc_init, | |
151 | .fini = _nvkm_ltc_fini, | |
f6bad8ab | 152 | }, |
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153 | .intr = gm107_ltc_intr, |
154 | .cbc_clear = gm107_ltc_cbc_clear, | |
155 | .cbc_wait = gm107_ltc_cbc_wait, | |
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156 | .zbc = 16, |
157 | .zbc_clear_color = gm107_ltc_zbc_clear_color, | |
158 | .zbc_clear_depth = gm107_ltc_zbc_clear_depth, | |
95484b57 | 159 | }.base; |