[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / include / subdev / clock.h

#ifndef __NOUVEAU_CLOCK_H__
#define __NOUVEAU_CLOCK_H__

#include <core/device.h>
#include <core/subdev.h>

struct nouveau_pll_vals;
struct nvbios_pll;

enum nv_clk_src {
	nv_clk_src_crystal,
	nv_clk_src_href,

	nv_clk_src_hclk,
	nv_clk_src_hclkm3,
	nv_clk_src_hclkm3d2,
	nv_clk_src_hclkm2d3, /* NVAA */
	nv_clk_src_hclkm4, /* NVAA */
	nv_clk_src_cclk, /* NVAA */

	nv_clk_src_host,

	nv_clk_src_sppll0,
	nv_clk_src_sppll1,

	nv_clk_src_mpllsrcref,
	nv_clk_src_mpllsrc,
	nv_clk_src_mpll,
	nv_clk_src_mdiv,

	nv_clk_src_core,
	nv_clk_src_shader,

	nv_clk_src_mem,

	nv_clk_src_gpc,
	nv_clk_src_rop,
	nv_clk_src_hubk01,
	nv_clk_src_hubk06,
	nv_clk_src_hubk07,
	nv_clk_src_copy,
	nv_clk_src_daemon,
	nv_clk_src_disp,
	nv_clk_src_vdec,

	nv_clk_src_dom6,

	nv_clk_src_max,
};

struct nouveau_cstate {
	struct list_head head;
	u8  voltage;
	u32 domain[nv_clk_src_max];
};

struct nouveau_pstate {
	struct list_head head;
	struct list_head list; /* c-states */
	struct nouveau_cstate base;
	u8 pstate;
	u8 fanspeed;
};

struct nouveau_clock {
	struct nouveau_subdev base;

	struct nouveau_clocks *domains;
	struct nouveau_pstate bstate;

	struct list_head states;
	int state_nr;

	int pstate; /* current */
	int ustate; /* user-requested (-1 disabled, -2 perfmon) */
	int astate; /* perfmon adjustment (base) */
	int tstate; /* thermal adjustment (max-) */
	int dstate; /* display adjustment (min+) */

	int  (*read)(struct nouveau_clock *, enum nv_clk_src);
	int  (*calc)(struct nouveau_clock *, struct nouveau_cstate *);
	int  (*prog)(struct nouveau_clock *);
	void (*tidy)(struct nouveau_clock *);

	/*XXX: die, these are here *only* to support the completely
	 *     bat-shit insane what-was-nouveau_hw.c code
	 */
	int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *,
			int clk, struct nouveau_pll_vals *pv);
	int (*pll_prog)(struct nouveau_clock *, u32 reg1,
			struct nouveau_pll_vals *pv);
};

static inline struct nouveau_clock *
nouveau_clock(void *obj)
{
	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK];
}

struct nouveau_clocks {
	enum nv_clk_src name;
	u8 bios; /* 0xff for none */
#define NVKM_CLK_DOM_FLAG_CORE 0x01
	u8 flags;
	const char *mname;
	int mdiv;
};

#define nouveau_clock_create(p,e,o,i,d)                                        \
	nouveau_clock_create_((p), (e), (o), (i), sizeof(**d), (void **)d)
#define nouveau_clock_destroy(p) ({                                            \
	struct nouveau_clock *clk = (p);                                       \
	_nouveau_clock_dtor(nv_object(clk));                                   \
})
#define nouveau_clock_init(p) ({                                               \
	struct nouveau_clock *clk = (p);                                       \
	_nouveau_clock_init(nv_object(clk));                                   \
})
#define nouveau_clock_fini(p,s)                                                \
	nouveau_subdev_fini(&(p)->base, (s))

int  nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
			   struct nouveau_oclass *,
			   struct nouveau_clocks *, int, void **);
void _nouveau_clock_dtor(struct nouveau_object *);
int _nouveau_clock_init(struct nouveau_object *);
#define _nouveau_clock_fini _nouveau_subdev_fini

extern struct nouveau_oclass nv04_clock_oclass;
extern struct nouveau_oclass nv40_clock_oclass;
extern struct nouveau_oclass *nv50_clock_oclass;
extern struct nouveau_oclass *nv84_clock_oclass;
extern struct nouveau_oclass *nvaa_clock_oclass;
extern struct nouveau_oclass nva3_clock_oclass;
extern struct nouveau_oclass nvc0_clock_oclass;
extern struct nouveau_oclass nve0_clock_oclass;

int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
			int clk, struct nouveau_pll_vals *);
int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
			struct nouveau_pll_vals *);
int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
			int clk, struct nouveau_pll_vals *);

int nouveau_clock_ustate(struct nouveau_clock *, int req);
int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);

#endif
Commit	Line	Data
8aceb7de BS	1	#ifndef __NOUVEAU_CLOCK_H__
	2	#define __NOUVEAU_CLOCK_H__
	3
	4	#include <core/device.h>
	5	#include <core/subdev.h>
	6
70790f4f BS	7	struct nouveau_pll_vals;
	8	struct nvbios_pll;
	9
7c856522 BS	10	enum nv_clk_src {
	11	nv_clk_src_crystal,
	12	nv_clk_src_href,
	13
	14	nv_clk_src_hclk,
	15	nv_clk_src_hclkm3,
	16	nv_clk_src_hclkm3d2,
a7e4201f RS	17	nv_clk_src_hclkm2d3, /* NVAA */
	18	nv_clk_src_hclkm4, /* NVAA */
	19	nv_clk_src_cclk, /* NVAA */
7c856522 BS	20
	21	nv_clk_src_host,
	22
	23	nv_clk_src_sppll0,
	24	nv_clk_src_sppll1,
	25
	26	nv_clk_src_mpllsrcref,
	27	nv_clk_src_mpllsrc,
	28	nv_clk_src_mpll,
	29	nv_clk_src_mdiv,
	30
	31	nv_clk_src_core,
	32	nv_clk_src_shader,
	33
	34	nv_clk_src_mem,
	35
	36	nv_clk_src_gpc,
	37	nv_clk_src_rop,
	38	nv_clk_src_hubk01,
	39	nv_clk_src_hubk06,
	40	nv_clk_src_hubk07,
	41	nv_clk_src_copy,
	42	nv_clk_src_daemon,
	43	nv_clk_src_disp,
	44	nv_clk_src_vdec,
	45
	46	nv_clk_src_dom6,
	47
	48	nv_clk_src_max,
	49	};
	50
	51	struct nouveau_cstate {
	52	struct list_head head;
	53	u8 voltage;
	54	u32 domain[nv_clk_src_max];
	55	};
	56
	57	struct nouveau_pstate {
	58	struct list_head head;
	59	struct list_head list; /* c-states */
	60	struct nouveau_cstate base;
	61	u8 pstate;
	62	u8 fanspeed;
	63	};
	64
8aceb7de BS	65	struct nouveau_clock {
8aceb7de BS	66	struct nouveau_subdev base;
70790f4f	67
7c856522 BS	68	struct nouveau_clocks *domains;
	69	struct nouveau_pstate bstate;
	70
	71	struct list_head states;
	72	int state_nr;
	73
	74	int pstate; /* current */
	75	int ustate; /* user-requested (-1 disabled, -2 perfmon) */
	76	int astate; /* perfmon adjustment (base) */
	77	int tstate; /* thermal adjustment (max-) */
	78	int dstate; /* display adjustment (min+) */
	79
	80	int (read)(struct nouveau_clock , enum nv_clk_src);
	81	int (calc)(struct nouveau_clock , struct nouveau_cstate *);
	82	int (prog)(struct nouveau_clock );
	83	void (tidy)(struct nouveau_clock );
	84
70790f4f BS	85	/XXX: die, these are here only* to support the completely
	86	* bat-shit insane what-was-nouveau_hw.c code
	87	*/
	88	int (pll_calc)(struct nouveau_clock , struct nvbios_pll *,
	89	int clk, struct nouveau_pll_vals *pv);
	90	int (pll_prog)(struct nouveau_clock , u32 reg1,
	91	struct nouveau_pll_vals *pv);
8aceb7de BS	92	};
	93
	94	static inline struct nouveau_clock *
	95	nouveau_clock(void *obj)
	96	{
	97	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK];
	98	}
	99
7c856522 BS	100	struct nouveau_clocks {
	101	enum nv_clk_src name;
	102	u8 bios; /* 0xff for none */
	103	#define NVKM_CLK_DOM_FLAG_CORE 0x01
	104	u8 flags;
	105	const char *mname;
	106	int mdiv;
	107	};
	108
	109	#define nouveau_clock_create(p,e,o,i,d) \
	110	nouveau_clock_create_((p), (e), (o), (i), sizeof(d), (void )d)
	111	#define nouveau_clock_destroy(p) ({ \
	112	struct nouveau_clock *clk = (p); \
	113	_nouveau_clock_dtor(nv_object(clk)); \
	114	})
	115	#define nouveau_clock_init(p) ({ \
	116	struct nouveau_clock *clk = (p); \
	117	_nouveau_clock_init(nv_object(clk)); \
	118	})
8aceb7de BS	119	#define nouveau_clock_fini(p,s) \
	120	nouveau_subdev_fini(&(p)->base, (s))
	121
	122	int nouveau_clock_create_(struct nouveau_object , struct nouveau_object ,
7c856522 BS	123	struct nouveau_oclass *,
	124	struct nouveau_clocks , int, void *);
	125	void _nouveau_clock_dtor(struct nouveau_object *);
	126	int _nouveau_clock_init(struct nouveau_object *);
8aceb7de BS	127	#define _nouveau_clock_fini _nouveau_subdev_fini
	128
	129	extern struct nouveau_oclass nv04_clock_oclass;
	130	extern struct nouveau_oclass nv40_clock_oclass;
7c856522 BS	131	extern struct nouveau_oclass *nv50_clock_oclass;
7c856522 BS	132	extern struct nouveau_oclass *nv84_clock_oclass;
a7e4201f	133	extern struct nouveau_oclass *nvaa_clock_oclass;
8aceb7de BS	134	extern struct nouveau_oclass nva3_clock_oclass;
8aceb7de BS	135	extern struct nouveau_oclass nvc0_clock_oclass;
7c856522	136	extern struct nouveau_oclass nve0_clock_oclass;
8aceb7de	137
70790f4f BS	138	int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
	139	int nv04_clock_pll_calc(struct nouveau_clock , struct nvbios_pll ,
	140	int clk, struct nouveau_pll_vals *);
	141	int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
	142	struct nouveau_pll_vals *);
d9c39056 ML	143	int nva3_clock_pll_calc(struct nouveau_clock , struct nvbios_pll ,
d9c39056 ML	144	int clk, struct nouveau_pll_vals *);
70790f4f	145
7c856522 BS	146	int nouveau_clock_ustate(struct nouveau_clock *, int req);
	147	int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
	148	int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
	149	int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
	150
8aceb7de	151	#endif