Commit | Line | Data |
---|---|---|
4b223eef BS |
1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
966a5b7d | 25 | #include <linux/firmware.h> |
e0cd3608 | 26 | #include <linux/module.h> |
966a5b7d | 27 | |
4b223eef BS |
28 | #include "drmP.h" |
29 | ||
30 | #include "nouveau_drv.h" | |
02a841d4 BS |
31 | #include <core/mm.h> |
32 | #include <engine/fifo.h> | |
0411de85 | 33 | |
02a841d4 BS |
34 | #include "nvc0.h" |
35 | #include "fuc/hubnvc0.fuc.h" | |
36 | #include "fuc/gpcnvc0.fuc.h" | |
0411de85 BS |
37 | |
38 | static void | |
39 | nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base) | |
40 | { | |
41 | NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base, | |
42 | nv_rd32(dev, base + 0x400)); | |
43 | NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, | |
44 | nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804), | |
45 | nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c)); | |
46 | NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, | |
47 | nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814), | |
48 | nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c)); | |
49 | } | |
50 | ||
ac1499d9 | 51 | void |
0411de85 BS |
52 | nvc0_graph_ctxctl_debug(struct drm_device *dev) |
53 | { | |
54 | u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff; | |
55 | u32 gpc; | |
56 | ||
57 | nvc0_graph_ctxctl_debug_unit(dev, 0x409000); | |
58 | for (gpc = 0; gpc < gpcnr; gpc++) | |
59 | nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000)); | |
60 | } | |
966a5b7d | 61 | |
ac1499d9 BS |
62 | int |
63 | nvc0_graph_context_new(struct nouveau_channel *chan, int engine) | |
966a5b7d | 64 | { |
966a5b7d | 65 | struct drm_device *dev = chan->dev; |
ac1499d9 BS |
66 | struct nvc0_graph_priv *priv = nv_engine(dev, engine); |
67 | struct nvc0_graph_data *data = priv->mmio_data; | |
68 | struct nvc0_graph_mmio *mmio = priv->mmio_list; | |
69 | struct nvc0_graph_chan *grch; | |
70 | struct nouveau_gpuobj *grctx; | |
966a5b7d | 71 | int ret, i; |
966a5b7d | 72 | |
ac1499d9 BS |
73 | grch = kzalloc(sizeof(*grch), GFP_KERNEL); |
74 | if (!grch) | |
966a5b7d | 75 | return -ENOMEM; |
ac1499d9 | 76 | chan->engctx[NVOBJ_ENGINE_GR] = grch; |
966a5b7d | 77 | |
ac1499d9 | 78 | ret = nouveau_gpuobj_new(dev, NULL, priv->size, 256, 0, &grch->grctx); |
60f7ab06 | 79 | if (ret) |
ac1499d9 | 80 | goto error; |
966a5b7d | 81 | |
ac1499d9 BS |
82 | ret = nouveau_gpuobj_map_vm(grch->grctx, chan->vm, NV_MEM_ACCESS_RW | |
83 | NV_MEM_ACCESS_SYS, &grch->grctx_vma); | |
966a5b7d BS |
84 | if (ret) |
85 | return ret; | |
86 | ||
ac1499d9 | 87 | grctx = grch->grctx; |
966a5b7d | 88 | |
ac1499d9 BS |
89 | /* allocate memory for a "mmio list" buffer that's used by the HUB |
90 | * fuc to modify some per-context register settings on first load | |
91 | * of the context. | |
92 | */ | |
93 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x100, 0, &grch->mmio); | |
73a60c0d BS |
94 | if (ret) |
95 | return ret; | |
96 | ||
ac1499d9 | 97 | ret = nouveau_gpuobj_map_vm(grch->mmio, chan->vm, |
3863c9bc | 98 | NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, |
ac1499d9 | 99 | &grch->mmio_vma); |
73a60c0d BS |
100 | if (ret) |
101 | return ret; | |
102 | ||
ac1499d9 BS |
103 | /* allocate buffers referenced by mmio list */ |
104 | for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { | |
105 | ret = nouveau_gpuobj_new(dev, NULL, data->size, data->align, | |
106 | 0, &grch->data[i].mem); | |
107 | if (ret) | |
108 | return ret; | |
73a60c0d | 109 | |
ac1499d9 BS |
110 | ret = nouveau_gpuobj_map_vm(grch->data[i].mem, chan->vm, |
111 | data->access, | |
112 | &grch->data[i].vma); | |
113 | if (ret) | |
114 | return ret; | |
966a5b7d | 115 | |
ac1499d9 | 116 | data++; |
966a5b7d BS |
117 | } |
118 | ||
ac1499d9 BS |
119 | /* finally, fill in the mmio list and point the context at it */ |
120 | for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { | |
121 | u32 addr = mmio->addr; | |
122 | u32 data = mmio->data; | |
966a5b7d | 123 | |
ac1499d9 BS |
124 | if (mmio->shift) { |
125 | u64 info = grch->data[mmio->buffer].vma.offset; | |
126 | data |= info >> mmio->shift; | |
127 | } | |
73a60c0d | 128 | |
ac1499d9 BS |
129 | nv_wo32(grch->mmio, grch->mmio_nr++ * 4, addr); |
130 | nv_wo32(grch->mmio, grch->mmio_nr++ * 4, data); | |
131 | mmio++; | |
132 | } | |
73a60c0d | 133 | |
ac1499d9 BS |
134 | for (i = 0; i < priv->size; i += 4) |
135 | nv_wo32(grch->grctx, i, priv->data[i / 4]); | |
966a5b7d | 136 | |
73a60c0d BS |
137 | nv_wo32(chan->ramin, 0x0210, lower_32_bits(grch->grctx_vma.offset) | 4); |
138 | nv_wo32(chan->ramin, 0x0214, upper_32_bits(grch->grctx_vma.offset)); | |
3863c9bc | 139 | nvimem_flush(dev); |
966a5b7d | 140 | |
ac1499d9 BS |
141 | if (!priv->firmware) { |
142 | nv_wo32(grctx, 0x00, grch->mmio_nr / 2); | |
73a60c0d | 143 | nv_wo32(grctx, 0x04, grch->mmio_vma.offset >> 8); |
0411de85 BS |
144 | } else { |
145 | nv_wo32(grctx, 0xf4, 0); | |
146 | nv_wo32(grctx, 0xf8, 0); | |
ac1499d9 | 147 | nv_wo32(grctx, 0x10, grch->mmio_nr / 2); |
73a60c0d BS |
148 | nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio_vma.offset)); |
149 | nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio_vma.offset)); | |
0411de85 BS |
150 | nv_wo32(grctx, 0x1c, 1); |
151 | nv_wo32(grctx, 0x20, 0); | |
152 | nv_wo32(grctx, 0x28, 0); | |
153 | nv_wo32(grctx, 0x2c, 0); | |
154 | } | |
3863c9bc | 155 | nvimem_flush(dev); |
4b223eef | 156 | return 0; |
966a5b7d BS |
157 | |
158 | error: | |
7a45cd19 | 159 | priv->base.context_del(chan, engine); |
966a5b7d | 160 | return ret; |
4b223eef BS |
161 | } |
162 | ||
ac1499d9 | 163 | void |
7a45cd19 | 164 | nvc0_graph_context_del(struct nouveau_channel *chan, int engine) |
4b223eef | 165 | { |
7a45cd19 | 166 | struct nvc0_graph_chan *grch = chan->engctx[engine]; |
ac1499d9 BS |
167 | int i; |
168 | ||
169 | for (i = 0; i < ARRAY_SIZE(grch->data); i++) { | |
170 | nouveau_gpuobj_unmap(&grch->data[i].vma); | |
171 | nouveau_gpuobj_ref(NULL, &grch->data[i].mem); | |
172 | } | |
966a5b7d | 173 | |
73a60c0d | 174 | nouveau_gpuobj_unmap(&grch->mmio_vma); |
966a5b7d | 175 | nouveau_gpuobj_ref(NULL, &grch->mmio); |
ac1499d9 BS |
176 | |
177 | nouveau_gpuobj_unmap(&grch->grctx_vma); | |
966a5b7d | 178 | nouveau_gpuobj_ref(NULL, &grch->grctx); |
7a45cd19 | 179 | chan->engctx[engine] = NULL; |
4b223eef BS |
180 | } |
181 | ||
7a45cd19 BS |
182 | static int |
183 | nvc0_graph_object_new(struct nouveau_channel *chan, int engine, | |
184 | u32 handle, u16 class) | |
4b223eef | 185 | { |
966a5b7d BS |
186 | return 0; |
187 | } | |
188 | ||
189 | static int | |
6c320fef | 190 | nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend) |
966a5b7d | 191 | { |
4b223eef BS |
192 | return 0; |
193 | } | |
194 | ||
966a5b7d BS |
195 | static void |
196 | nvc0_graph_init_obj418880(struct drm_device *dev) | |
197 | { | |
7a45cd19 | 198 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d BS |
199 | int i; |
200 | ||
201 | nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000); | |
202 | nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000); | |
203 | for (i = 0; i < 4; i++) | |
204 | nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000); | |
3863c9bc BS |
205 | nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); |
206 | nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); | |
966a5b7d BS |
207 | } |
208 | ||
209 | static void | |
210 | nvc0_graph_init_regs(struct drm_device *dev) | |
211 | { | |
212 | nv_wr32(dev, 0x400080, 0x003083c2); | |
213 | nv_wr32(dev, 0x400088, 0x00006fe7); | |
214 | nv_wr32(dev, 0x40008c, 0x00000000); | |
215 | nv_wr32(dev, 0x400090, 0x00000030); | |
216 | nv_wr32(dev, 0x40013c, 0x013901f7); | |
217 | nv_wr32(dev, 0x400140, 0x00000100); | |
218 | nv_wr32(dev, 0x400144, 0x00000000); | |
219 | nv_wr32(dev, 0x400148, 0x00000110); | |
220 | nv_wr32(dev, 0x400138, 0x00000000); | |
221 | nv_wr32(dev, 0x400130, 0x00000000); | |
222 | nv_wr32(dev, 0x400134, 0x00000000); | |
223 | nv_wr32(dev, 0x400124, 0x00000002); | |
224 | } | |
225 | ||
226 | static void | |
227 | nvc0_graph_init_gpc_0(struct drm_device *dev) | |
228 | { | |
7a45cd19 | 229 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
c4afbe74 BS |
230 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); |
231 | u32 data[TPC_MAX / 8]; | |
aa58c405 BS |
232 | u8 tpnr[GPC_MAX]; |
233 | int i, gpc, tpc; | |
f212949c | 234 | |
c4afbe74 | 235 | nv_wr32(dev, TPC_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */ |
ffe2dee4 | 236 | |
f212949c EV |
237 | /* |
238 | * TP ROP UNKVAL(magic_not_rop_nr) | |
239 | * 450: 4/0/0/0 2 3 | |
240 | * 460: 3/4/0/0 4 1 | |
241 | * 465: 3/4/4/0 4 7 | |
242 | * 470: 3/3/4/4 5 5 | |
243 | * 480: 3/4/4/4 6 6 | |
f212949c EV |
244 | */ |
245 | ||
aa58c405 | 246 | memset(data, 0x00, sizeof(data)); |
c4afbe74 BS |
247 | memcpy(tpnr, priv->tpc_nr, sizeof(priv->tpc_nr)); |
248 | for (i = 0, gpc = -1; i < priv->tpc_total; i++) { | |
aa58c405 BS |
249 | do { |
250 | gpc = (gpc + 1) % priv->gpc_nr; | |
251 | } while (!tpnr[gpc]); | |
c4afbe74 | 252 | tpc = priv->tpc_nr[gpc] - tpnr[gpc]--; |
aa58c405 BS |
253 | |
254 | data[i / 8] |= tpc << ((i % 8) * 4); | |
255 | } | |
256 | ||
257 | nv_wr32(dev, GPC_BCAST(0x0980), data[0]); | |
258 | nv_wr32(dev, GPC_BCAST(0x0984), data[1]); | |
259 | nv_wr32(dev, GPC_BCAST(0x0988), data[2]); | |
260 | nv_wr32(dev, GPC_BCAST(0x098c), data[3]); | |
966a5b7d BS |
261 | |
262 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
263 | nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | | |
c4afbe74 BS |
264 | priv->tpc_nr[gpc]); |
265 | nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); | |
066d65db | 266 | nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918); |
966a5b7d BS |
267 | } |
268 | ||
066d65db | 269 | nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918); |
e425e0b3 | 270 | nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800)); |
966a5b7d BS |
271 | } |
272 | ||
273 | static void | |
274 | nvc0_graph_init_units(struct drm_device *dev) | |
275 | { | |
276 | nv_wr32(dev, 0x409c24, 0x000f0000); | |
277 | nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */ | |
278 | nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */ | |
279 | nv_wr32(dev, 0x408030, 0xc0000000); | |
280 | nv_wr32(dev, 0x40601c, 0xc0000000); | |
281 | nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */ | |
282 | nv_wr32(dev, 0x406018, 0xc0000000); | |
283 | nv_wr32(dev, 0x405840, 0xc0000000); | |
284 | nv_wr32(dev, 0x405844, 0x00ffffff); | |
285 | nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008); | |
286 | nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000); | |
287 | } | |
288 | ||
289 | static void | |
290 | nvc0_graph_init_gpc_1(struct drm_device *dev) | |
291 | { | |
7a45cd19 | 292 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d BS |
293 | int gpc, tp; |
294 | ||
295 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
296 | nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000); | |
297 | nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000); | |
298 | nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000); | |
299 | nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000); | |
c4afbe74 BS |
300 | for (tp = 0; tp < priv->tpc_nr[gpc]; tp++) { |
301 | nv_wr32(dev, TPC_UNIT(gpc, tp, 0x508), 0xffffffff); | |
302 | nv_wr32(dev, TPC_UNIT(gpc, tp, 0x50c), 0xffffffff); | |
303 | nv_wr32(dev, TPC_UNIT(gpc, tp, 0x224), 0xc0000000); | |
304 | nv_wr32(dev, TPC_UNIT(gpc, tp, 0x48c), 0xc0000000); | |
305 | nv_wr32(dev, TPC_UNIT(gpc, tp, 0x084), 0xc0000000); | |
306 | nv_wr32(dev, TPC_UNIT(gpc, tp, 0x644), 0x001ffffe); | |
307 | nv_wr32(dev, TPC_UNIT(gpc, tp, 0x64c), 0x0000000f); | |
966a5b7d BS |
308 | } |
309 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff); | |
310 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff); | |
311 | } | |
312 | } | |
313 | ||
314 | static void | |
315 | nvc0_graph_init_rop(struct drm_device *dev) | |
316 | { | |
7a45cd19 | 317 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d BS |
318 | int rop; |
319 | ||
320 | for (rop = 0; rop < priv->rop_nr; rop++) { | |
321 | nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000); | |
322 | nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000); | |
323 | nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff); | |
324 | nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff); | |
325 | } | |
326 | } | |
327 | ||
fe799114 BS |
328 | static void |
329 | nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base, | |
330 | struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) | |
966a5b7d | 331 | { |
fe799114 | 332 | int i; |
966a5b7d BS |
333 | |
334 | nv_wr32(dev, fuc_base + 0x01c0, 0x01000000); | |
fe799114 BS |
335 | for (i = 0; i < data->size / 4; i++) |
336 | nv_wr32(dev, fuc_base + 0x01c4, data->data[i]); | |
966a5b7d BS |
337 | |
338 | nv_wr32(dev, fuc_base + 0x0180, 0x01000000); | |
fe799114 | 339 | for (i = 0; i < code->size / 4; i++) { |
966a5b7d BS |
340 | if ((i & 0x3f) == 0) |
341 | nv_wr32(dev, fuc_base + 0x0188, i >> 6); | |
fe799114 | 342 | nv_wr32(dev, fuc_base + 0x0184, code->data[i]); |
966a5b7d | 343 | } |
966a5b7d BS |
344 | } |
345 | ||
346 | static int | |
347 | nvc0_graph_init_ctxctl(struct drm_device *dev) | |
348 | { | |
0411de85 | 349 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
7a45cd19 | 350 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d | 351 | u32 r000260; |
0411de85 BS |
352 | int i; |
353 | ||
ac1499d9 BS |
354 | if (priv->firmware) { |
355 | /* load fuc microcode */ | |
0411de85 | 356 | r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); |
ac1499d9 BS |
357 | nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, |
358 | &priv->fuc409d); | |
359 | nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, | |
360 | &priv->fuc41ad); | |
0411de85 BS |
361 | nv_wr32(dev, 0x000260, r000260); |
362 | ||
ac1499d9 BS |
363 | /* start both of them running */ |
364 | nv_wr32(dev, 0x409840, 0xffffffff); | |
365 | nv_wr32(dev, 0x41a10c, 0x00000000); | |
0411de85 | 366 | nv_wr32(dev, 0x40910c, 0x00000000); |
ac1499d9 | 367 | nv_wr32(dev, 0x41a100, 0x00000002); |
0411de85 | 368 | nv_wr32(dev, 0x409100, 0x00000002); |
ac1499d9 BS |
369 | if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001)) |
370 | NV_INFO(dev, "0x409800 wait failed\n"); | |
371 | ||
372 | nv_wr32(dev, 0x409840, 0xffffffff); | |
373 | nv_wr32(dev, 0x409500, 0x7fffffff); | |
374 | nv_wr32(dev, 0x409504, 0x00000021); | |
375 | ||
376 | nv_wr32(dev, 0x409840, 0xffffffff); | |
377 | nv_wr32(dev, 0x409500, 0x00000000); | |
378 | nv_wr32(dev, 0x409504, 0x00000010); | |
379 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
380 | NV_ERROR(dev, "fuc09 req 0x10 timeout\n"); | |
0411de85 BS |
381 | return -EBUSY; |
382 | } | |
ac1499d9 | 383 | priv->size = nv_rd32(dev, 0x409800); |
0411de85 | 384 | |
ac1499d9 BS |
385 | nv_wr32(dev, 0x409840, 0xffffffff); |
386 | nv_wr32(dev, 0x409500, 0x00000000); | |
387 | nv_wr32(dev, 0x409504, 0x00000016); | |
388 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
389 | NV_ERROR(dev, "fuc09 req 0x16 timeout\n"); | |
390 | return -EBUSY; | |
391 | } | |
392 | ||
393 | nv_wr32(dev, 0x409840, 0xffffffff); | |
394 | nv_wr32(dev, 0x409500, 0x00000000); | |
395 | nv_wr32(dev, 0x409504, 0x00000025); | |
396 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
397 | NV_ERROR(dev, "fuc09 req 0x25 timeout\n"); | |
398 | return -EBUSY; | |
399 | } | |
400 | ||
401 | goto done; | |
0411de85 | 402 | } |
966a5b7d | 403 | |
ac1499d9 | 404 | /* load HUB microcode */ |
966a5b7d | 405 | r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); |
ac1499d9 BS |
406 | nv_wr32(dev, 0x4091c0, 0x01000000); |
407 | for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++) | |
408 | nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]); | |
409 | ||
410 | nv_wr32(dev, 0x409180, 0x01000000); | |
411 | for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) { | |
412 | if ((i & 0x3f) == 0) | |
413 | nv_wr32(dev, 0x409188, i >> 6); | |
414 | nv_wr32(dev, 0x409184, nvc0_grhub_code[i]); | |
415 | } | |
416 | ||
417 | /* load GPC microcode */ | |
418 | nv_wr32(dev, 0x41a1c0, 0x01000000); | |
419 | for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++) | |
420 | nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]); | |
421 | ||
422 | nv_wr32(dev, 0x41a180, 0x01000000); | |
423 | for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) { | |
424 | if ((i & 0x3f) == 0) | |
425 | nv_wr32(dev, 0x41a188, i >> 6); | |
426 | nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]); | |
427 | } | |
966a5b7d BS |
428 | nv_wr32(dev, 0x000260, r000260); |
429 | ||
ac1499d9 BS |
430 | /* start HUB ucode running, it'll init the GPCs */ |
431 | nv_wr32(dev, 0x409800, dev_priv->chipset); | |
966a5b7d | 432 | nv_wr32(dev, 0x40910c, 0x00000000); |
966a5b7d | 433 | nv_wr32(dev, 0x409100, 0x00000002); |
ac1499d9 BS |
434 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { |
435 | NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n"); | |
436 | nvc0_graph_ctxctl_debug(dev); | |
966a5b7d BS |
437 | return -EBUSY; |
438 | } | |
966a5b7d | 439 | |
ac1499d9 BS |
440 | priv->size = nv_rd32(dev, 0x409804); |
441 | done: | |
442 | if (priv->data == NULL) { | |
443 | int ret = nvc0_grctx_generate(dev); | |
444 | if (ret) { | |
445 | NV_ERROR(dev, "PGRAPH: failed to construct context\n"); | |
446 | return ret; | |
447 | } | |
966a5b7d | 448 | |
ac1499d9 | 449 | return 1; |
966a5b7d BS |
450 | } |
451 | ||
452 | return 0; | |
4b223eef BS |
453 | } |
454 | ||
7a45cd19 BS |
455 | static int |
456 | nvc0_graph_init(struct drm_device *dev, int engine) | |
4b223eef | 457 | { |
966a5b7d BS |
458 | int ret; |
459 | ||
ac1499d9 | 460 | reset: |
966a5b7d BS |
461 | nv_mask(dev, 0x000200, 0x18001000, 0x00000000); |
462 | nv_mask(dev, 0x000200, 0x18001000, 0x18001000); | |
463 | ||
966a5b7d BS |
464 | nvc0_graph_init_obj418880(dev); |
465 | nvc0_graph_init_regs(dev); | |
f212949c | 466 | /*nvc0_graph_init_unitplemented_magics(dev);*/ |
966a5b7d | 467 | nvc0_graph_init_gpc_0(dev); |
f212949c | 468 | /*nvc0_graph_init_unitplemented_c242(dev);*/ |
966a5b7d BS |
469 | |
470 | nv_wr32(dev, 0x400500, 0x00010001); | |
471 | nv_wr32(dev, 0x400100, 0xffffffff); | |
472 | nv_wr32(dev, 0x40013c, 0xffffffff); | |
473 | ||
474 | nvc0_graph_init_units(dev); | |
475 | nvc0_graph_init_gpc_1(dev); | |
476 | nvc0_graph_init_rop(dev); | |
477 | ||
478 | nv_wr32(dev, 0x400108, 0xffffffff); | |
479 | nv_wr32(dev, 0x400138, 0xffffffff); | |
480 | nv_wr32(dev, 0x400118, 0xffffffff); | |
481 | nv_wr32(dev, 0x400130, 0xffffffff); | |
482 | nv_wr32(dev, 0x40011c, 0xffffffff); | |
483 | nv_wr32(dev, 0x400134, 0xffffffff); | |
484 | nv_wr32(dev, 0x400054, 0x34ce3464); | |
485 | ||
486 | ret = nvc0_graph_init_ctxctl(dev); | |
ac1499d9 BS |
487 | if (ret) { |
488 | if (ret == 1) | |
489 | goto reset; | |
a82dd49f | 490 | return ret; |
ac1499d9 | 491 | } |
a82dd49f | 492 | |
4b223eef BS |
493 | return 0; |
494 | } | |
495 | ||
d5a27370 | 496 | int |
966a5b7d BS |
497 | nvc0_graph_isr_chid(struct drm_device *dev, u64 inst) |
498 | { | |
c420b2dc | 499 | struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO); |
966a5b7d BS |
500 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
501 | struct nouveau_channel *chan; | |
502 | unsigned long flags; | |
503 | int i; | |
504 | ||
505 | spin_lock_irqsave(&dev_priv->channels.lock, flags); | |
c420b2dc | 506 | for (i = 0; i < pfifo->channels; i++) { |
966a5b7d BS |
507 | chan = dev_priv->channels.ptr[i]; |
508 | if (!chan || !chan->ramin) | |
509 | continue; | |
510 | ||
3863c9bc | 511 | if (inst == chan->ramin->addr) |
966a5b7d BS |
512 | break; |
513 | } | |
514 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); | |
515 | return i; | |
516 | } | |
517 | ||
0411de85 BS |
518 | static void |
519 | nvc0_graph_ctxctl_isr(struct drm_device *dev) | |
520 | { | |
521 | u32 ustat = nv_rd32(dev, 0x409c18); | |
522 | ||
523 | if (ustat & 0x00000001) | |
524 | NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n"); | |
525 | if (ustat & 0x00080000) | |
526 | NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n"); | |
527 | if (ustat & ~0x00080001) | |
528 | NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat); | |
529 | ||
530 | nvc0_graph_ctxctl_debug(dev); | |
531 | nv_wr32(dev, 0x409c20, ustat); | |
532 | } | |
533 | ||
966a5b7d BS |
534 | static void |
535 | nvc0_graph_isr(struct drm_device *dev) | |
536 | { | |
537 | u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; | |
538 | u32 chid = nvc0_graph_isr_chid(dev, inst); | |
539 | u32 stat = nv_rd32(dev, 0x400100); | |
540 | u32 addr = nv_rd32(dev, 0x400704); | |
541 | u32 mthd = (addr & 0x00003ffc); | |
542 | u32 subc = (addr & 0x00070000) >> 16; | |
543 | u32 data = nv_rd32(dev, 0x400708); | |
544 | u32 code = nv_rd32(dev, 0x400110); | |
545 | u32 class = nv_rd32(dev, 0x404200 + (subc * 4)); | |
546 | ||
547 | if (stat & 0x00000010) { | |
bd2f2037 BS |
548 | if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) { |
549 | NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] " | |
550 | "subc %d class 0x%04x mthd 0x%04x " | |
551 | "data 0x%08x\n", | |
552 | chid, inst, subc, class, mthd, data); | |
553 | } | |
966a5b7d BS |
554 | nv_wr32(dev, 0x400100, 0x00000010); |
555 | stat &= ~0x00000010; | |
556 | } | |
557 | ||
eae5e7f3 BS |
558 | if (stat & 0x00000020) { |
559 | NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d " | |
560 | "class 0x%04x mthd 0x%04x data 0x%08x\n", | |
561 | chid, inst, subc, class, mthd, data); | |
562 | nv_wr32(dev, 0x400100, 0x00000020); | |
563 | stat &= ~0x00000020; | |
564 | } | |
565 | ||
966a5b7d BS |
566 | if (stat & 0x00100000) { |
567 | NV_INFO(dev, "PGRAPH: DATA_ERROR ["); | |
6effe393 | 568 | nouveau_enum_print(nv50_data_error_names, code); |
966a5b7d BS |
569 | printk("] ch %d [0x%010llx] subc %d class 0x%04x " |
570 | "mthd 0x%04x data 0x%08x\n", | |
571 | chid, inst, subc, class, mthd, data); | |
572 | nv_wr32(dev, 0x400100, 0x00100000); | |
573 | stat &= ~0x00100000; | |
574 | } | |
575 | ||
eae5e7f3 BS |
576 | if (stat & 0x00200000) { |
577 | u32 trap = nv_rd32(dev, 0x400108); | |
578 | NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap); | |
579 | nv_wr32(dev, 0x400108, trap); | |
580 | nv_wr32(dev, 0x400100, 0x00200000); | |
581 | stat &= ~0x00200000; | |
582 | } | |
583 | ||
966a5b7d | 584 | if (stat & 0x00080000) { |
0411de85 | 585 | nvc0_graph_ctxctl_isr(dev); |
966a5b7d BS |
586 | nv_wr32(dev, 0x400100, 0x00080000); |
587 | stat &= ~0x00080000; | |
588 | } | |
589 | ||
590 | if (stat) { | |
591 | NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat); | |
592 | nv_wr32(dev, 0x400100, stat); | |
593 | } | |
594 | ||
595 | nv_wr32(dev, 0x400500, 0x00010001); | |
596 | } | |
51f73d64 | 597 | |
fe799114 BS |
598 | static int |
599 | nvc0_graph_create_fw(struct drm_device *dev, const char *fwname, | |
600 | struct nvc0_graph_fuc *fuc) | |
601 | { | |
602 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
603 | const struct firmware *fw; | |
604 | char f[32]; | |
605 | int ret; | |
606 | ||
607 | snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname); | |
608 | ret = request_firmware(&fw, f, &dev->pdev->dev); | |
609 | if (ret) { | |
610 | snprintf(f, sizeof(f), "nouveau/%s", fwname); | |
611 | ret = request_firmware(&fw, f, &dev->pdev->dev); | |
612 | if (ret) { | |
613 | NV_ERROR(dev, "failed to load %s\n", fwname); | |
614 | return ret; | |
615 | } | |
616 | } | |
617 | ||
618 | fuc->size = fw->size; | |
619 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); | |
620 | release_firmware(fw); | |
621 | return (fuc->data != NULL) ? 0 : -ENOMEM; | |
622 | } | |
623 | ||
624 | static void | |
625 | nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc) | |
626 | { | |
627 | if (fuc->data) { | |
628 | kfree(fuc->data); | |
629 | fuc->data = NULL; | |
630 | } | |
631 | } | |
632 | ||
7a45cd19 BS |
633 | static void |
634 | nvc0_graph_destroy(struct drm_device *dev, int engine) | |
635 | { | |
636 | struct nvc0_graph_priv *priv = nv_engine(dev, engine); | |
637 | ||
ac1499d9 BS |
638 | nvc0_graph_destroy_fw(&priv->fuc409c); |
639 | nvc0_graph_destroy_fw(&priv->fuc409d); | |
640 | nvc0_graph_destroy_fw(&priv->fuc41ac); | |
641 | nvc0_graph_destroy_fw(&priv->fuc41ad); | |
fe799114 | 642 | |
7a45cd19 | 643 | nouveau_irq_unregister(dev, 12); |
7a45cd19 BS |
644 | |
645 | nouveau_gpuobj_ref(NULL, &priv->unk4188b8); | |
646 | nouveau_gpuobj_ref(NULL, &priv->unk4188b4); | |
647 | ||
ac1499d9 BS |
648 | if (priv->data) |
649 | kfree(priv->data); | |
7a45cd19 BS |
650 | |
651 | NVOBJ_ENGINE_DEL(dev, GR); | |
652 | kfree(priv); | |
653 | } | |
654 | ||
655 | int | |
656 | nvc0_graph_create(struct drm_device *dev) | |
657 | { | |
658 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
659 | struct nvc0_graph_priv *priv; | |
660 | int ret, gpc, i; | |
847adea2 | 661 | u32 fermi; |
7a45cd19 | 662 | |
847adea2 BS |
663 | fermi = nvc0_graph_class(dev); |
664 | if (!fermi) { | |
a82dd49f BS |
665 | NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n"); |
666 | return 0; | |
667 | } | |
668 | ||
7a45cd19 BS |
669 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
670 | if (!priv) | |
671 | return -ENOMEM; | |
672 | ||
673 | priv->base.destroy = nvc0_graph_destroy; | |
674 | priv->base.init = nvc0_graph_init; | |
675 | priv->base.fini = nvc0_graph_fini; | |
676 | priv->base.context_new = nvc0_graph_context_new; | |
677 | priv->base.context_del = nvc0_graph_context_del; | |
678 | priv->base.object_new = nvc0_graph_object_new; | |
679 | ||
680 | NVOBJ_ENGINE_ADD(dev, GR, &priv->base); | |
681 | nouveau_irq_register(dev, 12, nvc0_graph_isr); | |
7a45cd19 | 682 | |
0411de85 BS |
683 | if (nouveau_ctxfw) { |
684 | NV_INFO(dev, "PGRAPH: using external firmware\n"); | |
685 | if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) || | |
686 | nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) || | |
687 | nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) || | |
688 | nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) { | |
689 | ret = 0; | |
690 | goto error; | |
691 | } | |
ac1499d9 | 692 | priv->firmware = true; |
fe799114 BS |
693 | } |
694 | ||
7a45cd19 BS |
695 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4); |
696 | if (ret) | |
697 | goto error; | |
698 | ||
699 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8); | |
700 | if (ret) | |
701 | goto error; | |
702 | ||
703 | for (i = 0; i < 0x1000; i += 4) { | |
704 | nv_wo32(priv->unk4188b4, i, 0x00000010); | |
705 | nv_wo32(priv->unk4188b8, i, 0x00000010); | |
706 | } | |
707 | ||
708 | priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f; | |
709 | priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16; | |
710 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
c4afbe74 BS |
711 | priv->tpc_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608)); |
712 | priv->tpc_total += priv->tpc_nr[gpc]; | |
7a45cd19 BS |
713 | } |
714 | ||
715 | /*XXX: these need figuring out... */ | |
716 | switch (dev_priv->chipset) { | |
717 | case 0xc0: | |
c4afbe74 | 718 | if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ |
7a45cd19 | 719 | priv->magic_not_rop_nr = 0x07; |
7a45cd19 | 720 | } else |
c4afbe74 | 721 | if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ |
7a45cd19 | 722 | priv->magic_not_rop_nr = 0x05; |
7a45cd19 | 723 | } else |
c4afbe74 | 724 | if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ |
7a45cd19 | 725 | priv->magic_not_rop_nr = 0x06; |
7a45cd19 BS |
726 | } |
727 | break; | |
728 | case 0xc3: /* 450, 4/0/0/0, 2 */ | |
729 | priv->magic_not_rop_nr = 0x03; | |
7a45cd19 BS |
730 | break; |
731 | case 0xc4: /* 460, 3/4/0/0, 4 */ | |
732 | priv->magic_not_rop_nr = 0x01; | |
7a45cd19 | 733 | break; |
a219997a BS |
734 | case 0xc1: /* 2/0/0/0, 1 */ |
735 | priv->magic_not_rop_nr = 0x01; | |
a219997a BS |
736 | break; |
737 | case 0xc8: /* 4/4/3/4, 5 */ | |
738 | priv->magic_not_rop_nr = 0x06; | |
a219997a BS |
739 | break; |
740 | case 0xce: /* 4/4/0/0, 4 */ | |
741 | priv->magic_not_rop_nr = 0x03; | |
a219997a | 742 | break; |
3c23a7b8 BS |
743 | case 0xcf: /* 4/0/0/0, 3 */ |
744 | priv->magic_not_rop_nr = 0x03; | |
745 | break; | |
06784090 BS |
746 | case 0xd9: /* 1/0/0/0, 1 */ |
747 | priv->magic_not_rop_nr = 0x01; | |
748 | break; | |
7a45cd19 BS |
749 | } |
750 | ||
751 | if (!priv->magic_not_rop_nr) { | |
752 | NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n", | |
c4afbe74 BS |
753 | priv->tpc_nr[0], priv->tpc_nr[1], priv->tpc_nr[2], |
754 | priv->tpc_nr[3], priv->rop_nr); | |
06784090 | 755 | priv->magic_not_rop_nr = 0x00; |
7a45cd19 BS |
756 | } |
757 | ||
758 | NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ | |
759 | NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ | |
7a45cd19 | 760 | NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ |
847adea2 BS |
761 | if (fermi >= 0x9197) |
762 | NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */ | |
763 | if (fermi >= 0x9297) | |
764 | NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */ | |
7a45cd19 BS |
765 | NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */ |
766 | return 0; | |
767 | ||
768 | error: | |
769 | nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR); | |
770 | return ret; | |
771 | } |