Commit | Line | Data |
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4b223eef BS |
1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
966a5b7d | 25 | #include <linux/firmware.h> |
e0cd3608 | 26 | #include <linux/module.h> |
966a5b7d | 27 | |
4b223eef BS |
28 | #include "drmP.h" |
29 | ||
30 | #include "nouveau_drv.h" | |
02a841d4 BS |
31 | #include <core/mm.h> |
32 | #include <engine/fifo.h> | |
0411de85 | 33 | |
02a841d4 BS |
34 | #include "nvc0.h" |
35 | #include "fuc/hubnvc0.fuc.h" | |
36 | #include "fuc/gpcnvc0.fuc.h" | |
0411de85 BS |
37 | |
38 | static void | |
39 | nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base) | |
40 | { | |
41 | NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base, | |
42 | nv_rd32(dev, base + 0x400)); | |
43 | NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, | |
44 | nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804), | |
45 | nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c)); | |
46 | NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, | |
47 | nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814), | |
48 | nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c)); | |
49 | } | |
50 | ||
51 | static void | |
52 | nvc0_graph_ctxctl_debug(struct drm_device *dev) | |
53 | { | |
54 | u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff; | |
55 | u32 gpc; | |
56 | ||
57 | nvc0_graph_ctxctl_debug_unit(dev, 0x409000); | |
58 | for (gpc = 0; gpc < gpcnr; gpc++) | |
59 | nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000)); | |
60 | } | |
966a5b7d | 61 | |
7a45cd19 BS |
62 | static int |
63 | nvc0_graph_load_context(struct nouveau_channel *chan) | |
64 | { | |
65 | struct drm_device *dev = chan->dev; | |
66 | ||
67 | nv_wr32(dev, 0x409840, 0x00000030); | |
68 | nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); | |
69 | nv_wr32(dev, 0x409504, 0x00000003); | |
70 | if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010)) | |
71 | NV_ERROR(dev, "PGRAPH: load_ctx timeout\n"); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | static int | |
77 | nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan) | |
78 | { | |
79 | nv_wr32(dev, 0x409840, 0x00000003); | |
80 | nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12); | |
81 | nv_wr32(dev, 0x409504, 0x00000009); | |
82 | if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) { | |
83 | NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n"); | |
84 | return -EBUSY; | |
85 | } | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
966a5b7d BS |
90 | static int |
91 | nvc0_graph_construct_context(struct nouveau_channel *chan) | |
92 | { | |
93 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
7a45cd19 BS |
94 | struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR); |
95 | struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR]; | |
966a5b7d BS |
96 | struct drm_device *dev = chan->dev; |
97 | int ret, i; | |
98 | u32 *ctx; | |
99 | ||
100 | ctx = kmalloc(priv->grctx_size, GFP_KERNEL); | |
101 | if (!ctx) | |
102 | return -ENOMEM; | |
103 | ||
0411de85 BS |
104 | if (!nouveau_ctxfw) { |
105 | nv_wr32(dev, 0x409840, 0x80000000); | |
106 | nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); | |
107 | nv_wr32(dev, 0x409504, 0x00000001); | |
108 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { | |
109 | NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n"); | |
110 | nvc0_graph_ctxctl_debug(dev); | |
60f7ab06 DC |
111 | ret = -EBUSY; |
112 | goto err; | |
0411de85 BS |
113 | } |
114 | } else { | |
115 | nvc0_graph_load_context(chan); | |
116 | ||
117 | nv_wo32(grch->grctx, 0x1c, 1); | |
118 | nv_wo32(grch->grctx, 0x20, 0); | |
119 | nv_wo32(grch->grctx, 0x28, 0); | |
120 | nv_wo32(grch->grctx, 0x2c, 0); | |
121 | dev_priv->engine.instmem.flush(dev); | |
122 | } | |
966a5b7d BS |
123 | |
124 | ret = nvc0_grctx_generate(chan); | |
60f7ab06 DC |
125 | if (ret) |
126 | goto err; | |
966a5b7d | 127 | |
0411de85 BS |
128 | if (!nouveau_ctxfw) { |
129 | nv_wr32(dev, 0x409840, 0x80000000); | |
130 | nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); | |
131 | nv_wr32(dev, 0x409504, 0x00000002); | |
132 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { | |
133 | NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n"); | |
134 | nvc0_graph_ctxctl_debug(dev); | |
60f7ab06 DC |
135 | ret = -EBUSY; |
136 | goto err; | |
0411de85 BS |
137 | } |
138 | } else { | |
139 | ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst); | |
60f7ab06 DC |
140 | if (ret) |
141 | goto err; | |
966a5b7d BS |
142 | } |
143 | ||
144 | for (i = 0; i < priv->grctx_size; i += 4) | |
145 | ctx[i / 4] = nv_ro32(grch->grctx, i); | |
146 | ||
147 | priv->grctx_vals = ctx; | |
148 | return 0; | |
60f7ab06 DC |
149 | |
150 | err: | |
151 | kfree(ctx); | |
152 | return ret; | |
966a5b7d BS |
153 | } |
154 | ||
155 | static int | |
156 | nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan) | |
157 | { | |
7a45cd19 BS |
158 | struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR); |
159 | struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR]; | |
966a5b7d | 160 | struct drm_device *dev = chan->dev; |
6688a4dd | 161 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
966a5b7d | 162 | int i = 0, gpc, tp, ret; |
966a5b7d | 163 | |
73a60c0d | 164 | ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, 0, &grch->unk408004); |
966a5b7d BS |
165 | if (ret) |
166 | return ret; | |
167 | ||
73a60c0d BS |
168 | ret = nouveau_gpuobj_map_vm(grch->unk408004, NV_MEM_ACCESS_RW | |
169 | NV_MEM_ACCESS_SYS, chan->vm, | |
170 | &grch->unk408004_vma); | |
966a5b7d BS |
171 | if (ret) |
172 | return ret; | |
173 | ||
73a60c0d BS |
174 | ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, 0, &grch->unk40800c); |
175 | if (ret) | |
176 | return ret; | |
177 | ||
178 | ret = nouveau_gpuobj_map_vm(grch->unk40800c, NV_MEM_ACCESS_RW | | |
179 | NV_MEM_ACCESS_SYS, chan->vm, | |
180 | &grch->unk40800c_vma); | |
181 | if (ret) | |
182 | return ret; | |
183 | ||
184 | ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096, 0, | |
966a5b7d BS |
185 | &grch->unk418810); |
186 | if (ret) | |
187 | return ret; | |
188 | ||
73a60c0d BS |
189 | ret = nouveau_gpuobj_map_vm(grch->unk418810, NV_MEM_ACCESS_RW, |
190 | chan->vm, &grch->unk418810_vma); | |
966a5b7d BS |
191 | if (ret) |
192 | return ret; | |
193 | ||
73a60c0d BS |
194 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, 0, &grch->mmio); |
195 | if (ret) | |
196 | return ret; | |
197 | ||
198 | ret = nouveau_gpuobj_map_vm(grch->mmio, NV_MEM_ACCESS_RW | | |
199 | NV_MEM_ACCESS_SYS, chan->vm, | |
200 | &grch->mmio_vma); | |
201 | if (ret) | |
202 | return ret; | |
966a5b7d BS |
203 | |
204 | nv_wo32(grch->mmio, i++ * 4, 0x00408004); | |
73a60c0d | 205 | nv_wo32(grch->mmio, i++ * 4, grch->unk408004_vma.offset >> 8); |
966a5b7d BS |
206 | nv_wo32(grch->mmio, i++ * 4, 0x00408008); |
207 | nv_wo32(grch->mmio, i++ * 4, 0x80000018); | |
208 | ||
209 | nv_wo32(grch->mmio, i++ * 4, 0x0040800c); | |
73a60c0d | 210 | nv_wo32(grch->mmio, i++ * 4, grch->unk40800c_vma.offset >> 8); |
966a5b7d BS |
211 | nv_wo32(grch->mmio, i++ * 4, 0x00408010); |
212 | nv_wo32(grch->mmio, i++ * 4, 0x80000000); | |
213 | ||
214 | nv_wo32(grch->mmio, i++ * 4, 0x00418810); | |
73a60c0d | 215 | nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810_vma.offset >> 12); |
966a5b7d | 216 | nv_wo32(grch->mmio, i++ * 4, 0x00419848); |
73a60c0d | 217 | nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810_vma.offset >> 12); |
966a5b7d BS |
218 | |
219 | nv_wo32(grch->mmio, i++ * 4, 0x00419004); | |
73a60c0d | 220 | nv_wo32(grch->mmio, i++ * 4, grch->unk40800c_vma.offset >> 8); |
966a5b7d BS |
221 | nv_wo32(grch->mmio, i++ * 4, 0x00419008); |
222 | nv_wo32(grch->mmio, i++ * 4, 0x00000000); | |
223 | ||
224 | nv_wo32(grch->mmio, i++ * 4, 0x00418808); | |
73a60c0d | 225 | nv_wo32(grch->mmio, i++ * 4, grch->unk408004_vma.offset >> 8); |
966a5b7d BS |
226 | nv_wo32(grch->mmio, i++ * 4, 0x0041880c); |
227 | nv_wo32(grch->mmio, i++ * 4, 0x80000018); | |
228 | ||
6688a4dd BS |
229 | if (dev_priv->chipset != 0xc1) { |
230 | u32 magic = 0x02180000; | |
231 | nv_wo32(grch->mmio, i++ * 4, 0x00405830); | |
232 | nv_wo32(grch->mmio, i++ * 4, magic); | |
233 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
234 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
235 | u32 reg = TP_UNIT(gpc, tp, 0x520); | |
236 | nv_wo32(grch->mmio, i++ * 4, reg); | |
237 | nv_wo32(grch->mmio, i++ * 4, magic); | |
238 | magic += 0x0324; | |
239 | } | |
240 | } | |
241 | } else { | |
242 | u32 magic = 0x02180000; | |
243 | nv_wo32(grch->mmio, i++ * 4, 0x00405830); | |
244 | nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218); | |
245 | nv_wo32(grch->mmio, i++ * 4, 0x004064c4); | |
246 | nv_wo32(grch->mmio, i++ * 4, 0x0086ffff); | |
247 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
248 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
249 | u32 reg = TP_UNIT(gpc, tp, 0x520); | |
250 | nv_wo32(grch->mmio, i++ * 4, reg); | |
251 | nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic); | |
252 | magic += 0x0324; | |
253 | } | |
254 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
255 | u32 reg = TP_UNIT(gpc, tp, 0x544); | |
256 | nv_wo32(grch->mmio, i++ * 4, reg); | |
257 | nv_wo32(grch->mmio, i++ * 4, magic); | |
258 | magic += 0x0324; | |
259 | } | |
966a5b7d BS |
260 | } |
261 | } | |
262 | ||
263 | grch->mmio_nr = i / 2; | |
264 | return 0; | |
265 | } | |
266 | ||
7a45cd19 BS |
267 | static int |
268 | nvc0_graph_context_new(struct nouveau_channel *chan, int engine) | |
4b223eef | 269 | { |
7a45cd19 BS |
270 | struct drm_device *dev = chan->dev; |
271 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
966a5b7d | 272 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; |
7a45cd19 | 273 | struct nvc0_graph_priv *priv = nv_engine(dev, engine); |
966a5b7d | 274 | struct nvc0_graph_chan *grch; |
966a5b7d BS |
275 | struct nouveau_gpuobj *grctx; |
276 | int ret, i; | |
277 | ||
7a45cd19 BS |
278 | grch = kzalloc(sizeof(*grch), GFP_KERNEL); |
279 | if (!grch) | |
966a5b7d | 280 | return -ENOMEM; |
7a45cd19 | 281 | chan->engctx[NVOBJ_ENGINE_GR] = grch; |
966a5b7d | 282 | |
73a60c0d | 283 | ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256, 0, |
966a5b7d BS |
284 | &grch->grctx); |
285 | if (ret) | |
286 | goto error; | |
73a60c0d BS |
287 | |
288 | ret = nouveau_gpuobj_map_vm(grch->grctx, NV_MEM_ACCESS_RW | | |
289 | NV_MEM_ACCESS_SYS, chan->vm, | |
290 | &grch->grctx_vma); | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
966a5b7d BS |
294 | grctx = grch->grctx; |
295 | ||
296 | ret = nvc0_graph_create_context_mmio_list(chan); | |
297 | if (ret) | |
298 | goto error; | |
299 | ||
73a60c0d BS |
300 | nv_wo32(chan->ramin, 0x0210, lower_32_bits(grch->grctx_vma.offset) | 4); |
301 | nv_wo32(chan->ramin, 0x0214, upper_32_bits(grch->grctx_vma.offset)); | |
966a5b7d BS |
302 | pinstmem->flush(dev); |
303 | ||
304 | if (!priv->grctx_vals) { | |
305 | ret = nvc0_graph_construct_context(chan); | |
306 | if (ret) | |
307 | goto error; | |
308 | } | |
309 | ||
310 | for (i = 0; i < priv->grctx_size; i += 4) | |
311 | nv_wo32(grctx, i, priv->grctx_vals[i / 4]); | |
312 | ||
0411de85 BS |
313 | if (!nouveau_ctxfw) { |
314 | nv_wo32(grctx, 0x00, grch->mmio_nr); | |
73a60c0d | 315 | nv_wo32(grctx, 0x04, grch->mmio_vma.offset >> 8); |
0411de85 BS |
316 | } else { |
317 | nv_wo32(grctx, 0xf4, 0); | |
318 | nv_wo32(grctx, 0xf8, 0); | |
319 | nv_wo32(grctx, 0x10, grch->mmio_nr); | |
73a60c0d BS |
320 | nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio_vma.offset)); |
321 | nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio_vma.offset)); | |
0411de85 BS |
322 | nv_wo32(grctx, 0x1c, 1); |
323 | nv_wo32(grctx, 0x20, 0); | |
324 | nv_wo32(grctx, 0x28, 0); | |
325 | nv_wo32(grctx, 0x2c, 0); | |
326 | } | |
966a5b7d | 327 | pinstmem->flush(dev); |
4b223eef | 328 | return 0; |
966a5b7d BS |
329 | |
330 | error: | |
7a45cd19 | 331 | priv->base.context_del(chan, engine); |
966a5b7d | 332 | return ret; |
4b223eef BS |
333 | } |
334 | ||
7a45cd19 BS |
335 | static void |
336 | nvc0_graph_context_del(struct nouveau_channel *chan, int engine) | |
4b223eef | 337 | { |
7a45cd19 | 338 | struct nvc0_graph_chan *grch = chan->engctx[engine]; |
966a5b7d | 339 | |
73a60c0d BS |
340 | nouveau_gpuobj_unmap(&grch->mmio_vma); |
341 | nouveau_gpuobj_unmap(&grch->unk418810_vma); | |
342 | nouveau_gpuobj_unmap(&grch->unk40800c_vma); | |
343 | nouveau_gpuobj_unmap(&grch->unk408004_vma); | |
344 | nouveau_gpuobj_unmap(&grch->grctx_vma); | |
966a5b7d BS |
345 | nouveau_gpuobj_ref(NULL, &grch->mmio); |
346 | nouveau_gpuobj_ref(NULL, &grch->unk418810); | |
347 | nouveau_gpuobj_ref(NULL, &grch->unk40800c); | |
348 | nouveau_gpuobj_ref(NULL, &grch->unk408004); | |
349 | nouveau_gpuobj_ref(NULL, &grch->grctx); | |
7a45cd19 | 350 | chan->engctx[engine] = NULL; |
4b223eef BS |
351 | } |
352 | ||
7a45cd19 BS |
353 | static int |
354 | nvc0_graph_object_new(struct nouveau_channel *chan, int engine, | |
355 | u32 handle, u16 class) | |
4b223eef | 356 | { |
966a5b7d BS |
357 | return 0; |
358 | } | |
359 | ||
360 | static int | |
6c320fef | 361 | nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend) |
966a5b7d | 362 | { |
4b223eef BS |
363 | return 0; |
364 | } | |
365 | ||
966a5b7d BS |
366 | static void |
367 | nvc0_graph_init_obj418880(struct drm_device *dev) | |
368 | { | |
7a45cd19 | 369 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d BS |
370 | int i; |
371 | ||
372 | nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000); | |
373 | nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000); | |
374 | for (i = 0; i < 4; i++) | |
375 | nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000); | |
376 | nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8); | |
377 | nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8); | |
378 | } | |
379 | ||
380 | static void | |
381 | nvc0_graph_init_regs(struct drm_device *dev) | |
382 | { | |
383 | nv_wr32(dev, 0x400080, 0x003083c2); | |
384 | nv_wr32(dev, 0x400088, 0x00006fe7); | |
385 | nv_wr32(dev, 0x40008c, 0x00000000); | |
386 | nv_wr32(dev, 0x400090, 0x00000030); | |
387 | nv_wr32(dev, 0x40013c, 0x013901f7); | |
388 | nv_wr32(dev, 0x400140, 0x00000100); | |
389 | nv_wr32(dev, 0x400144, 0x00000000); | |
390 | nv_wr32(dev, 0x400148, 0x00000110); | |
391 | nv_wr32(dev, 0x400138, 0x00000000); | |
392 | nv_wr32(dev, 0x400130, 0x00000000); | |
393 | nv_wr32(dev, 0x400134, 0x00000000); | |
394 | nv_wr32(dev, 0x400124, 0x00000002); | |
395 | } | |
396 | ||
397 | static void | |
398 | nvc0_graph_init_gpc_0(struct drm_device *dev) | |
399 | { | |
7a45cd19 | 400 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
066d65db | 401 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tp_total); |
aa58c405 BS |
402 | u32 data[TP_MAX / 8]; |
403 | u8 tpnr[GPC_MAX]; | |
404 | int i, gpc, tpc; | |
f212949c | 405 | |
ffe2dee4 CB |
406 | nv_wr32(dev, TP_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */ |
407 | ||
f212949c EV |
408 | /* |
409 | * TP ROP UNKVAL(magic_not_rop_nr) | |
410 | * 450: 4/0/0/0 2 3 | |
411 | * 460: 3/4/0/0 4 1 | |
412 | * 465: 3/4/4/0 4 7 | |
413 | * 470: 3/3/4/4 5 5 | |
414 | * 480: 3/4/4/4 6 6 | |
f212949c EV |
415 | */ |
416 | ||
aa58c405 BS |
417 | memset(data, 0x00, sizeof(data)); |
418 | memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr)); | |
419 | for (i = 0, gpc = -1; i < priv->tp_total; i++) { | |
420 | do { | |
421 | gpc = (gpc + 1) % priv->gpc_nr; | |
422 | } while (!tpnr[gpc]); | |
423 | tpc = priv->tp_nr[gpc] - tpnr[gpc]--; | |
424 | ||
425 | data[i / 8] |= tpc << ((i % 8) * 4); | |
426 | } | |
427 | ||
428 | nv_wr32(dev, GPC_BCAST(0x0980), data[0]); | |
429 | nv_wr32(dev, GPC_BCAST(0x0984), data[1]); | |
430 | nv_wr32(dev, GPC_BCAST(0x0988), data[2]); | |
431 | nv_wr32(dev, GPC_BCAST(0x098c), data[3]); | |
966a5b7d BS |
432 | |
433 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
434 | nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | | |
435 | priv->tp_nr[gpc]); | |
436 | nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total); | |
066d65db | 437 | nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918); |
966a5b7d BS |
438 | } |
439 | ||
066d65db | 440 | nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918); |
e425e0b3 | 441 | nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800)); |
966a5b7d BS |
442 | } |
443 | ||
444 | static void | |
445 | nvc0_graph_init_units(struct drm_device *dev) | |
446 | { | |
447 | nv_wr32(dev, 0x409c24, 0x000f0000); | |
448 | nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */ | |
449 | nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */ | |
450 | nv_wr32(dev, 0x408030, 0xc0000000); | |
451 | nv_wr32(dev, 0x40601c, 0xc0000000); | |
452 | nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */ | |
453 | nv_wr32(dev, 0x406018, 0xc0000000); | |
454 | nv_wr32(dev, 0x405840, 0xc0000000); | |
455 | nv_wr32(dev, 0x405844, 0x00ffffff); | |
456 | nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008); | |
457 | nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000); | |
458 | } | |
459 | ||
460 | static void | |
461 | nvc0_graph_init_gpc_1(struct drm_device *dev) | |
462 | { | |
7a45cd19 | 463 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d BS |
464 | int gpc, tp; |
465 | ||
466 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
467 | nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000); | |
468 | nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000); | |
469 | nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000); | |
470 | nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000); | |
471 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
472 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff); | |
473 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff); | |
474 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000); | |
475 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000); | |
476 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000); | |
0f1cb203 BS |
477 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe); |
478 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f); | |
966a5b7d BS |
479 | } |
480 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff); | |
481 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff); | |
482 | } | |
483 | } | |
484 | ||
485 | static void | |
486 | nvc0_graph_init_rop(struct drm_device *dev) | |
487 | { | |
7a45cd19 | 488 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d BS |
489 | int rop; |
490 | ||
491 | for (rop = 0; rop < priv->rop_nr; rop++) { | |
492 | nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000); | |
493 | nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000); | |
494 | nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff); | |
495 | nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff); | |
496 | } | |
497 | } | |
498 | ||
fe799114 BS |
499 | static void |
500 | nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base, | |
501 | struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) | |
966a5b7d | 502 | { |
fe799114 | 503 | int i; |
966a5b7d BS |
504 | |
505 | nv_wr32(dev, fuc_base + 0x01c0, 0x01000000); | |
fe799114 BS |
506 | for (i = 0; i < data->size / 4; i++) |
507 | nv_wr32(dev, fuc_base + 0x01c4, data->data[i]); | |
966a5b7d BS |
508 | |
509 | nv_wr32(dev, fuc_base + 0x0180, 0x01000000); | |
fe799114 | 510 | for (i = 0; i < code->size / 4; i++) { |
966a5b7d BS |
511 | if ((i & 0x3f) == 0) |
512 | nv_wr32(dev, fuc_base + 0x0188, i >> 6); | |
fe799114 | 513 | nv_wr32(dev, fuc_base + 0x0184, code->data[i]); |
966a5b7d | 514 | } |
966a5b7d BS |
515 | } |
516 | ||
517 | static int | |
518 | nvc0_graph_init_ctxctl(struct drm_device *dev) | |
519 | { | |
0411de85 | 520 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
7a45cd19 | 521 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
966a5b7d | 522 | u32 r000260; |
0411de85 BS |
523 | int i; |
524 | ||
525 | if (!nouveau_ctxfw) { | |
526 | /* load HUB microcode */ | |
527 | r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); | |
528 | nv_wr32(dev, 0x4091c0, 0x01000000); | |
529 | for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++) | |
530 | nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]); | |
531 | ||
532 | nv_wr32(dev, 0x409180, 0x01000000); | |
533 | for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) { | |
534 | if ((i & 0x3f) == 0) | |
535 | nv_wr32(dev, 0x409188, i >> 6); | |
536 | nv_wr32(dev, 0x409184, nvc0_grhub_code[i]); | |
537 | } | |
538 | ||
539 | /* load GPC microcode */ | |
540 | nv_wr32(dev, 0x41a1c0, 0x01000000); | |
541 | for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++) | |
542 | nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]); | |
543 | ||
544 | nv_wr32(dev, 0x41a180, 0x01000000); | |
545 | for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) { | |
546 | if ((i & 0x3f) == 0) | |
547 | nv_wr32(dev, 0x41a188, i >> 6); | |
548 | nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]); | |
549 | } | |
550 | nv_wr32(dev, 0x000260, r000260); | |
551 | ||
552 | /* start HUB ucode running, it'll init the GPCs */ | |
553 | nv_wr32(dev, 0x409800, dev_priv->chipset); | |
554 | nv_wr32(dev, 0x40910c, 0x00000000); | |
555 | nv_wr32(dev, 0x409100, 0x00000002); | |
556 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { | |
557 | NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n"); | |
558 | nvc0_graph_ctxctl_debug(dev); | |
559 | return -EBUSY; | |
560 | } | |
561 | ||
562 | priv->grctx_size = nv_rd32(dev, 0x409804); | |
563 | return 0; | |
564 | } | |
966a5b7d BS |
565 | |
566 | /* load fuc microcode */ | |
567 | r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); | |
fe799114 BS |
568 | nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d); |
569 | nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad); | |
966a5b7d BS |
570 | nv_wr32(dev, 0x000260, r000260); |
571 | ||
966a5b7d BS |
572 | /* start both of them running */ |
573 | nv_wr32(dev, 0x409840, 0xffffffff); | |
574 | nv_wr32(dev, 0x41a10c, 0x00000000); | |
575 | nv_wr32(dev, 0x40910c, 0x00000000); | |
576 | nv_wr32(dev, 0x41a100, 0x00000002); | |
577 | nv_wr32(dev, 0x409100, 0x00000002); | |
578 | if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001)) | |
579 | NV_INFO(dev, "0x409800 wait failed\n"); | |
580 | ||
581 | nv_wr32(dev, 0x409840, 0xffffffff); | |
582 | nv_wr32(dev, 0x409500, 0x7fffffff); | |
583 | nv_wr32(dev, 0x409504, 0x00000021); | |
584 | ||
585 | nv_wr32(dev, 0x409840, 0xffffffff); | |
586 | nv_wr32(dev, 0x409500, 0x00000000); | |
587 | nv_wr32(dev, 0x409504, 0x00000010); | |
588 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
589 | NV_ERROR(dev, "fuc09 req 0x10 timeout\n"); | |
590 | return -EBUSY; | |
591 | } | |
592 | priv->grctx_size = nv_rd32(dev, 0x409800); | |
593 | ||
594 | nv_wr32(dev, 0x409840, 0xffffffff); | |
595 | nv_wr32(dev, 0x409500, 0x00000000); | |
596 | nv_wr32(dev, 0x409504, 0x00000016); | |
597 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
598 | NV_ERROR(dev, "fuc09 req 0x16 timeout\n"); | |
599 | return -EBUSY; | |
600 | } | |
601 | ||
602 | nv_wr32(dev, 0x409840, 0xffffffff); | |
603 | nv_wr32(dev, 0x409500, 0x00000000); | |
604 | nv_wr32(dev, 0x409504, 0x00000025); | |
605 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
606 | NV_ERROR(dev, "fuc09 req 0x25 timeout\n"); | |
607 | return -EBUSY; | |
608 | } | |
609 | ||
610 | return 0; | |
4b223eef BS |
611 | } |
612 | ||
7a45cd19 BS |
613 | static int |
614 | nvc0_graph_init(struct drm_device *dev, int engine) | |
4b223eef | 615 | { |
966a5b7d BS |
616 | int ret; |
617 | ||
966a5b7d BS |
618 | nv_mask(dev, 0x000200, 0x18001000, 0x00000000); |
619 | nv_mask(dev, 0x000200, 0x18001000, 0x18001000); | |
620 | ||
966a5b7d BS |
621 | nvc0_graph_init_obj418880(dev); |
622 | nvc0_graph_init_regs(dev); | |
f212949c | 623 | /*nvc0_graph_init_unitplemented_magics(dev);*/ |
966a5b7d | 624 | nvc0_graph_init_gpc_0(dev); |
f212949c | 625 | /*nvc0_graph_init_unitplemented_c242(dev);*/ |
966a5b7d BS |
626 | |
627 | nv_wr32(dev, 0x400500, 0x00010001); | |
628 | nv_wr32(dev, 0x400100, 0xffffffff); | |
629 | nv_wr32(dev, 0x40013c, 0xffffffff); | |
630 | ||
631 | nvc0_graph_init_units(dev); | |
632 | nvc0_graph_init_gpc_1(dev); | |
633 | nvc0_graph_init_rop(dev); | |
634 | ||
635 | nv_wr32(dev, 0x400108, 0xffffffff); | |
636 | nv_wr32(dev, 0x400138, 0xffffffff); | |
637 | nv_wr32(dev, 0x400118, 0xffffffff); | |
638 | nv_wr32(dev, 0x400130, 0xffffffff); | |
639 | nv_wr32(dev, 0x40011c, 0xffffffff); | |
640 | nv_wr32(dev, 0x400134, 0xffffffff); | |
641 | nv_wr32(dev, 0x400054, 0x34ce3464); | |
642 | ||
643 | ret = nvc0_graph_init_ctxctl(dev); | |
a82dd49f BS |
644 | if (ret) |
645 | return ret; | |
646 | ||
4b223eef BS |
647 | return 0; |
648 | } | |
649 | ||
d5a27370 | 650 | int |
966a5b7d BS |
651 | nvc0_graph_isr_chid(struct drm_device *dev, u64 inst) |
652 | { | |
c420b2dc | 653 | struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO); |
966a5b7d BS |
654 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
655 | struct nouveau_channel *chan; | |
656 | unsigned long flags; | |
657 | int i; | |
658 | ||
659 | spin_lock_irqsave(&dev_priv->channels.lock, flags); | |
c420b2dc | 660 | for (i = 0; i < pfifo->channels; i++) { |
966a5b7d BS |
661 | chan = dev_priv->channels.ptr[i]; |
662 | if (!chan || !chan->ramin) | |
663 | continue; | |
664 | ||
665 | if (inst == chan->ramin->vinst) | |
666 | break; | |
667 | } | |
668 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); | |
669 | return i; | |
670 | } | |
671 | ||
0411de85 BS |
672 | static void |
673 | nvc0_graph_ctxctl_isr(struct drm_device *dev) | |
674 | { | |
675 | u32 ustat = nv_rd32(dev, 0x409c18); | |
676 | ||
677 | if (ustat & 0x00000001) | |
678 | NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n"); | |
679 | if (ustat & 0x00080000) | |
680 | NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n"); | |
681 | if (ustat & ~0x00080001) | |
682 | NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat); | |
683 | ||
684 | nvc0_graph_ctxctl_debug(dev); | |
685 | nv_wr32(dev, 0x409c20, ustat); | |
686 | } | |
687 | ||
966a5b7d BS |
688 | static void |
689 | nvc0_graph_isr(struct drm_device *dev) | |
690 | { | |
691 | u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; | |
692 | u32 chid = nvc0_graph_isr_chid(dev, inst); | |
693 | u32 stat = nv_rd32(dev, 0x400100); | |
694 | u32 addr = nv_rd32(dev, 0x400704); | |
695 | u32 mthd = (addr & 0x00003ffc); | |
696 | u32 subc = (addr & 0x00070000) >> 16; | |
697 | u32 data = nv_rd32(dev, 0x400708); | |
698 | u32 code = nv_rd32(dev, 0x400110); | |
699 | u32 class = nv_rd32(dev, 0x404200 + (subc * 4)); | |
700 | ||
701 | if (stat & 0x00000010) { | |
bd2f2037 BS |
702 | if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) { |
703 | NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] " | |
704 | "subc %d class 0x%04x mthd 0x%04x " | |
705 | "data 0x%08x\n", | |
706 | chid, inst, subc, class, mthd, data); | |
707 | } | |
966a5b7d BS |
708 | nv_wr32(dev, 0x400100, 0x00000010); |
709 | stat &= ~0x00000010; | |
710 | } | |
711 | ||
eae5e7f3 BS |
712 | if (stat & 0x00000020) { |
713 | NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d " | |
714 | "class 0x%04x mthd 0x%04x data 0x%08x\n", | |
715 | chid, inst, subc, class, mthd, data); | |
716 | nv_wr32(dev, 0x400100, 0x00000020); | |
717 | stat &= ~0x00000020; | |
718 | } | |
719 | ||
966a5b7d BS |
720 | if (stat & 0x00100000) { |
721 | NV_INFO(dev, "PGRAPH: DATA_ERROR ["); | |
6effe393 | 722 | nouveau_enum_print(nv50_data_error_names, code); |
966a5b7d BS |
723 | printk("] ch %d [0x%010llx] subc %d class 0x%04x " |
724 | "mthd 0x%04x data 0x%08x\n", | |
725 | chid, inst, subc, class, mthd, data); | |
726 | nv_wr32(dev, 0x400100, 0x00100000); | |
727 | stat &= ~0x00100000; | |
728 | } | |
729 | ||
eae5e7f3 BS |
730 | if (stat & 0x00200000) { |
731 | u32 trap = nv_rd32(dev, 0x400108); | |
732 | NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap); | |
733 | nv_wr32(dev, 0x400108, trap); | |
734 | nv_wr32(dev, 0x400100, 0x00200000); | |
735 | stat &= ~0x00200000; | |
736 | } | |
737 | ||
966a5b7d | 738 | if (stat & 0x00080000) { |
0411de85 | 739 | nvc0_graph_ctxctl_isr(dev); |
966a5b7d BS |
740 | nv_wr32(dev, 0x400100, 0x00080000); |
741 | stat &= ~0x00080000; | |
742 | } | |
743 | ||
744 | if (stat) { | |
745 | NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat); | |
746 | nv_wr32(dev, 0x400100, stat); | |
747 | } | |
748 | ||
749 | nv_wr32(dev, 0x400500, 0x00010001); | |
750 | } | |
51f73d64 | 751 | |
fe799114 BS |
752 | static int |
753 | nvc0_graph_create_fw(struct drm_device *dev, const char *fwname, | |
754 | struct nvc0_graph_fuc *fuc) | |
755 | { | |
756 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
757 | const struct firmware *fw; | |
758 | char f[32]; | |
759 | int ret; | |
760 | ||
761 | snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname); | |
762 | ret = request_firmware(&fw, f, &dev->pdev->dev); | |
763 | if (ret) { | |
764 | snprintf(f, sizeof(f), "nouveau/%s", fwname); | |
765 | ret = request_firmware(&fw, f, &dev->pdev->dev); | |
766 | if (ret) { | |
767 | NV_ERROR(dev, "failed to load %s\n", fwname); | |
768 | return ret; | |
769 | } | |
770 | } | |
771 | ||
772 | fuc->size = fw->size; | |
773 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); | |
774 | release_firmware(fw); | |
775 | return (fuc->data != NULL) ? 0 : -ENOMEM; | |
776 | } | |
777 | ||
778 | static void | |
779 | nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc) | |
780 | { | |
781 | if (fuc->data) { | |
782 | kfree(fuc->data); | |
783 | fuc->data = NULL; | |
784 | } | |
785 | } | |
786 | ||
7a45cd19 BS |
787 | static void |
788 | nvc0_graph_destroy(struct drm_device *dev, int engine) | |
789 | { | |
790 | struct nvc0_graph_priv *priv = nv_engine(dev, engine); | |
791 | ||
0411de85 BS |
792 | if (nouveau_ctxfw) { |
793 | nvc0_graph_destroy_fw(&priv->fuc409c); | |
794 | nvc0_graph_destroy_fw(&priv->fuc409d); | |
795 | nvc0_graph_destroy_fw(&priv->fuc41ac); | |
796 | nvc0_graph_destroy_fw(&priv->fuc41ad); | |
797 | } | |
fe799114 | 798 | |
7a45cd19 | 799 | nouveau_irq_unregister(dev, 12); |
7a45cd19 BS |
800 | |
801 | nouveau_gpuobj_ref(NULL, &priv->unk4188b8); | |
802 | nouveau_gpuobj_ref(NULL, &priv->unk4188b4); | |
803 | ||
804 | if (priv->grctx_vals) | |
805 | kfree(priv->grctx_vals); | |
806 | ||
807 | NVOBJ_ENGINE_DEL(dev, GR); | |
808 | kfree(priv); | |
809 | } | |
810 | ||
811 | int | |
812 | nvc0_graph_create(struct drm_device *dev) | |
813 | { | |
814 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
815 | struct nvc0_graph_priv *priv; | |
816 | int ret, gpc, i; | |
847adea2 | 817 | u32 fermi; |
7a45cd19 | 818 | |
847adea2 BS |
819 | fermi = nvc0_graph_class(dev); |
820 | if (!fermi) { | |
a82dd49f BS |
821 | NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n"); |
822 | return 0; | |
823 | } | |
824 | ||
7a45cd19 BS |
825 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
826 | if (!priv) | |
827 | return -ENOMEM; | |
828 | ||
829 | priv->base.destroy = nvc0_graph_destroy; | |
830 | priv->base.init = nvc0_graph_init; | |
831 | priv->base.fini = nvc0_graph_fini; | |
832 | priv->base.context_new = nvc0_graph_context_new; | |
833 | priv->base.context_del = nvc0_graph_context_del; | |
834 | priv->base.object_new = nvc0_graph_object_new; | |
835 | ||
836 | NVOBJ_ENGINE_ADD(dev, GR, &priv->base); | |
837 | nouveau_irq_register(dev, 12, nvc0_graph_isr); | |
7a45cd19 | 838 | |
0411de85 BS |
839 | if (nouveau_ctxfw) { |
840 | NV_INFO(dev, "PGRAPH: using external firmware\n"); | |
841 | if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) || | |
842 | nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) || | |
843 | nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) || | |
844 | nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) { | |
845 | ret = 0; | |
846 | goto error; | |
847 | } | |
fe799114 BS |
848 | } |
849 | ||
7a45cd19 BS |
850 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4); |
851 | if (ret) | |
852 | goto error; | |
853 | ||
854 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8); | |
855 | if (ret) | |
856 | goto error; | |
857 | ||
858 | for (i = 0; i < 0x1000; i += 4) { | |
859 | nv_wo32(priv->unk4188b4, i, 0x00000010); | |
860 | nv_wo32(priv->unk4188b8, i, 0x00000010); | |
861 | } | |
862 | ||
863 | priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f; | |
864 | priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16; | |
865 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
866 | priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608)); | |
867 | priv->tp_total += priv->tp_nr[gpc]; | |
868 | } | |
869 | ||
870 | /*XXX: these need figuring out... */ | |
871 | switch (dev_priv->chipset) { | |
872 | case 0xc0: | |
873 | if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */ | |
874 | priv->magic_not_rop_nr = 0x07; | |
7a45cd19 BS |
875 | } else |
876 | if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */ | |
877 | priv->magic_not_rop_nr = 0x05; | |
7a45cd19 BS |
878 | } else |
879 | if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */ | |
880 | priv->magic_not_rop_nr = 0x06; | |
7a45cd19 BS |
881 | } |
882 | break; | |
883 | case 0xc3: /* 450, 4/0/0/0, 2 */ | |
884 | priv->magic_not_rop_nr = 0x03; | |
7a45cd19 BS |
885 | break; |
886 | case 0xc4: /* 460, 3/4/0/0, 4 */ | |
887 | priv->magic_not_rop_nr = 0x01; | |
7a45cd19 | 888 | break; |
a219997a BS |
889 | case 0xc1: /* 2/0/0/0, 1 */ |
890 | priv->magic_not_rop_nr = 0x01; | |
a219997a BS |
891 | break; |
892 | case 0xc8: /* 4/4/3/4, 5 */ | |
893 | priv->magic_not_rop_nr = 0x06; | |
a219997a BS |
894 | break; |
895 | case 0xce: /* 4/4/0/0, 4 */ | |
896 | priv->magic_not_rop_nr = 0x03; | |
a219997a | 897 | break; |
3c23a7b8 BS |
898 | case 0xcf: /* 4/0/0/0, 3 */ |
899 | priv->magic_not_rop_nr = 0x03; | |
900 | break; | |
06784090 BS |
901 | case 0xd9: /* 1/0/0/0, 1 */ |
902 | priv->magic_not_rop_nr = 0x01; | |
903 | break; | |
7a45cd19 BS |
904 | } |
905 | ||
906 | if (!priv->magic_not_rop_nr) { | |
907 | NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n", | |
908 | priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2], | |
909 | priv->tp_nr[3], priv->rop_nr); | |
06784090 | 910 | priv->magic_not_rop_nr = 0x00; |
7a45cd19 BS |
911 | } |
912 | ||
913 | NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ | |
914 | NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ | |
7a45cd19 | 915 | NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ |
847adea2 BS |
916 | if (fermi >= 0x9197) |
917 | NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */ | |
918 | if (fermi >= 0x9297) | |
919 | NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */ | |
7a45cd19 BS |
920 | NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */ |
921 | return 0; | |
922 | ||
923 | error: | |
924 | nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR); | |
925 | return ret; | |
926 | } |