[linux-block.git] / drivers / gpu / drm / nouveau / core / engine / graph / nv20.c

#include <core/os.h>
#include <core/class.h>
#include <core/engctx.h>
#include <core/handle.h>
#include <core/enum.h>

#include <subdev/timer.h>
#include <subdev/fb.h>

#include <engine/graph.h>
#include <engine/fifo.h>

#include "nv20.h"
#include "regs.h"

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

static struct nouveau_oclass
nv20_graph_sclass[] = {
	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
	{ 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
	{},
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
nv20_graph_context_ctor(struct nouveau_object *parent,
			struct nouveau_object *engine,
			struct nouveau_oclass *oclass, void *data, u32 size,
			struct nouveau_object **pobject)
{
	struct nv20_graph_chan *chan;
	int ret, i;

	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
					   0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
					   &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	chan->chid = nouveau_fifo_chan(parent)->chid;

	nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
	nv_wo32(chan, 0x033c, 0xffff0000);
	nv_wo32(chan, 0x03a0, 0x0fff0000);
	nv_wo32(chan, 0x03a4, 0x0fff0000);
	nv_wo32(chan, 0x047c, 0x00000101);
	nv_wo32(chan, 0x0490, 0x00000111);
	nv_wo32(chan, 0x04a8, 0x44400000);
	for (i = 0x04d4; i <= 0x04e0; i += 4)
		nv_wo32(chan, i, 0x00030303);
	for (i = 0x04f4; i <= 0x0500; i += 4)
		nv_wo32(chan, i, 0x00080000);
	for (i = 0x050c; i <= 0x0518; i += 4)
		nv_wo32(chan, i, 0x01012000);
	for (i = 0x051c; i <= 0x0528; i += 4)
		nv_wo32(chan, i, 0x000105b8);
	for (i = 0x052c; i <= 0x0538; i += 4)
		nv_wo32(chan, i, 0x00080008);
	for (i = 0x055c; i <= 0x0598; i += 4)
		nv_wo32(chan, i, 0x07ff0000);
	nv_wo32(chan, 0x05a4, 0x4b7fffff);
	nv_wo32(chan, 0x05fc, 0x00000001);
	nv_wo32(chan, 0x0604, 0x00004000);
	nv_wo32(chan, 0x0610, 0x00000001);
	nv_wo32(chan, 0x0618, 0x00040000);
	nv_wo32(chan, 0x061c, 0x00010000);
	for (i = 0x1c1c; i <= 0x248c; i += 16) {
		nv_wo32(chan, (i + 0), 0x10700ff9);
		nv_wo32(chan, (i + 4), 0x0436086c);
		nv_wo32(chan, (i + 8), 0x000c001b);
	}
	nv_wo32(chan, 0x281c, 0x3f800000);
	nv_wo32(chan, 0x2830, 0x3f800000);
	nv_wo32(chan, 0x285c, 0x40000000);
	nv_wo32(chan, 0x2860, 0x3f800000);
	nv_wo32(chan, 0x2864, 0x3f000000);
	nv_wo32(chan, 0x286c, 0x40000000);
	nv_wo32(chan, 0x2870, 0x3f800000);
	nv_wo32(chan, 0x2878, 0xbf800000);
	nv_wo32(chan, 0x2880, 0xbf800000);
	nv_wo32(chan, 0x34a4, 0x000fe000);
	nv_wo32(chan, 0x3530, 0x000003f8);
	nv_wo32(chan, 0x3540, 0x002fe000);
	for (i = 0x355c; i <= 0x3578; i += 4)
		nv_wo32(chan, i, 0x001c527c);
	return 0;
}

int
nv20_graph_context_init(struct nouveau_object *object)
{
	struct nv20_graph_priv *priv = (void *)object->engine;
	struct nv20_graph_chan *chan = (void *)object;
	int ret;

	ret = nouveau_graph_context_init(&chan->base);
	if (ret)
		return ret;

	nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
	return 0;
}

int
nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
{
	struct nv20_graph_priv *priv = (void *)object->engine;
	struct nv20_graph_chan *chan = (void *)object;
	int chid = -1;

	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
	if (nv_rd32(priv, 0x400144) & 0x00010000)
		chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
	if (chan->chid == chid) {
		nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
		nv_wr32(priv, 0x400788, 0x00000002);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
		nv_wr32(priv, 0x400144, 0x10000000);
		nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
	}
	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);

	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
	return nouveau_graph_context_fini(&chan->base, suspend);
}

static struct nouveau_oclass
nv20_graph_cclass = {
	.handle = NV_ENGCTX(GR, 0x20),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv20_graph_context_ctor,
		.dtor = _nouveau_graph_context_dtor,
		.init = nv20_graph_context_init,
		.fini = nv20_graph_context_fini,
		.rd32 = _nouveau_graph_context_rd32,
		.wr32 = _nouveau_graph_context_wr32,
	},
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

void
nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
{
	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
	struct nv20_graph_priv *priv = (void *)engine;
	unsigned long flags;

	pfifo->pause(pfifo, &flags);
	nv04_graph_idle(priv);

	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);

	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);

	if (nv_device(engine)->card_type == NV_20) {
		nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	}

	pfifo->start(pfifo, &flags);
}

void
nv20_graph_intr(struct nouveau_subdev *subdev)
{
	struct nv20_graph_priv *priv = (void *)subdev;
	struct nouveau_engine *engine = nv_engine(subdev);
	struct nouveau_handle *handle = NULL;
	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	u32 chid = (addr & 0x01f00000) >> 20;
	u32 subc = (addr & 0x00070000) >> 16;
	u32 mthd = (addr & 0x00001ffc);
	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
	u32 inst = nv_ro32(priv->ctxtab, (chid * 4)) << 4;
	u32 show = stat;

	if (stat & NV_PGRAPH_INTR_ERROR) {
		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
			handle = nouveau_engctx_lookup_class(engine, inst, class);
			if (handle && !nv_call(handle->object, mthd, data))
				show &= ~NV_PGRAPH_INTR_ERROR;
			nouveau_engctx_handle_put(handle);
		}
	}

	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);

	if (show) {
		nv_info(priv, "");
		nouveau_bitfield_print(nv10_graph_intr_name, show);
		printk(" nsource:");
		nouveau_bitfield_print(nv04_graph_nsource, nsource);
		printk(" nstatus:");
		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
		printk("\n");
		nv_info(priv, "ch %d/%d class 0x%04x mthd 0x%04x data 0x%08x\n",
			chid, subc, class, mthd, data);
	}
}

static int
nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv20_graph_priv *priv;
	int ret;

	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(parent, NULL, 32 * 4, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00001000;
	nv_subdev(priv)->intr = nv20_graph_intr;
	nv_engine(priv)->cclass = &nv20_graph_cclass;
	nv_engine(priv)->sclass = nv20_graph_sclass;
	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
	return 0;
}

void
nv20_graph_dtor(struct nouveau_object *object)
{
	struct nv20_graph_priv *priv = (void *)object;
	nouveau_gpuobj_ref(NULL, &priv->ctxtab);
	nouveau_graph_destroy(&priv->base);
}

int
nv20_graph_init(struct nouveau_object *object)
{
	struct nouveau_engine *engine = nv_engine(object);
	struct nv20_graph_priv *priv = (void *)engine;
	struct nouveau_fb *pfb = nouveau_fb(object);
	u32 tmp, vramsz;
	int ret, i;

	ret = nouveau_graph_init(&priv->base);
	if (ret)
		return ret;

	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);

	if (nv_device(priv)->chipset == 0x20) {
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
		for (i = 0; i < 15; i++)
			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	} else {
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
		for (i = 0; i < 32; i++)
			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	}

	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
	nv_wr32(priv, 0x40009C           , 0x00000040);

	if (nv_device(priv)->chipset >= 0x25) {
		nv_wr32(priv, 0x400890, 0x00a8cfff);
		nv_wr32(priv, 0x400610, 0x304B1FB6);
		nv_wr32(priv, 0x400B80, 0x1cbd3883);
		nv_wr32(priv, 0x400B84, 0x44000000);
		nv_wr32(priv, 0x400098, 0x40000080);
		nv_wr32(priv, 0x400B88, 0x000000ff);

	} else {
		nv_wr32(priv, 0x400880, 0x0008c7df);
		nv_wr32(priv, 0x400094, 0x00000005);
		nv_wr32(priv, 0x400B80, 0x45eae20e);
		nv_wr32(priv, 0x400B84, 0x24000000);
		nv_wr32(priv, 0x400098, 0x00000040);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->tile.regions; i++)
		engine->tile_prog(engine, i);

	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));

	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);

	/* begin RAM config */
	vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
	nv_wr32(priv, 0x400820, 0);
	nv_wr32(priv, 0x400824, 0);
	nv_wr32(priv, 0x400864, vramsz - 1);
	nv_wr32(priv, 0x400868, vramsz - 1);

	/* interesting.. the below overwrites some of the tile setup above.. */
	nv_wr32(priv, 0x400B20, 0x00000000);
	nv_wr32(priv, 0x400B04, 0xFFFFFFFF);

	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
	return 0;
}

struct nouveau_oclass
nv20_graph_oclass = {
	.handle = NV_ENGINE(GR, 0x20),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv20_graph_ctor,
		.dtor = nv20_graph_dtor,
		.init = nv20_graph_init,
		.fini = _nouveau_graph_fini,
	},
};
Commit	Line	Data
ebb945a9 BS	1	#include <core/os.h>
	2	#include <core/class.h>
	3	#include <core/engctx.h>
	4	#include <core/handle.h>
	5	#include <core/enum.h>
	6
	7	#include <subdev/timer.h>
	8	#include <subdev/fb.h>
	9
	10	#include <engine/graph.h>
	11	#include <engine/fifo.h>
	12
	13	#include "nv20.h"
	14	#include "regs.h"
	15
	16	/*******************************************************************************
	17	* Graphics object classes
	18	******************************************************************************/
	19
	20	static struct nouveau_oclass
	21	nv20_graph_sclass[] = {
	22	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
	23	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
	24	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
	25	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
	26	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
	27	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
	28	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
	29	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
	30	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
	31	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
	32	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
	33	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
	34	{ 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
	35	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
	36	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
	37	{},
a0b1de84 BS	38	};
a0b1de84 BS	39
ebb945a9 BS	40	/*******************************************************************************
	41	* PGRAPH context
	42	******************************************************************************/
6ee73861	43
ebb945a9 BS	44	static int
	45	nv20_graph_context_ctor(struct nouveau_object *parent,
	46	struct nouveau_object *engine,
	47	struct nouveau_oclass oclass, void data, u32 size,
	48	struct nouveau_object **pobject)
a0b1de84	49	{
ebb945a9 BS	50	struct nv20_graph_chan *chan;
ebb945a9 BS	51	int ret, i;
a0b1de84	52
ebb945a9 BS	53	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
	54	0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
	55	&chan);
	56	*pobject = nv_object(chan);
	57	if (ret)
	58	return ret;
a0b1de84	59
ebb945a9	60	chan->chid = nouveau_fifo_chan(parent)->chid;
b8c157d3	61
ebb945a9 BS	62	nv_wo32(chan, 0x0000, 0x00000001 \| (chan->chid << 24));
	63	nv_wo32(chan, 0x033c, 0xffff0000);
	64	nv_wo32(chan, 0x03a0, 0x0fff0000);
	65	nv_wo32(chan, 0x03a4, 0x0fff0000);
	66	nv_wo32(chan, 0x047c, 0x00000101);
	67	nv_wo32(chan, 0x0490, 0x00000111);
	68	nv_wo32(chan, 0x04a8, 0x44400000);
6ee73861	69	for (i = 0x04d4; i <= 0x04e0; i += 4)
ebb945a9	70	nv_wo32(chan, i, 0x00030303);
6ee73861	71	for (i = 0x04f4; i <= 0x0500; i += 4)
ebb945a9	72	nv_wo32(chan, i, 0x00080000);
6ee73861	73	for (i = 0x050c; i <= 0x0518; i += 4)
ebb945a9	74	nv_wo32(chan, i, 0x01012000);
6ee73861	75	for (i = 0x051c; i <= 0x0528; i += 4)
ebb945a9	76	nv_wo32(chan, i, 0x000105b8);
6ee73861	77	for (i = 0x052c; i <= 0x0538; i += 4)
ebb945a9	78	nv_wo32(chan, i, 0x00080008);
6ee73861	79	for (i = 0x055c; i <= 0x0598; i += 4)
ebb945a9 BS	80	nv_wo32(chan, i, 0x07ff0000);
	81	nv_wo32(chan, 0x05a4, 0x4b7fffff);
	82	nv_wo32(chan, 0x05fc, 0x00000001);
	83	nv_wo32(chan, 0x0604, 0x00004000);
	84	nv_wo32(chan, 0x0610, 0x00000001);
	85	nv_wo32(chan, 0x0618, 0x00040000);
	86	nv_wo32(chan, 0x061c, 0x00010000);
6ee73861	87	for (i = 0x1c1c; i <= 0x248c; i += 16) {
ebb945a9 BS	88	nv_wo32(chan, (i + 0), 0x10700ff9);
	89	nv_wo32(chan, (i + 4), 0x0436086c);
	90	nv_wo32(chan, (i + 8), 0x000c001b);
6ee73861	91	}
ebb945a9 BS	92	nv_wo32(chan, 0x281c, 0x3f800000);
	93	nv_wo32(chan, 0x2830, 0x3f800000);
	94	nv_wo32(chan, 0x285c, 0x40000000);
	95	nv_wo32(chan, 0x2860, 0x3f800000);
	96	nv_wo32(chan, 0x2864, 0x3f000000);
	97	nv_wo32(chan, 0x286c, 0x40000000);
	98	nv_wo32(chan, 0x2870, 0x3f800000);
	99	nv_wo32(chan, 0x2878, 0xbf800000);
	100	nv_wo32(chan, 0x2880, 0xbf800000);
	101	nv_wo32(chan, 0x34a4, 0x000fe000);
	102	nv_wo32(chan, 0x3530, 0x000003f8);
	103	nv_wo32(chan, 0x3540, 0x002fe000);
6ee73861	104	for (i = 0x355c; i <= 0x3578; i += 4)
ebb945a9 BS	105	nv_wo32(chan, i, 0x001c527c);
ebb945a9 BS	106	return 0;
6ee73861 BS	107	}
6ee73861 BS	108
ebb945a9 BS	109	int
ebb945a9 BS	110	nv20_graph_context_init(struct nouveau_object *object)
6ee73861	111	{
ebb945a9 BS	112	struct nv20_graph_priv priv = (void )object->engine;
	113	struct nv20_graph_chan chan = (void )object;
	114	int ret;
6ee73861	115
ebb945a9 BS	116	ret = nouveau_graph_context_init(&chan->base);
	117	if (ret)
	118	return ret;
6ee73861	119
ebb945a9 BS	120	nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
ebb945a9 BS	121	return 0;
6ee73861 BS	122	}
6ee73861 BS	123
ebb945a9 BS	124	int
ebb945a9 BS	125	nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
6ee73861	126	{
ebb945a9 BS	127	struct nv20_graph_priv priv = (void )object->engine;
	128	struct nv20_graph_chan chan = (void )object;
	129	int chid = -1;
	130
	131	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
	132	if (nv_rd32(priv, 0x400144) & 0x00010000)
	133	chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
	134	if (chan->chid == chid) {
	135	nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
	136	nv_wr32(priv, 0x400788, 0x00000002);
	137	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	138	nv_wr32(priv, 0x400144, 0x10000000);
	139	nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
6ee73861	140	}
ebb945a9	141	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
6ee73861	142
ebb945a9 BS	143	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
ebb945a9 BS	144	return nouveau_graph_context_fini(&chan->base, suspend);
6ee73861 BS	145	}
6ee73861 BS	146
ebb945a9 BS	147	static struct nouveau_oclass
	148	nv20_graph_cclass = {
	149	.handle = NV_ENGCTX(GR, 0x20),
	150	.ofuncs = &(struct nouveau_ofuncs) {
	151	.ctor = nv20_graph_context_ctor,
	152	.dtor = _nouveau_graph_context_dtor,
	153	.init = nv20_graph_context_init,
	154	.fini = nv20_graph_context_fini,
	155	.rd32 = _nouveau_graph_context_rd32,
	156	.wr32 = _nouveau_graph_context_wr32,
	157	},
	158	};
6ee73861	159
ebb945a9 BS	160	/*******************************************************************************
	161	* PGRAPH engine/subdev functions
	162	******************************************************************************/
6ee73861 BS	163
6ee73861 BS	164	void
ebb945a9	165	nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
6ee73861	166	{
ebb945a9 BS	167	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	168	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
	169	struct nv20_graph_priv priv = (void )engine;
3945e475	170	unsigned long flags;
6ee73861	171
ebb945a9 BS	172	pfifo->pause(pfifo, &flags);
ebb945a9 BS	173	nv04_graph_idle(priv);
3945e475	174
ebb945a9 BS	175	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	176	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	177	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
3945e475	178
ebb945a9 BS	179	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	180	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
	181	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	182	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
	183	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	184	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
3945e475	185
ebb945a9 BS	186	if (nv_device(engine)->card_type == NV_20) {
	187	nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
	188	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
	189	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	190	}
6ee73861	191
ebb945a9	192	pfifo->start(pfifo, &flags);
6ee73861 BS	193	}
6ee73861 BS	194
ebb945a9 BS	195	void
ebb945a9 BS	196	nv20_graph_intr(struct nouveau_subdev *subdev)
0d87c100	197	{
ebb945a9 BS	198	struct nv20_graph_priv priv = (void )subdev;
	199	struct nouveau_engine *engine = nv_engine(subdev);
	200	struct nouveau_handle *handle = NULL;
	201	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	202	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	203	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
	204	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	205	u32 chid = (addr & 0x01f00000) >> 20;
	206	u32 subc = (addr & 0x00070000) >> 16;
	207	u32 mthd = (addr & 0x00001ffc);
	208	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	209	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
	210	u32 inst = nv_ro32(priv->ctxtab, (chid * 4)) << 4;
	211	u32 show = stat;
	212
	213	if (stat & NV_PGRAPH_INTR_ERROR) {
	214	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
	215	handle = nouveau_engctx_lookup_class(engine, inst, class);
	216	if (handle && !nv_call(handle->object, mthd, data))
	217	show &= ~NV_PGRAPH_INTR_ERROR;
	218	nouveau_engctx_handle_put(handle);
	219	}
87a326a3	220	}
87a326a3	221
ebb945a9 BS	222	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	223	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
	224
	225	if (show) {
	226	nv_info(priv, "");
	227	nouveau_bitfield_print(nv10_graph_intr_name, show);
	228	printk(" nsource:");
	229	nouveau_bitfield_print(nv04_graph_nsource, nsource);
	230	printk(" nstatus:");
	231	nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
	232	printk("\n");
	233	nv_info(priv, "ch %d/%d class 0x%04x mthd 0x%04x data 0x%08x\n",
	234	chid, subc, class, mthd, data);
6ee73861	235	}
ebb945a9	236	}
6ee73861	237
ebb945a9 BS	238	static int
	239	nv20_graph_ctor(struct nouveau_object parent, struct nouveau_object engine,
	240	struct nouveau_oclass oclass, void data, u32 size,
	241	struct nouveau_object **pobject)
	242	{
	243	struct nv20_graph_priv *priv;
	244	int ret;
6ee73861	245
ebb945a9 BS	246	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
	247	*pobject = nv_object(priv);
	248	if (ret)
	249	return ret;
6ee73861	250
ebb945a9 BS	251	ret = nouveau_gpuobj_new(parent, NULL, 32 * 4, 16,
	252	NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	253	if (ret)
	254	return ret;
6ee73861	255
ebb945a9 BS	256	nv_subdev(priv)->unit = 0x00001000;
	257	nv_subdev(priv)->intr = nv20_graph_intr;
	258	nv_engine(priv)->cclass = &nv20_graph_cclass;
	259	nv_engine(priv)->sclass = nv20_graph_sclass;
	260	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
6ee73861 BS	261	return 0;
	262	}
	263
ebb945a9 BS	264	void
ebb945a9 BS	265	nv20_graph_dtor(struct nouveau_object *object)
6ee73861	266	{
ebb945a9 BS	267	struct nv20_graph_priv priv = (void )object;
	268	nouveau_gpuobj_ref(NULL, &priv->ctxtab);
	269	nouveau_graph_destroy(&priv->base);
	270	}
6ee73861	271
ebb945a9 BS	272	int
	273	nv20_graph_init(struct nouveau_object *object)
	274	{
	275	struct nouveau_engine *engine = nv_engine(object);
	276	struct nv20_graph_priv priv = (void )engine;
	277	struct nouveau_fb *pfb = nouveau_fb(object);
	278	u32 tmp, vramsz;
	279	int ret, i;
6ee73861	280
ebb945a9 BS	281	ret = nouveau_graph_init(&priv->base);
	282	if (ret)
	283	return ret;
6ee73861	284
ebb945a9	285	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
6ee73861	286
ebb945a9 BS	287	if (nv_device(priv)->chipset == 0x20) {
	288	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
	289	for (i = 0; i < 15; i++)
	290	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
	291	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	292	} else {
	293	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
	294	for (i = 0; i < 32; i++)
	295	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
	296	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
6ee73861 BS	297	}
6ee73861 BS	298
ebb945a9 BS	299	nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
ebb945a9 BS	300	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
6ee73861	301
ebb945a9 BS	302	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	303	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	304	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
	305	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	306	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
	307	nv_wr32(priv, 0x40009C , 0x00000040);
274fec93	308
ebb945a9 BS	309	if (nv_device(priv)->chipset >= 0x25) {
	310	nv_wr32(priv, 0x400890, 0x00a8cfff);
	311	nv_wr32(priv, 0x400610, 0x304B1FB6);
	312	nv_wr32(priv, 0x400B80, 0x1cbd3883);
	313	nv_wr32(priv, 0x400B84, 0x44000000);
	314	nv_wr32(priv, 0x400098, 0x40000080);
	315	nv_wr32(priv, 0x400B88, 0x000000ff);
274fec93	316
ebb945a9 BS	317	} else {
	318	nv_wr32(priv, 0x400880, 0x0008c7df);
	319	nv_wr32(priv, 0x400094, 0x00000005);
	320	nv_wr32(priv, 0x400B80, 0x45eae20e);
	321	nv_wr32(priv, 0x400B84, 0x24000000);
	322	nv_wr32(priv, 0x400098, 0x00000040);
	323	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
	324	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
	325	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
	326	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
274fec93	327	}
a0b1de84	328
ebb945a9 BS	329	/* Turn all the tiling regions off. */
	330	for (i = 0; i < pfb->tile.regions; i++)
	331	engine->tile_prog(engine, i);
a0b1de84	332
ebb945a9 BS	333	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
	334	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	335	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
a0b1de84	336
ebb945a9 BS	337	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
ebb945a9 BS	338	nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
a0b1de84	339
ebb945a9 BS	340	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	341	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
	342	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) \| 0x00020100;
	343	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
a0b1de84	344
ebb945a9 BS	345	/* begin RAM config */
	346	vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
	347	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	348	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	349	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	350	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
	351	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	352	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
	353	nv_wr32(priv, 0x400820, 0);
	354	nv_wr32(priv, 0x400824, 0);
	355	nv_wr32(priv, 0x400864, vramsz - 1);
	356	nv_wr32(priv, 0x400868, vramsz - 1);
a0b1de84	357
ebb945a9 BS	358	/* interesting.. the below overwrites some of the tile setup above.. */
	359	nv_wr32(priv, 0x400B20, 0x00000000);
	360	nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
a0b1de84	361
ebb945a9 BS	362	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	363	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	364	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	365	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
a0b1de84 BS	366	return 0;
a0b1de84 BS	367	}
ebb945a9 BS	368
	369	struct nouveau_oclass
	370	nv20_graph_oclass = {
	371	.handle = NV_ENGINE(GR, 0x20),
	372	.ofuncs = &(struct nouveau_ofuncs) {
	373	.ctor = nv20_graph_ctor,
	374	.dtor = nv20_graph_dtor,
	375	.init = nv20_graph_init,
	376	.fini = _nouveau_graph_fini,
	377	},
	378	};