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1 | /* |
2 | * Copyright 2013 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | |
23 | */ | |
24 | ||
25 | #include "os.h" | |
26 | ||
26410c67 ML |
27 | #define GF100 0xc0 |
28 | #define GF117 0xd7 | |
29 | #define GK100 0xe0 | |
8f6fe267 | 30 | #define GK110 0xf0 |
67af60f0 | 31 | #define GK208 0x108 |
26410c67 | 32 | |
23f67841 BS |
33 | #define NV_PGRAPH_TRAPPED_ADDR 0x400704 |
34 | #define NV_PGRAPH_TRAPPED_DATA_LO 0x400708 | |
35 | #define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c | |
36 | ||
37 | #define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700) | |
38 | ||
67af60f0 BS |
39 | #define NV_PGRAPH_FECS_INTR_ACK 0x409004 |
40 | #define NV_PGRAPH_FECS_INTR 0x409008 | |
5d91e191 | 41 | #define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 |
67af60f0 BS |
42 | #define NV_PGRAPH_FECS_INTR_CHSW 0x00000100 |
43 | #define NV_PGRAPH_FECS_INTR_FIFO 0x00000004 | |
44 | #define NV_PGRAPH_FECS_INTR_MODE 0x40900c | |
45 | #define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004 | |
46 | #define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004 | |
47 | #define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000 | |
48 | #define NV_PGRAPH_FECS_INTR_EN_SET 0x409010 | |
49 | #define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004 | |
50 | #define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c | |
51 | #define NV_PGRAPH_FECS_ACCESS 0x409048 | |
52 | #define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002 | |
53 | #define NV_PGRAPH_FECS_FIFO_DATA 0x409064 | |
54 | #define NV_PGRAPH_FECS_FIFO_CMD 0x409068 | |
55 | #define NV_PGRAPH_FECS_FIFO_ACK 0x409074 | |
56 | #define NV_PGRAPH_FECS_CAPS 0x409108 | |
60a4acd7 | 57 | #define NV_PGRAPH_FECS_SIGNAL 0x409400 |
67af60f0 BS |
58 | #define NV_PGRAPH_FECS_IROUTE 0x409404 |
59 | #define NV_PGRAPH_FECS_BAR_MASK0 0x40940c | |
60 | #define NV_PGRAPH_FECS_BAR_MASK1 0x409410 | |
61 | #define NV_PGRAPH_FECS_BAR 0x409414 | |
62 | #define NV_PGRAPH_FECS_BAR_SET 0x409418 | |
63 | #define NV_PGRAPH_FECS_RED_SWITCH 0x409614 | |
64 | #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400 | |
65 | #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200 | |
66 | #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100 | |
67 | #define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040 | |
68 | #define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020 | |
69 | #define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010 | |
70 | #define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002 | |
71 | #define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001 | |
72 | #define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 | |
73 | #define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 | |
74 | #define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c | |
75 | #define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 | |
76 | #define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 | |
77 | #define NV_PGRAPH_FECS_MMCTX_BASE 0x409710 | |
78 | #define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714 | |
79 | #define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718 | |
80 | #define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c | |
81 | #define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720 | |
82 | #define NV_PGRAPH_FECS_MMIO_CTRL 0x409728 | |
83 | #define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c | |
84 | #define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730 | |
85 | #define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c | |
60a4acd7 BS |
86 | #if CHIPSET < GK110 |
87 | #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) | |
88 | #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) | |
89 | #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) | |
e1b22bc1 | 90 | #define NV_PGRAPH_FECS_UNK86C 0x40986c |
60a4acd7 BS |
91 | #else |
92 | #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) | |
93 | #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) | |
e1b22bc1 | 94 | #define NV_PGRAPH_FECS_UNK86C 0x40988c |
60a4acd7 BS |
95 | #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) |
96 | #endif | |
67af60f0 BS |
97 | #define NV_PGRAPH_FECS_STRANDS_CNT 0x409880 |
98 | #define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908 | |
99 | #define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c | |
100 | #define NV_PGRAPH_FECS_STRAND_WORDS 0x409910 | |
101 | #define NV_PGRAPH_FECS_STRAND_DATA 0x409918 | |
102 | #define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c | |
103 | #define NV_PGRAPH_FECS_STRAND_CMD 0x409928 | |
104 | #define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001 | |
105 | #define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002 | |
106 | #define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003 | |
107 | #define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004 | |
108 | #define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a | |
109 | #define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b | |
110 | #define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c | |
111 | #define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d | |
112 | #define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c | |
113 | #define NV_PGRAPH_FECS_MEM_BASE 0x409a04 | |
114 | #define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c | |
115 | #define NV_PGRAPH_FECS_MEM_CMD 0x409a10 | |
116 | #define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007 | |
117 | #define NV_PGRAPH_FECS_MEM_TARGET 0x409a20 | |
118 | #define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000 | |
119 | #define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f | |
120 | #define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001 | |
121 | #define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002 | |
122 | #define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00 | |
123 | #define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04 | |
124 | #define NV_PGRAPH_FECS_CHSW 0x409b0c | |
125 | #define NV_PGRAPH_FECS_CHSW_ACK 0x00000001 | |
60a4acd7 | 126 | #define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c |
67af60f0 | 127 | #define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24 |
60a4acd7 | 128 | |
67af60f0 BS |
129 | #define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004 |
130 | #define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008 | |
131 | #define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004 | |
132 | #define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010 | |
133 | #define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004 | |
134 | #define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c | |
135 | #define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048 | |
136 | #define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002 | |
137 | #define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064 | |
138 | #define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068 | |
139 | #define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074 | |
140 | #define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608 | |
6acc09b9 | 141 | #define NV_PGRAPH_GPCX_GPCCS_CAPS 0x41a108 |
67af60f0 BS |
142 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614 |
143 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800 | |
144 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200 | |
145 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020 | |
146 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002 | |
147 | #define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618 | |
148 | #define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700 | |
149 | #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704 | |
150 | #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c | |
60a4acd7 BS |
151 | #if CHIPSET < GK110 |
152 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) | |
153 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) | |
154 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) | |
e1b22bc1 | 155 | #define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c |
60a4acd7 BS |
156 | #else |
157 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) | |
158 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) | |
e1b22bc1 | 159 | #define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c |
60a4acd7 BS |
160 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) |
161 | #endif | |
67af60f0 BS |
162 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c |
163 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928 | |
164 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003 | |
165 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004 | |
166 | #define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04 | |
60a4acd7 | 167 | |
e99716f1 BS |
168 | #define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) |
169 | #define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) | |
170 | ||
171 | #define T_WAIT 0 | |
172 | #define T_MMCTX 1 | |
173 | #define T_STRWAIT 2 | |
174 | #define T_STRINIT 3 | |
175 | #define T_AUTO 4 | |
176 | #define T_CHAN 5 | |
177 | #define T_LOAD 6 | |
178 | #define T_SAVE 7 | |
179 | #define T_LCHAN 8 | |
180 | #define T_LCTXH 9 | |
181 | ||
67af60f0 BS |
182 | #if CHIPSET < GK208 |
183 | #define imm32(reg,val) /* | |
184 | */ movw reg ((val) & 0x0000ffff) /* | |
185 | */ sethi reg ((val) & 0xffff0000) | |
186 | #else | |
187 | #define imm32(reg,val) /* | |
188 | */ mov reg (val) | |
189 | #endif | |
190 | ||
60a4acd7 | 191 | #define nv_mkio(rv,r,i) /* |
67af60f0 BS |
192 | */ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2)) |
193 | ||
194 | #define hash # | |
195 | #define fn(a) a | |
196 | #if CHIPSET < GK208 | |
197 | #define call(a) call fn(hash)a | |
198 | #else | |
199 | #define call(a) lcall fn(hash)a | |
200 | #endif | |
60a4acd7 BS |
201 | |
202 | #define nv_iord(rv,r,i) /* | |
203 | */ nv_mkio(rv,r,i) /* | |
204 | */ iord rv I[rv] | |
67af60f0 | 205 | |
60a4acd7 BS |
206 | #define nv_iowr(r,i,rv) /* |
207 | */ nv_mkio($r0,r,i) /* | |
208 | */ iowr I[$r0] rv /* | |
209 | */ clear b32 $r0 | |
210 | ||
67af60f0 BS |
211 | #define nv_rd32(reg,addr) /* |
212 | */ imm32($r14, addr) /* | |
213 | */ call(nv_rd32) /* | |
214 | */ mov b32 reg $r15 | |
215 | ||
216 | #define nv_wr32(addr,reg) /* | |
217 | */ mov b32 $r15 reg /* | |
218 | */ imm32($r14, addr) /* | |
219 | */ call(nv_wr32) | |
220 | ||
e99716f1 | 221 | #define trace_set(bit) /* |
e99716f1 BS |
222 | */ clear b32 $r9 /* |
223 | */ bset $r9 bit /* | |
60a4acd7 | 224 | */ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) |
67af60f0 | 225 | |
e99716f1 | 226 | #define trace_clr(bit) /* |
e99716f1 BS |
227 | */ clear b32 $r9 /* |
228 | */ bset $r9 bit /* | |
60a4acd7 | 229 | */ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9) |