Commit | Line | Data |
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6ee73861 | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
6ee73861 | 3 | * |
ebb945a9 BS |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
6ee73861 | 10 | * |
ebb945a9 BS |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. | |
6ee73861 | 13 | * |
ebb945a9 BS |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
6ee73861 | 21 | * |
ebb945a9 | 22 | * Authors: Ben Skeggs |
6ee73861 BS |
23 | */ |
24 | ||
ebb945a9 BS |
25 | #include <core/os.h> |
26 | #include <core/class.h> | |
27 | #include <core/engctx.h> | |
28 | #include <core/namedb.h> | |
29 | #include <core/handle.h> | |
02a841d4 | 30 | #include <core/ramht.h> |
750087f1 | 31 | #include <core/event.h> |
ebb945a9 BS |
32 | |
33 | #include <subdev/instmem.h> | |
34 | #include <subdev/instmem/nv04.h> | |
35 | #include <subdev/timer.h> | |
36 | #include <subdev/fb.h> | |
37 | ||
38 | #include <engine/fifo.h> | |
39 | ||
40 | #include "nv04.h" | |
41 | ||
42 | static struct ramfc_desc | |
43 | nv04_ramfc[] = { | |
c420b2dc BS |
44 | { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, |
45 | { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, | |
46 | { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, | |
47 | { 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, | |
48 | { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE }, | |
49 | { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, | |
50 | { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE }, | |
51 | { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 }, | |
52 | {} | |
53 | }; | |
54 | ||
ebb945a9 BS |
55 | /******************************************************************************* |
56 | * FIFO channel objects | |
57 | ******************************************************************************/ | |
c420b2dc | 58 | |
ebb945a9 BS |
59 | int |
60 | nv04_fifo_object_attach(struct nouveau_object *parent, | |
61 | struct nouveau_object *object, u32 handle) | |
588d7d12 | 62 | { |
ebb945a9 BS |
63 | struct nv04_fifo_priv *priv = (void *)parent->engine; |
64 | struct nv04_fifo_chan *chan = (void *)parent; | |
65 | u32 context, chid = chan->base.chid; | |
66 | int ret; | |
67 | ||
68 | if (nv_iclass(object, NV_GPUOBJ_CLASS)) | |
69 | context = nv_gpuobj(object)->addr >> 4; | |
70 | else | |
71 | context = 0x00000004; /* just non-zero */ | |
72 | ||
73 | switch (nv_engidx(object->engine)) { | |
74 | case NVDEV_ENGINE_DMAOBJ: | |
75 | case NVDEV_ENGINE_SW: | |
76 | context |= 0x00000000; | |
77 | break; | |
78 | case NVDEV_ENGINE_GR: | |
79 | context |= 0x00010000; | |
80 | break; | |
81 | case NVDEV_ENGINE_MPEG: | |
82 | context |= 0x00020000; | |
83 | break; | |
84 | default: | |
85 | return -EINVAL; | |
588d7d12 FJ |
86 | } |
87 | ||
ebb945a9 BS |
88 | context |= 0x80000000; /* valid */ |
89 | context |= chid << 24; | |
90 | ||
91 | mutex_lock(&nv_subdev(priv)->mutex); | |
92 | ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); | |
93 | mutex_unlock(&nv_subdev(priv)->mutex); | |
94 | return ret; | |
95 | } | |
96 | ||
97 | void | |
98 | nv04_fifo_object_detach(struct nouveau_object *parent, int cookie) | |
99 | { | |
100 | struct nv04_fifo_priv *priv = (void *)parent->engine; | |
101 | mutex_lock(&nv_subdev(priv)->mutex); | |
102 | nouveau_ramht_remove(priv->ramht, cookie); | |
103 | mutex_unlock(&nv_subdev(priv)->mutex); | |
588d7d12 FJ |
104 | } |
105 | ||
4c2d4222 BS |
106 | int |
107 | nv04_fifo_context_attach(struct nouveau_object *parent, | |
108 | struct nouveau_object *object) | |
109 | { | |
110 | nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid; | |
111 | return 0; | |
112 | } | |
113 | ||
c420b2dc | 114 | static int |
ebb945a9 BS |
115 | nv04_fifo_chan_ctor(struct nouveau_object *parent, |
116 | struct nouveau_object *engine, | |
117 | struct nouveau_oclass *oclass, void *data, u32 size, | |
118 | struct nouveau_object **pobject) | |
6ee73861 | 119 | { |
ebb945a9 BS |
120 | struct nv04_fifo_priv *priv = (void *)engine; |
121 | struct nv04_fifo_chan *chan; | |
a7c6e75e | 122 | struct nv03_channel_dma_class *args = data; |
6ee73861 BS |
123 | int ret; |
124 | ||
ebb945a9 BS |
125 | if (size < sizeof(*args)) |
126 | return -EINVAL; | |
6ee73861 | 127 | |
ebb945a9 BS |
128 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, |
129 | 0x10000, args->pushbuf, | |
507ceb15 MP |
130 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
131 | (1ULL << NVDEV_ENGINE_SW) | | |
132 | (1ULL << NVDEV_ENGINE_GR), &chan); | |
ebb945a9 BS |
133 | *pobject = nv_object(chan); |
134 | if (ret) | |
135 | return ret; | |
70ee6f1c | 136 | |
ebb945a9 BS |
137 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
138 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | |
4c2d4222 | 139 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; |
ebb945a9 | 140 | chan->ramfc = chan->base.chid * 32; |
6ee73861 | 141 | |
ebb945a9 BS |
142 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); |
143 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); | |
144 | nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); | |
145 | nv_wo32(priv->ramfc, chan->ramfc + 0x10, | |
70ee6f1c BS |
146 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
147 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | | |
c420b2dc | 148 | #ifdef __BIG_ENDIAN |
70ee6f1c | 149 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
c420b2dc | 150 | #endif |
70ee6f1c | 151 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); |
ebb945a9 BS |
152 | return 0; |
153 | } | |
154 | ||
155 | void | |
156 | nv04_fifo_chan_dtor(struct nouveau_object *object) | |
157 | { | |
158 | struct nv04_fifo_priv *priv = (void *)object->engine; | |
159 | struct nv04_fifo_chan *chan = (void *)object; | |
160 | struct ramfc_desc *c = priv->ramfc_desc; | |
ff9e5279 | 161 | |
ebb945a9 BS |
162 | do { |
163 | nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); | |
164 | } while ((++c)->bits); | |
165 | ||
166 | nouveau_fifo_channel_destroy(&chan->base); | |
167 | } | |
c420b2dc | 168 | |
ebb945a9 BS |
169 | int |
170 | nv04_fifo_chan_init(struct nouveau_object *object) | |
171 | { | |
172 | struct nv04_fifo_priv *priv = (void *)object->engine; | |
173 | struct nv04_fifo_chan *chan = (void *)object; | |
174 | u32 mask = 1 << chan->base.chid; | |
175 | unsigned long flags; | |
176 | int ret; | |
177 | ||
178 | ret = nouveau_fifo_channel_init(&chan->base); | |
c420b2dc | 179 | if (ret) |
ebb945a9 BS |
180 | return ret; |
181 | ||
182 | spin_lock_irqsave(&priv->base.lock, flags); | |
183 | nv_mask(priv, NV04_PFIFO_MODE, mask, mask); | |
184 | spin_unlock_irqrestore(&priv->base.lock, flags); | |
185 | return 0; | |
6ee73861 BS |
186 | } |
187 | ||
ebb945a9 BS |
188 | int |
189 | nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend) | |
6ee73861 | 190 | { |
ebb945a9 BS |
191 | struct nv04_fifo_priv *priv = (void *)object->engine; |
192 | struct nv04_fifo_chan *chan = (void *)object; | |
193 | struct nouveau_gpuobj *fctx = priv->ramfc; | |
194 | struct ramfc_desc *c; | |
3945e475 | 195 | unsigned long flags; |
ebb945a9 BS |
196 | u32 data = chan->ramfc; |
197 | u32 chid; | |
6ee73861 | 198 | |
c420b2dc | 199 | /* prevent fifo context switches */ |
ebb945a9 BS |
200 | spin_lock_irqsave(&priv->base.lock, flags); |
201 | nv_wr32(priv, NV03_PFIFO_CACHES, 0); | |
3945e475 | 202 | |
c420b2dc | 203 | /* if this channel is active, replace it with a null context */ |
ebb945a9 BS |
204 | chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; |
205 | if (chid == chan->base.chid) { | |
206 | nv_mask(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); | |
207 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 0); | |
208 | nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); | |
c420b2dc | 209 | |
ebb945a9 | 210 | c = priv->ramfc_desc; |
c420b2dc | 211 | do { |
ebb945a9 BS |
212 | u32 rm = ((1ULL << c->bits) - 1) << c->regs; |
213 | u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; | |
214 | u32 rv = (nv_rd32(priv, c->regp) & rm) >> c->regs; | |
215 | u32 cv = (nv_ro32(fctx, c->ctxp + data) & ~cm); | |
216 | nv_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); | |
217 | } while ((++c)->bits); | |
218 | ||
219 | c = priv->ramfc_desc; | |
220 | do { | |
221 | nv_wr32(priv, c->regp, 0x00000000); | |
c420b2dc BS |
222 | } while ((++c)->bits); |
223 | ||
ebb945a9 BS |
224 | nv_wr32(priv, NV03_PFIFO_CACHE1_GET, 0); |
225 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUT, 0); | |
226 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); | |
227 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); | |
228 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); | |
3945e475 FJ |
229 | } |
230 | ||
c420b2dc | 231 | /* restore normal operation, after disabling dma mode */ |
ebb945a9 BS |
232 | nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); |
233 | nv_wr32(priv, NV03_PFIFO_CACHES, 1); | |
234 | spin_unlock_irqrestore(&priv->base.lock, flags); | |
235 | ||
236 | return nouveau_fifo_channel_fini(&chan->base, suspend); | |
6ee73861 BS |
237 | } |
238 | ||
ebb945a9 BS |
239 | static struct nouveau_ofuncs |
240 | nv04_fifo_ofuncs = { | |
241 | .ctor = nv04_fifo_chan_ctor, | |
242 | .dtor = nv04_fifo_chan_dtor, | |
243 | .init = nv04_fifo_chan_init, | |
244 | .fini = nv04_fifo_chan_fini, | |
245 | .rd32 = _nouveau_fifo_channel_rd32, | |
246 | .wr32 = _nouveau_fifo_channel_wr32, | |
247 | }; | |
248 | ||
249 | static struct nouveau_oclass | |
250 | nv04_fifo_sclass[] = { | |
c97f8c92 | 251 | { NV03_CHANNEL_DMA_CLASS, &nv04_fifo_ofuncs }, |
ebb945a9 BS |
252 | {} |
253 | }; | |
254 | ||
255 | /******************************************************************************* | |
256 | * FIFO context - basically just the instmem reserved for the channel | |
257 | ******************************************************************************/ | |
258 | ||
6ee73861 | 259 | int |
ebb945a9 BS |
260 | nv04_fifo_context_ctor(struct nouveau_object *parent, |
261 | struct nouveau_object *engine, | |
262 | struct nouveau_oclass *oclass, void *data, u32 size, | |
263 | struct nouveau_object **pobject) | |
6ee73861 | 264 | { |
ebb945a9 BS |
265 | struct nv04_fifo_base *base; |
266 | int ret; | |
6ee73861 | 267 | |
ebb945a9 BS |
268 | ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
269 | 0x1000, NVOBJ_FLAG_HEAP, &base); | |
270 | *pobject = nv_object(base); | |
271 | if (ret) | |
272 | return ret; | |
6ee73861 | 273 | |
ebb945a9 BS |
274 | return 0; |
275 | } | |
6ee73861 | 276 | |
ebb945a9 BS |
277 | static struct nouveau_oclass |
278 | nv04_fifo_cclass = { | |
279 | .handle = NV_ENGCTX(FIFO, 0x04), | |
280 | .ofuncs = &(struct nouveau_ofuncs) { | |
281 | .ctor = nv04_fifo_context_ctor, | |
282 | .dtor = _nouveau_fifo_context_dtor, | |
283 | .init = _nouveau_fifo_context_init, | |
284 | .fini = _nouveau_fifo_context_fini, | |
285 | .rd32 = _nouveau_fifo_context_rd32, | |
286 | .wr32 = _nouveau_fifo_context_wr32, | |
287 | }, | |
288 | }; | |
6ee73861 | 289 | |
ebb945a9 BS |
290 | /******************************************************************************* |
291 | * PFIFO engine | |
292 | ******************************************************************************/ | |
6ee73861 | 293 | |
ebb945a9 BS |
294 | void |
295 | nv04_fifo_pause(struct nouveau_fifo *pfifo, unsigned long *pflags) | |
296 | __acquires(priv->base.lock) | |
297 | { | |
298 | struct nv04_fifo_priv *priv = (void *)pfifo; | |
299 | unsigned long flags; | |
6ee73861 | 300 | |
ebb945a9 BS |
301 | spin_lock_irqsave(&priv->base.lock, flags); |
302 | *pflags = flags; | |
303 | ||
304 | nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000000); | |
305 | nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); | |
306 | ||
307 | /* in some cases the puller may be left in an inconsistent state | |
308 | * if you try to stop it while it's busy translating handles. | |
309 | * sometimes you get a CACHE_ERROR, sometimes it just fails | |
310 | * silently; sending incorrect instance offsets to PGRAPH after | |
311 | * it's started up again. | |
312 | * | |
313 | * to avoid this, we invalidate the most recently calculated | |
314 | * instance. | |
315 | */ | |
316 | if (!nv_wait(priv, NV04_PFIFO_CACHE1_PULL0, | |
317 | NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0x00000000)) | |
318 | nv_warn(priv, "timeout idling puller\n"); | |
319 | ||
320 | if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) & | |
321 | NV04_PFIFO_CACHE1_PULL0_HASH_FAILED) | |
322 | nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); | |
323 | ||
324 | nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0x00000000); | |
325 | } | |
6ee73861 | 326 | |
ebb945a9 BS |
327 | void |
328 | nv04_fifo_start(struct nouveau_fifo *pfifo, unsigned long *pflags) | |
329 | __releases(priv->base.lock) | |
330 | { | |
331 | struct nv04_fifo_priv *priv = (void *)pfifo; | |
332 | unsigned long flags = *pflags; | |
6ee73861 | 333 | |
ebb945a9 BS |
334 | nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); |
335 | nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000001); | |
336 | ||
337 | spin_unlock_irqrestore(&priv->base.lock, flags); | |
6ee73861 BS |
338 | } |
339 | ||
ebb945a9 BS |
340 | static const char * |
341 | nv_dma_state_err(u32 state) | |
5178d40d | 342 | { |
ebb945a9 BS |
343 | static const char * const desc[] = { |
344 | "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE", | |
345 | "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK" | |
346 | }; | |
347 | return desc[(state >> 29) & 0x7]; | |
5178d40d BS |
348 | } |
349 | ||
350 | static bool | |
ebb945a9 | 351 | nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) |
5178d40d | 352 | { |
ebb945a9 BS |
353 | struct nv04_fifo_chan *chan = NULL; |
354 | struct nouveau_handle *bind; | |
5178d40d BS |
355 | const int subc = (addr >> 13) & 0x7; |
356 | const int mthd = addr & 0x1ffc; | |
357 | bool handled = false; | |
ebb945a9 | 358 | unsigned long flags; |
5178d40d BS |
359 | u32 engine; |
360 | ||
ebb945a9 BS |
361 | spin_lock_irqsave(&priv->base.lock, flags); |
362 | if (likely(chid >= priv->base.min && chid <= priv->base.max)) | |
363 | chan = (void *)priv->base.channel[chid]; | |
5178d40d BS |
364 | if (unlikely(!chan)) |
365 | goto out; | |
366 | ||
367 | switch (mthd) { | |
ebb945a9 BS |
368 | case 0x0000: |
369 | bind = nouveau_namedb_get(nv_namedb(chan), data); | |
370 | if (unlikely(!bind)) | |
5178d40d BS |
371 | break; |
372 | ||
ebb945a9 BS |
373 | if (nv_engidx(bind->object->engine) == NVDEV_ENGINE_SW) { |
374 | engine = 0x0000000f << (subc * 4); | |
375 | chan->subc[subc] = data; | |
376 | handled = true; | |
377 | ||
378 | nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); | |
379 | } | |
5178d40d | 380 | |
ebb945a9 | 381 | nouveau_namedb_put(bind); |
5178d40d BS |
382 | break; |
383 | default: | |
ebb945a9 | 384 | engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); |
5178d40d BS |
385 | if (unlikely(((engine >> (subc * 4)) & 0xf) != 0)) |
386 | break; | |
387 | ||
ebb945a9 BS |
388 | bind = nouveau_namedb_get(nv_namedb(chan), chan->subc[subc]); |
389 | if (likely(bind)) { | |
390 | if (!nv_call(bind->object, mthd, data)) | |
391 | handled = true; | |
392 | nouveau_namedb_put(bind); | |
393 | } | |
5178d40d BS |
394 | break; |
395 | } | |
396 | ||
397 | out: | |
ebb945a9 | 398 | spin_unlock_irqrestore(&priv->base.lock, flags); |
5178d40d BS |
399 | return handled; |
400 | } | |
401 | ||
fc10199e MS |
402 | static void |
403 | nv04_fifo_cache_error(struct nouveau_device *device, | |
404 | struct nv04_fifo_priv *priv, u32 chid, u32 get) | |
405 | { | |
406 | u32 mthd, data; | |
407 | int ptr; | |
408 | ||
409 | /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my | |
410 | * G80 chips, but CACHE1 isn't big enough for this much data.. Tests | |
411 | * show that it wraps around to the start at GET=0x800.. No clue as to | |
412 | * why.. | |
413 | */ | |
414 | ptr = (get & 0x7ff) >> 2; | |
415 | ||
416 | if (device->card_type < NV_40) { | |
417 | mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr)); | |
418 | data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr)); | |
419 | } else { | |
420 | mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr)); | |
421 | data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr)); | |
422 | } | |
423 | ||
424 | if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { | |
93260d3c MS |
425 | const char *client_name = |
426 | nouveau_client_name_for_fifo_chid(&priv->base, chid); | |
fc10199e | 427 | nv_error(priv, |
93260d3c MS |
428 | "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", |
429 | chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc, | |
430 | data); | |
fc10199e MS |
431 | } |
432 | ||
433 | nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0); | |
434 | nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); | |
435 | ||
436 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, | |
437 | nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1); | |
438 | nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); | |
439 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, | |
440 | nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1); | |
441 | nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0); | |
442 | ||
443 | nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, | |
444 | nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); | |
445 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); | |
446 | } | |
447 | ||
448 | static void | |
449 | nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, | |
450 | u32 chid) | |
451 | { | |
93260d3c | 452 | const char *client_name; |
fc10199e MS |
453 | u32 dma_get = nv_rd32(priv, 0x003244); |
454 | u32 dma_put = nv_rd32(priv, 0x003240); | |
455 | u32 push = nv_rd32(priv, 0x003220); | |
456 | u32 state = nv_rd32(priv, 0x003228); | |
457 | ||
93260d3c MS |
458 | client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid); |
459 | ||
fc10199e MS |
460 | if (device->card_type == NV_50) { |
461 | u32 ho_get = nv_rd32(priv, 0x003328); | |
462 | u32 ho_put = nv_rd32(priv, 0x003320); | |
463 | u32 ib_get = nv_rd32(priv, 0x003334); | |
464 | u32 ib_put = nv_rd32(priv, 0x003330); | |
465 | ||
466 | nv_error(priv, | |
93260d3c MS |
467 | "DMA_PUSHER - ch %d [%s] get 0x%02x%08x put 0x%02x%08x ib_get 0x%08x ib_put 0x%08x state 0x%08x (err: %s) push 0x%08x\n", |
468 | chid, client_name, ho_get, dma_get, ho_put, dma_put, | |
469 | ib_get, ib_put, state, nv_dma_state_err(state), push); | |
fc10199e MS |
470 | |
471 | /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ | |
472 | nv_wr32(priv, 0x003364, 0x00000000); | |
473 | if (dma_get != dma_put || ho_get != ho_put) { | |
474 | nv_wr32(priv, 0x003244, dma_put); | |
475 | nv_wr32(priv, 0x003328, ho_put); | |
476 | } else | |
477 | if (ib_get != ib_put) | |
478 | nv_wr32(priv, 0x003334, ib_put); | |
479 | } else { | |
480 | nv_error(priv, | |
93260d3c MS |
481 | "DMA_PUSHER - ch %d [%s] get 0x%08x put 0x%08x state 0x%08x (err: %s) push 0x%08x\n", |
482 | chid, client_name, dma_get, dma_put, state, | |
483 | nv_dma_state_err(state), push); | |
fc10199e MS |
484 | |
485 | if (dma_get != dma_put) | |
486 | nv_wr32(priv, 0x003244, dma_put); | |
487 | } | |
488 | ||
489 | nv_wr32(priv, 0x003228, 0x00000000); | |
490 | nv_wr32(priv, 0x003220, 0x00000001); | |
491 | nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); | |
492 | } | |
493 | ||
5178d40d | 494 | void |
ebb945a9 | 495 | nv04_fifo_intr(struct nouveau_subdev *subdev) |
5178d40d | 496 | { |
ebb945a9 BS |
497 | struct nouveau_device *device = nv_device(subdev); |
498 | struct nv04_fifo_priv *priv = (void *)subdev; | |
5178d40d BS |
499 | uint32_t status, reassign; |
500 | int cnt = 0; | |
501 | ||
ebb945a9 BS |
502 | reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; |
503 | while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) { | |
5178d40d BS |
504 | uint32_t chid, get; |
505 | ||
ebb945a9 | 506 | nv_wr32(priv, NV03_PFIFO_CACHES, 0); |
5178d40d | 507 | |
ebb945a9 BS |
508 | chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; |
509 | get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); | |
5178d40d BS |
510 | |
511 | if (status & NV_PFIFO_INTR_CACHE_ERROR) { | |
fc10199e | 512 | nv04_fifo_cache_error(device, priv, chid, get); |
5178d40d BS |
513 | status &= ~NV_PFIFO_INTR_CACHE_ERROR; |
514 | } | |
515 | ||
516 | if (status & NV_PFIFO_INTR_DMA_PUSHER) { | |
fc10199e | 517 | nv04_fifo_dma_pusher(device, priv, chid); |
5178d40d BS |
518 | status &= ~NV_PFIFO_INTR_DMA_PUSHER; |
519 | } | |
520 | ||
521 | if (status & NV_PFIFO_INTR_SEMAPHORE) { | |
522 | uint32_t sem; | |
523 | ||
524 | status &= ~NV_PFIFO_INTR_SEMAPHORE; | |
ebb945a9 | 525 | nv_wr32(priv, NV03_PFIFO_INTR_0, |
5178d40d BS |
526 | NV_PFIFO_INTR_SEMAPHORE); |
527 | ||
ebb945a9 BS |
528 | sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); |
529 | nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); | |
5178d40d | 530 | |
ebb945a9 BS |
531 | nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); |
532 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); | |
5178d40d BS |
533 | } |
534 | ||
ebb945a9 | 535 | if (device->card_type == NV_50) { |
5178d40d | 536 | if (status & 0x00000010) { |
5178d40d | 537 | status &= ~0x00000010; |
ebb945a9 | 538 | nv_wr32(priv, 0x002100, 0x00000010); |
5178d40d | 539 | } |
750087f1 BS |
540 | |
541 | if (status & 0x40000000) { | |
79ca2770 | 542 | nvkm_event_send(&priv->base.uevent, 1, 0, NULL, 0); |
750087f1 BS |
543 | nv_wr32(priv, 0x002100, 0x40000000); |
544 | status &= ~0x40000000; | |
545 | } | |
5178d40d BS |
546 | } |
547 | ||
548 | if (status) { | |
ae4ba737 | 549 | nv_warn(priv, "unknown intr 0x%08x, ch %d\n", |
ebb945a9 BS |
550 | status, chid); |
551 | nv_wr32(priv, NV03_PFIFO_INTR_0, status); | |
5178d40d BS |
552 | status = 0; |
553 | } | |
554 | ||
ebb945a9 | 555 | nv_wr32(priv, NV03_PFIFO_CACHES, reassign); |
5178d40d BS |
556 | } |
557 | ||
558 | if (status) { | |
ae4ba737 | 559 | nv_error(priv, "still angry after %d spins, halt\n", cnt); |
ebb945a9 BS |
560 | nv_wr32(priv, 0x002140, 0); |
561 | nv_wr32(priv, 0x000140, 0); | |
5178d40d BS |
562 | } |
563 | ||
ebb945a9 | 564 | nv_wr32(priv, 0x000100, 0x00000100); |
5178d40d | 565 | } |
c420b2dc | 566 | |
ebb945a9 BS |
567 | static int |
568 | nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
569 | struct nouveau_oclass *oclass, void *data, u32 size, | |
570 | struct nouveau_object **pobject) | |
c420b2dc | 571 | { |
ebb945a9 BS |
572 | struct nv04_instmem_priv *imem = nv04_instmem(parent); |
573 | struct nv04_fifo_priv *priv; | |
574 | int ret; | |
c420b2dc | 575 | |
ebb945a9 BS |
576 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 15, &priv); |
577 | *pobject = nv_object(priv); | |
578 | if (ret) | |
579 | return ret; | |
580 | ||
581 | nouveau_ramht_ref(imem->ramht, &priv->ramht); | |
582 | nouveau_gpuobj_ref(imem->ramro, &priv->ramro); | |
583 | nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); | |
584 | ||
585 | nv_subdev(priv)->unit = 0x00000100; | |
586 | nv_subdev(priv)->intr = nv04_fifo_intr; | |
587 | nv_engine(priv)->cclass = &nv04_fifo_cclass; | |
588 | nv_engine(priv)->sclass = nv04_fifo_sclass; | |
589 | priv->base.pause = nv04_fifo_pause; | |
590 | priv->base.start = nv04_fifo_start; | |
591 | priv->ramfc_desc = nv04_ramfc; | |
592 | return 0; | |
593 | } | |
c420b2dc | 594 | |
ebb945a9 BS |
595 | void |
596 | nv04_fifo_dtor(struct nouveau_object *object) | |
597 | { | |
598 | struct nv04_fifo_priv *priv = (void *)object; | |
5787640d BS |
599 | nouveau_gpuobj_ref(NULL, &priv->ramfc); |
600 | nouveau_gpuobj_ref(NULL, &priv->ramro); | |
ebb945a9 BS |
601 | nouveau_ramht_ref(NULL, &priv->ramht); |
602 | nouveau_fifo_destroy(&priv->base); | |
c420b2dc BS |
603 | } |
604 | ||
605 | int | |
ebb945a9 | 606 | nv04_fifo_init(struct nouveau_object *object) |
c420b2dc | 607 | { |
ebb945a9 BS |
608 | struct nv04_fifo_priv *priv = (void *)object; |
609 | int ret; | |
610 | ||
611 | ret = nouveau_fifo_init(&priv->base); | |
612 | if (ret) | |
613 | return ret; | |
c420b2dc | 614 | |
ebb945a9 BS |
615 | nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); |
616 | nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); | |
c420b2dc | 617 | |
ebb945a9 BS |
618 | nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | |
619 | ((priv->ramht->bits - 9) << 16) | | |
620 | (priv->ramht->base.addr >> 8)); | |
621 | nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); | |
622 | nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8); | |
5787640d | 623 | |
ebb945a9 | 624 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); |
c420b2dc | 625 | |
ebb945a9 BS |
626 | nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); |
627 | nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); | |
628 | ||
629 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); | |
630 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); | |
631 | nv_wr32(priv, NV03_PFIFO_CACHES, 1); | |
c420b2dc BS |
632 | return 0; |
633 | } | |
ebb945a9 | 634 | |
16c4f227 BS |
635 | struct nouveau_oclass * |
636 | nv04_fifo_oclass = &(struct nouveau_oclass) { | |
ebb945a9 BS |
637 | .handle = NV_ENGINE(FIFO, 0x04), |
638 | .ofuncs = &(struct nouveau_ofuncs) { | |
639 | .ctor = nv04_fifo_ctor, | |
640 | .dtor = nv04_fifo_dtor, | |
641 | .init = nv04_fifo_init, | |
642 | .fini = _nouveau_fifo_fini, | |
643 | }, | |
644 | }; |