[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / engine / dmaobj / nvc0.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/device.h>
#include <core/gpuobj.h>
#include <core/class.h>

#include <subdev/fb.h>
#include <engine/dmaobj.h>

struct nvc0_dmaeng_priv {
	struct nouveau_dmaeng base;
};

static int
nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
		 struct nouveau_object *parent,
		 struct nouveau_dmaobj *dmaobj,
		 struct nouveau_gpuobj **pgpuobj)
{
	u32 flags0 = nv_mclass(dmaobj);
	u32 flags5 = 0x00000000;
	int ret;

	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
		switch (nv_mclass(parent->parent)) {
		case NVA3_DISP_MAST_CLASS:
		case NVA3_DISP_SYNC_CLASS:
		case NVA3_DISP_OVLY_CLASS:
			break;
		default:
			return -EINVAL;
		}
	} else
		return 0;

	if (!(dmaobj->conf0 & NVC0_DMA_CONF0_ENABLE)) {
		if (dmaobj->target == NV_MEM_TARGET_VM) {
			dmaobj->conf0  = NVC0_DMA_CONF0_PRIV_VM;
			dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_VM;
		} else {
			dmaobj->conf0  = NVC0_DMA_CONF0_PRIV_US;
			dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_LINEAR;
			dmaobj->conf0 |= 0x00020000;
		}
	}

	flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_TYPE) << 22;
	flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_PRIV);
	flags5 |= (dmaobj->conf0 & NVC0_DMA_CONF0_UNKN);

	switch (dmaobj->target) {
	case NV_MEM_TARGET_VM:
		flags0 |= 0x00000000;
		break;
	case NV_MEM_TARGET_VRAM:
		flags0 |= 0x00010000;
		break;
	case NV_MEM_TARGET_PCI:
		flags0 |= 0x00020000;
		break;
	case NV_MEM_TARGET_PCI_NOSNOOP:
		flags0 |= 0x00030000;
		break;
	default:
		return -EINVAL;
	}

	switch (dmaobj->access) {
	case NV_MEM_ACCESS_VM:
		break;
	case NV_MEM_ACCESS_RO:
		flags0 |= 0x00040000;
		break;
	case NV_MEM_ACCESS_WO:
	case NV_MEM_ACCESS_RW:
		flags0 |= 0x00080000;
		break;
	}

	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
	if (ret == 0) {
		nv_wo32(*pgpuobj, 0x00, flags0);
		nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit));
		nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start));
		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 |
					upper_32_bits(dmaobj->start));
		nv_wo32(*pgpuobj, 0x10, 0x00000000);
		nv_wo32(*pgpuobj, 0x14, flags5);
	}

	return ret;
}

static int
nvc0_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		 struct nouveau_oclass *oclass, void *data, u32 size,
		 struct nouveau_object **pobject)
{
	struct nvc0_dmaeng_priv *priv;
	int ret;

	ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->sclass = nouveau_dmaobj_sclass;
	priv->base.bind = nvc0_dmaobj_bind;
	return 0;
}

struct nouveau_oclass
nvc0_dmaeng_oclass = {
	.handle = NV_ENGINE(DMAOBJ, 0xc0),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nvc0_dmaeng_ctor,
		.dtor = _nouveau_dmaeng_dtor,
		.init = _nouveau_dmaeng_init,
		.fini = _nouveau_dmaeng_fini,
	},
};
Commit	Line	Data
ebb945a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
f86770aa	25	#include <core/device.h>
82d23aea BS	26	#include <core/gpuobj.h>
82d23aea BS	27	#include <core/class.h>
ebb945a9	28
82d23aea	29	#include <subdev/fb.h>
ebb945a9 BS	30	#include <engine/dmaobj.h>
	31
	32	struct nvc0_dmaeng_priv {
	33	struct nouveau_dmaeng base;
	34	};
	35
82d23aea BS	36	static int
	37	nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
	38	struct nouveau_object *parent,
	39	struct nouveau_dmaobj *dmaobj,
	40	struct nouveau_gpuobj **pgpuobj)
	41	{
80fe155b BS	42	u32 flags0 = nv_mclass(dmaobj);
	43	u32 flags5 = 0x00000000;
	44	int ret;
82d23aea BS	45
	46	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
	47	switch (nv_mclass(parent->parent)) {
370c00f9 BS	48	case NVA3_DISP_MAST_CLASS:
	49	case NVA3_DISP_SYNC_CLASS:
	50	case NVA3_DISP_OVLY_CLASS:
	51	break;
82d23aea BS	52	default:
	53	return -EINVAL;
	54	}
	55	} else
	56	return 0;
	57
80fe155b BS	58	if (!(dmaobj->conf0 & NVC0_DMA_CONF0_ENABLE)) {
	59	if (dmaobj->target == NV_MEM_TARGET_VM) {
	60	dmaobj->conf0 = NVC0_DMA_CONF0_PRIV_VM;
	61	dmaobj->conf0 \|= NVC0_DMA_CONF0_TYPE_VM;
	62	} else {
	63	dmaobj->conf0 = NVC0_DMA_CONF0_PRIV_US;
	64	dmaobj->conf0 \|= NVC0_DMA_CONF0_TYPE_LINEAR;
	65	dmaobj->conf0 \|= 0x00020000;
	66	}
	67	}
	68
	69	flags0 \|= (dmaobj->conf0 & NVC0_DMA_CONF0_TYPE) << 22;
	70	flags0 \|= (dmaobj->conf0 & NVC0_DMA_CONF0_PRIV);
	71	flags5 \|= (dmaobj->conf0 & NVC0_DMA_CONF0_UNKN);
	72
	73	switch (dmaobj->target) {
	74	case NV_MEM_TARGET_VM:
	75	flags0 \|= 0x00000000;
	76	break;
	77	case NV_MEM_TARGET_VRAM:
	78	flags0 \|= 0x00010000;
	79	break;
	80	case NV_MEM_TARGET_PCI:
	81	flags0 \|= 0x00020000;
	82	break;
	83	case NV_MEM_TARGET_PCI_NOSNOOP:
	84	flags0 \|= 0x00030000;
	85	break;
	86	default:
	87	return -EINVAL;
	88	}
	89
	90	switch (dmaobj->access) {
	91	case NV_MEM_ACCESS_VM:
	92	break;
	93	case NV_MEM_ACCESS_RO:
	94	flags0 \|= 0x00040000;
	95	break;
	96	case NV_MEM_ACCESS_WO:
	97	case NV_MEM_ACCESS_RW:
	98	flags0 \|= 0x00080000;
	99	break;
	100	}
	101
	102	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
	103	if (ret == 0) {
	104	nv_wo32(*pgpuobj, 0x00, flags0);
	105	nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit));
	106	nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start));
	107	nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 \|
	108	upper_32_bits(dmaobj->start));
	109	nv_wo32(*pgpuobj, 0x10, 0x00000000);
	110	nv_wo32(*pgpuobj, 0x14, flags5);
	111	}
	112
82d23aea BS	113	return ret;
	114	}
	115
ebb945a9 BS	116	static int
	117	nvc0_dmaeng_ctor(struct nouveau_object parent, struct nouveau_object engine,
	118	struct nouveau_oclass oclass, void data, u32 size,
	119	struct nouveau_object **pobject)
	120	{
	121	struct nvc0_dmaeng_priv *priv;
	122	int ret;
	123
	124	ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
	125	*pobject = nv_object(priv);
	126	if (ret)
	127	return ret;
	128
f86770aa	129	nv_engine(priv)->sclass = nouveau_dmaobj_sclass;
82d23aea	130	priv->base.bind = nvc0_dmaobj_bind;
ebb945a9 BS	131	return 0;
	132	}
	133
	134	struct nouveau_oclass
	135	nvc0_dmaeng_oclass = {
	136	.handle = NV_ENGINE(DMAOBJ, 0xc0),
	137	.ofuncs = &(struct nouveau_ofuncs) {
	138	.ctor = nvc0_dmaeng_ctor,
	139	.dtor = _nouveau_dmaeng_dtor,
	140	.init = _nouveau_dmaeng_init,
	141	.fini = _nouveau_dmaeng_fini,
	142	},
	143	};