drm/nv50/disp: preparation for storing static class data
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / engine / disp / nve0.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <engine/software.h>
26#include <engine/disp.h>
27
28#include <core/class.h>
29
30#include "nv50.h"
31
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32/*******************************************************************************
33 * Base display object
34 ******************************************************************************/
35
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36static struct nouveau_oclass
37nve0_disp_sclass[] = {
38 { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
39 { NVE0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
40 { NVE0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
41 { NVE0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
42 { NVE0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
43 {}
44};
45
46static struct nouveau_oclass
47nve0_disp_base_oclass[] = {
d2fa7d32 48 { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs, nvd0_disp_base_omthds },
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49 {}
50};
51
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52/*******************************************************************************
53 * Display engine implementation
54 ******************************************************************************/
55
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56static int
57nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
58 struct nouveau_oclass *oclass, void *data, u32 size,
59 struct nouveau_object **pobject)
60{
61 struct nv50_disp_priv *priv;
1d7c71a3 62 int heads = nv_rd32(parent, 0x022448);
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63 int ret;
64
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65 ret = nouveau_disp_create(parent, engine, oclass, heads,
66 "PDISP", "display", &priv);
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67 *pobject = nv_object(priv);
68 if (ret)
69 return ret;
70
71 nv_engine(priv)->sclass = nve0_disp_base_oclass;
72 nv_engine(priv)->cclass = &nv50_disp_cclass;
73 nv_subdev(priv)->intr = nvd0_disp_intr;
5cc027f6 74 INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
46654061 75 priv->sclass = nve0_disp_sclass;
1d7c71a3 76 priv->head.nr = heads;
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77 priv->dac.nr = 3;
78 priv->sor.nr = 4;
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79 priv->dac.power = nv50_dac_power;
80 priv->dac.sense = nv50_dac_sense;
74b66850 81 priv->sor.power = nv50_sor_power;
0a9e2b95 82 priv->sor.hda_eld = nvd0_hda_eld;
1c30cd09 83 priv->sor.hdmi = nvd0_hdmi_ctrl;
0a0afd28 84 priv->sor.dp = &nvd0_sor_dp_func;
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85 return 0;
86}
87
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88struct nouveau_oclass *
89nve0_disp_oclass = &(struct nv50_disp_impl) {
90 .base.base.handle = NV_ENGINE(DISP, 0x91),
91 .base.base.ofuncs = &(struct nouveau_ofuncs) {
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92 .ctor = nve0_disp_ctor,
93 .dtor = _nouveau_disp_dtor,
94 .init = _nouveau_disp_init,
95 .fini = _nouveau_disp_fini,
96 },
a8f8b489 97}.base.base;