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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <engine/software.h> | |
26 | #include <engine/disp.h> | |
27 | ||
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28 | #include <core/class.h> |
29 | ||
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30 | #include "nv50.h" |
31 | ||
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32 | /******************************************************************************* |
33 | * Base display object | |
34 | ******************************************************************************/ | |
35 | ||
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36 | static struct nouveau_oclass |
37 | nva3_disp_sclass[] = { | |
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38 | { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, |
39 | { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, | |
40 | { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, | |
41 | { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, | |
42 | { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, | |
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43 | {} |
44 | }; | |
45 | ||
d2fa7d32 | 46 | static struct nouveau_omthds |
6c5a0424 | 47 | nva3_disp_base_omthds[] = { |
d2fa7d32 | 48 | { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, |
74b66850 | 49 | { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, |
0a9e2b95 | 50 | { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd }, |
1c30cd09 | 51 | { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd }, |
4a230fa6 | 52 | { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, |
ebd6acbb | 53 | { SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd }, |
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54 | { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, |
55 | { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, | |
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56 | { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, |
57 | { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, | |
58 | { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, | |
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59 | {}, |
60 | }; | |
61 | ||
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62 | static struct nouveau_oclass |
63 | nva3_disp_base_oclass[] = { | |
ef22c8bb | 64 | { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs, nva3_disp_base_omthds }, |
370c00f9 | 65 | {} |
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66 | }; |
67 | ||
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68 | /******************************************************************************* |
69 | * Display engine implementation | |
70 | ******************************************************************************/ | |
71 | ||
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72 | static int |
73 | nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
74 | struct nouveau_oclass *oclass, void *data, u32 size, | |
75 | struct nouveau_object **pobject) | |
76 | { | |
77 | struct nv50_disp_priv *priv; | |
78 | int ret; | |
79 | ||
1d7c71a3 | 80 | ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", |
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81 | "display", &priv); |
82 | *pobject = nv_object(priv); | |
83 | if (ret) | |
84 | return ret; | |
85 | ||
86 | nv_engine(priv)->sclass = nva3_disp_base_oclass; | |
87 | nv_engine(priv)->cclass = &nv50_disp_cclass; | |
88 | nv_subdev(priv)->intr = nv50_disp_intr; | |
5cc027f6 | 89 | INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); |
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90 | priv->sclass = nva3_disp_sclass; |
91 | priv->head.nr = 2; | |
92 | priv->dac.nr = 3; | |
93 | priv->sor.nr = 4; | |
a2bc283f | 94 | priv->pior.nr = 3; |
ef22c8bb | 95 | priv->dac.power = nv50_dac_power; |
7ebb38b5 | 96 | priv->dac.sense = nv50_dac_sense; |
ef22c8bb | 97 | priv->sor.power = nv50_sor_power; |
a4feaf4e | 98 | priv->sor.hda_eld = nva3_hda_eld; |
8e9e3d2d | 99 | priv->sor.hdmi = nva3_hdmi_ctrl; |
a2bc283f | 100 | priv->pior.power = nv50_pior_power; |
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101 | return 0; |
102 | } | |
103 | ||
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104 | struct nouveau_oclass * |
105 | nva3_disp_oclass = &(struct nv50_disp_impl) { | |
106 | .base.base.handle = NV_ENGINE(DISP, 0x85), | |
107 | .base.base.ofuncs = &(struct nouveau_ofuncs) { | |
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108 | .ctor = nva3_disp_ctor, |
109 | .dtor = _nouveau_disp_dtor, | |
110 | .init = _nouveau_disp_init, | |
111 | .fini = _nouveau_disp_fini, | |
112 | }, | |
79ca2770 | 113 | .base.vblank = &nv50_disp_vblank_func, |
b8407c9e | 114 | .base.outp = nv94_disp_outp_sclass, |
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115 | .mthd.core = &nv94_disp_mast_mthd_chan, |
116 | .mthd.base = &nv84_disp_sync_mthd_chan, | |
117 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, | |
118 | .mthd.prev = 0x000004, | |
a8f8b489 | 119 | }.base.base; |