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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
70c0f263 | 25 | #include <subdev/bios.h> |
a10220bb | 26 | #include <subdev/bus.h> |
e0996aea | 27 | #include <subdev/gpio.h> |
4196faa8 | 28 | #include <subdev/i2c.h> |
8aceb7de | 29 | #include <subdev/clock.h> |
aa1b9b48 | 30 | #include <subdev/therm.h> |
d38ac521 | 31 | #include <subdev/mxm.h> |
cb75d97e | 32 | #include <subdev/devinit.h> |
7d9115de | 33 | #include <subdev/mc.h> |
5a5c7432 | 34 | #include <subdev/timer.h> |
861d2107 BS |
35 | #include <subdev/fb.h> |
36 | #include <subdev/ltcg.h> | |
c0abf5c9 | 37 | #include <subdev/ibus.h> |
3863c9bc BS |
38 | #include <subdev/instmem.h> |
39 | #include <subdev/vm.h> | |
40 | #include <subdev/bar.h> | |
ff4b42c7 | 41 | #include <subdev/pwr.h> |
c9c0ccae | 42 | #include <subdev/volt.h> |
9274f4a9 | 43 | |
dded35de | 44 | #include <engine/device.h> |
ebb945a9 BS |
45 | #include <engine/dmaobj.h> |
46 | #include <engine/fifo.h> | |
47 | #include <engine/software.h> | |
48 | #include <engine/graph.h> | |
49 | #include <engine/vp.h> | |
50 | #include <engine/bsp.h> | |
51 | #include <engine/ppp.h> | |
52 | #include <engine/copy.h> | |
53 | #include <engine/disp.h> | |
aa4d7a4d | 54 | #include <engine/perfmon.h> |
ebb945a9 | 55 | |
9274f4a9 BS |
56 | int |
57 | nvc0_identify(struct nouveau_device *device) | |
58 | { | |
59 | switch (device->chipset) { | |
60 | case 0xc0: | |
2094dd82 | 61 | device->cname = "GF100"; |
70c0f263 | 62 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
7356859a | 63 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
c26fe843 | 64 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
8aceb7de | 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
7b49bd68 | 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
d38ac521 | 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
08f6fbdb | 69 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
48ae0b35 | 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
c9c0ccae | 79 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
ebb945a9 | 80 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
16c4f227 | 81 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 82 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 83 | device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; |
7d8bd91b | 84 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 85 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 86 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 BS |
87 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
88 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; | |
a8f8b489 | 89 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
aa4d7a4d | 90 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
91 | break; |
92 | case 0xc4: | |
2094dd82 | 93 | device->cname = "GF104"; |
70c0f263 | 94 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
7356859a | 95 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
c26fe843 | 96 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
8aceb7de | 97 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
7b49bd68 | 98 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
d38ac521 | 99 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 100 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
08f6fbdb | 101 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
48ae0b35 | 102 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 103 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 104 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 105 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 106 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 107 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
108 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
109 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 110 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
c9c0ccae | 111 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
ebb945a9 | 112 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
16c4f227 | 113 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 114 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
eeb0558e | 115 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
7d8bd91b | 116 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 117 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 118 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 BS |
119 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
120 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; | |
a8f8b489 | 121 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
aa4d7a4d | 122 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
123 | break; |
124 | case 0xc3: | |
2094dd82 | 125 | device->cname = "GF106"; |
70c0f263 | 126 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
7356859a | 127 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
c26fe843 | 128 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
8aceb7de | 129 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
7b49bd68 | 130 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
d38ac521 | 131 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 132 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 133 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
48ae0b35 | 134 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 135 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 136 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 137 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 138 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 139 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
140 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
141 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 142 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
c9c0ccae | 143 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
ebb945a9 | 144 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
16c4f227 | 145 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 146 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
eeb0558e | 147 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
7d8bd91b | 148 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 149 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 150 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 | 151 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
a8f8b489 | 152 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
aa4d7a4d | 153 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
154 | break; |
155 | case 0xce: | |
2094dd82 | 156 | device->cname = "GF114"; |
70c0f263 | 157 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
7356859a | 158 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
c26fe843 | 159 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
8aceb7de | 160 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
7b49bd68 | 161 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
d38ac521 | 162 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 163 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
6e9cbb40 | 164 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
48ae0b35 | 165 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 166 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 167 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 168 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 169 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 170 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
171 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
172 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 173 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
c9c0ccae | 174 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
ebb945a9 | 175 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
16c4f227 | 176 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 177 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
eeb0558e | 178 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
7d8bd91b | 179 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 180 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 181 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 BS |
182 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
183 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; | |
a8f8b489 | 184 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
aa4d7a4d | 185 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
186 | break; |
187 | case 0xcf: | |
2094dd82 | 188 | device->cname = "GF116"; |
70c0f263 | 189 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
7356859a | 190 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
c26fe843 | 191 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
8aceb7de | 192 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
7b49bd68 | 193 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
d38ac521 | 194 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 195 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 196 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
48ae0b35 | 197 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 198 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 199 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 200 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 201 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 202 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
203 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
204 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 205 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
c9c0ccae | 206 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
ebb945a9 | 207 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
16c4f227 | 208 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 209 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
eeb0558e | 210 | device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; |
7d8bd91b | 211 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 212 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 213 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 BS |
214 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
215 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; | |
a8f8b489 | 216 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
aa4d7a4d | 217 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
218 | break; |
219 | case 0xc1: | |
2094dd82 | 220 | device->cname = "GF108"; |
70c0f263 | 221 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
7356859a | 222 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
c26fe843 | 223 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
8aceb7de | 224 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
7b49bd68 | 225 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
d38ac521 | 226 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 227 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 228 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
48ae0b35 | 229 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 230 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 231 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 232 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 233 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 234 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
235 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
236 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 237 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
c9c0ccae | 238 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
ebb945a9 | 239 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
16c4f227 | 240 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 241 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 242 | device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; |
7d8bd91b | 243 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 244 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 245 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 | 246 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
a8f8b489 | 247 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
aa4d7a4d | 248 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
249 | break; |
250 | case 0xc8: | |
2094dd82 | 251 | device->cname = "GF110"; |
70c0f263 | 252 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
7356859a | 253 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
c26fe843 | 254 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
8aceb7de | 255 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
7b49bd68 | 256 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
d38ac521 | 257 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 258 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
0bae1d61 | 259 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
48ae0b35 | 260 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 261 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 262 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 263 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 264 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 265 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
266 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
267 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 268 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
c9c0ccae | 269 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
ebb945a9 | 270 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; |
16c4f227 | 271 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 272 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 273 | device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; |
7d8bd91b | 274 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 275 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 276 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 BS |
277 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
278 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; | |
a8f8b489 | 279 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
aa4d7a4d | 280 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
281 | break; |
282 | case 0xd9: | |
2094dd82 | 283 | device->cname = "GF119"; |
70c0f263 | 284 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
d93174ec | 285 | device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; |
c26fe843 | 286 | device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; |
8aceb7de | 287 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
bc79202f | 288 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
d38ac521 | 289 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 290 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 291 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
48ae0b35 | 292 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
5a5c7432 | 293 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 294 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 295 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
3f196a04 | 296 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 297 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3f196a04 BS |
298 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
299 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
ff4b42c7 | 300 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
c9c0ccae | 301 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
3f196a04 | 302 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
16c4f227 | 303 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 304 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 305 | device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; |
3f196a04 BS |
306 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
307 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; | |
308 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | |
309 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; | |
a8f8b489 | 310 | device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; |
aa4d7a4d | 311 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
3f196a04 BS |
312 | break; |
313 | case 0xd7: | |
314 | device->cname = "GF117"; | |
315 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
d93174ec | 316 | device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; |
82c2b5ed | 317 | device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; |
3f196a04 BS |
318 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
319 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | |
320 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | |
cf336014 | 321 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 322 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
48ae0b35 | 323 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
3f196a04 | 324 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 325 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
f6bad8ab | 326 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
c0abf5c9 | 327 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
24a4ae86 | 328 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
3863c9bc BS |
329 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
330 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
344e107d | 331 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
16c4f227 | 332 | device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; |
c46c3ddf | 333 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
26410c67 | 334 | device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; |
7d8bd91b | 335 | device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; |
23c14ed2 | 336 | device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; |
4a795014 | 337 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
ebb945a9 | 338 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; |
a8f8b489 | 339 | device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; |
aa4d7a4d | 340 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; |
9274f4a9 BS |
341 | break; |
342 | default: | |
343 | nv_fatal(device, "unknown Fermi chipset\n"); | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
347 | return 0; | |
7b49bd68 | 348 | } |