[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / engine / device / nv10.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clock.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>

#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/disp.h>

int
nv10_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x10:
		device->cname = "NV10";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x15:
		device->cname = "NV15";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x16:
		device->cname = "NV16";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x1a:
		device->cname = "nForce";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv1a_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x11:
		device->cname = "NV11";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x17:
		device->cname = "NV17";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x1f:
		device->cname = "nForce2";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv1a_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x18:
		device->cname = "NV18";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Celsius chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
70c0f263	25	#include <subdev/bios.h>
a10220bb	26	#include <subdev/bus.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
8aceb7de	29	#include <subdev/clock.h>
cb75d97e	30	#include <subdev/devinit.h>
7d9115de	31	#include <subdev/mc.h>
5a5c7432	32	#include <subdev/timer.h>
861d2107	33	#include <subdev/fb.h>
3863c9bc BS	34	#include <subdev/instmem.h>
3863c9bc BS	35	#include <subdev/vm.h>
9274f4a9	36
dded35de	37	#include <engine/device.h>
ebb945a9 BS	38	#include <engine/dmaobj.h>
	39	#include <engine/fifo.h>
	40	#include <engine/software.h>
	41	#include <engine/graph.h>
	42	#include <engine/disp.h>
	43
9274f4a9 BS	44	int
	45	nv10_identify(struct nouveau_device *device)
	46	{
	47	switch (device->chipset) {
	48	case 0x10:
2094dd82	49	device->cname = "NV10";
70c0f263	50	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	51	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	52	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	53	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	54	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
08f6fbdb	55	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	56	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	57	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	58	device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
24a4ae86	59	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	60	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9 BS	61	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
	62	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
	63	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	64	break;
9274f4a9 BS	65	case 0x15:
2094dd82	66	device->cname = "NV15";
70c0f263	67	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	68	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	69	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	70	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	71	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
08f6fbdb	72	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	73	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	74	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	75	device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
24a4ae86	76	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	77	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9	78	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227	79	device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
c46c3ddf	80	device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 BS	81	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
ebb945a9 BS	82	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	83	break;
9274f4a9 BS	84	case 0x16:
2094dd82	85	device->cname = "NV16";
70c0f263	86	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	87	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	88	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	89	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	90	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
08f6fbdb	91	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	92	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	93	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	94	device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
24a4ae86	95	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	96	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9	97	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227	98	device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
c46c3ddf	99	device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 BS	100	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
ebb945a9 BS	101	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	102	break;
9274f4a9 BS	103	case 0x1a:
2094dd82	104	device->cname = "nForce";
70c0f263	105	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	106	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	107	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	108	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	109	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
08f6fbdb	110	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	111	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	112	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	113	device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
24a4ae86	114	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	115	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9	116	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227	117	device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
c46c3ddf	118	device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 BS	119	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
ebb945a9 BS	120	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	121	break;
9274f4a9 BS	122	case 0x11:
2094dd82	123	device->cname = "NV11";
70c0f263	124	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	125	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	126	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	127	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	128	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
08f6fbdb	129	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	130	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	131	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	132	device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
24a4ae86	133	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	134	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9	135	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227	136	device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
c46c3ddf	137	device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 BS	138	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
ebb945a9 BS	139	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	140	break;
9274f4a9 BS	141	case 0x17:
2094dd82	142	device->cname = "NV17";
70c0f263	143	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	144	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	145	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	146	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	147	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
08f6fbdb	148	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	149	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	150	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	151	device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
24a4ae86	152	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	153	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9	154	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227	155	device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
c46c3ddf	156	device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 BS	157	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
ebb945a9 BS	158	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	159	break;
9274f4a9 BS	160	case 0x1f:
2094dd82	161	device->cname = "nForce2";
70c0f263	162	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	163	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	164	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	165	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	166	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
08f6fbdb	167	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	168	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	169	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	170	device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
24a4ae86	171	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	172	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9	173	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227	174	device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
c46c3ddf	175	device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 BS	176	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
ebb945a9 BS	177	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	178	break;
9274f4a9 BS	179	case 0x18:
2094dd82	180	device->cname = "NV18";
70c0f263	181	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	182	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c	183	device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de	184	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cf336014	185	device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
08f6fbdb	186	device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
48ae0b35	187	device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
5a5c7432	188	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e	189	device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
24a4ae86	190	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
3863c9bc	191	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9	192	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227	193	device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
c46c3ddf	194	device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 BS	195	device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
ebb945a9 BS	196	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	197	break;
	198	default:
	199	nv_fatal(device, "unknown Celsius chipset\n");
	200	return -EINVAL;
	201	}
	202
	203	return 0;
	204	}