[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / engine / device / base.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/object.h>
#include <core/device.h>
#include <core/client.h>
#include <core/option.h>

#include <core/class.h>

#include <engine/device.h>

static DEFINE_MUTEX(nv_devices_mutex);
static LIST_HEAD(nv_devices);

struct nouveau_device *
nouveau_device_find(u64 name)
{
	struct nouveau_device *device, *match = NULL;
	mutex_lock(&nv_devices_mutex);
	list_for_each_entry(device, &nv_devices, head) {
		if (device->handle == name) {
			match = device;
			break;
		}
	}
	mutex_unlock(&nv_devices_mutex);
	return match;
}

/******************************************************************************
 * nouveau_devobj (0x0080): class implementation
 *****************************************************************************/
struct nouveau_devobj {
	struct nouveau_parent base;
	struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
};

static const u64 disable_map[] = {
	[NVDEV_SUBDEV_VBIOS]	= NV_DEVICE_DISABLE_VBIOS,
	[NVDEV_SUBDEV_DEVINIT]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_GPIO]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_I2C]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_CLOCK]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_MXM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_MC]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_BUS]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_TIMER]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_FB]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_LTCG]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_IBUS]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_INSTMEM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_VM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_BAR]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_VOLT]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_THERM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_ENGINE_DMAOBJ]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_ENGINE_FIFO]	= NV_DEVICE_DISABLE_FIFO,
	[NVDEV_ENGINE_SW]	= NV_DEVICE_DISABLE_FIFO,
	[NVDEV_ENGINE_GR]	= NV_DEVICE_DISABLE_GRAPH,
	[NVDEV_ENGINE_MPEG]	= NV_DEVICE_DISABLE_MPEG,
	[NVDEV_ENGINE_ME]	= NV_DEVICE_DISABLE_ME,
	[NVDEV_ENGINE_VP]	= NV_DEVICE_DISABLE_VP,
	[NVDEV_ENGINE_CRYPT]	= NV_DEVICE_DISABLE_CRYPT,
	[NVDEV_ENGINE_BSP]	= NV_DEVICE_DISABLE_BSP,
	[NVDEV_ENGINE_PPP]	= NV_DEVICE_DISABLE_PPP,
	[NVDEV_ENGINE_COPY0]	= NV_DEVICE_DISABLE_COPY0,
	[NVDEV_ENGINE_COPY1]	= NV_DEVICE_DISABLE_COPY1,
	[NVDEV_ENGINE_VIC]	= NV_DEVICE_DISABLE_VIC,
	[NVDEV_ENGINE_VENC]	= NV_DEVICE_DISABLE_VENC,
	[NVDEV_ENGINE_DISP]	= NV_DEVICE_DISABLE_DISP,
	[NVDEV_SUBDEV_NR]	= 0,
};

static int
nouveau_devobj_ctor(struct nouveau_object *parent,
		    struct nouveau_object *engine,
		    struct nouveau_oclass *oclass, void *data, u32 size,
		    struct nouveau_object **pobject)
{
	struct nouveau_client *client = nv_client(parent);
	struct nouveau_device *device;
	struct nouveau_devobj *devobj;
	struct nv_device_class *args = data;
	u32 boot0, strap;
	u64 disable, mmio_base, mmio_size;
	void __iomem *map;
	int ret, i, c;

	if (size < sizeof(struct nv_device_class))
		return -EINVAL;

	/* find the device subdev that matches what the client requested */
	device = nv_device(client->device);
	if (args->device != ~0) {
		device = nouveau_device_find(args->device);
		if (!device)
			return -ENODEV;
	}

	ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL,
				    (1ULL << NVDEV_ENGINE_DMAOBJ) |
				    (1ULL << NVDEV_ENGINE_FIFO) |
				    (1ULL << NVDEV_ENGINE_DISP), &devobj);
	*pobject = nv_object(devobj);
	if (ret)
		return ret;

	mmio_base = pci_resource_start(device->pdev, 0);
	mmio_size = pci_resource_len(device->pdev, 0);

	/* translate api disable mask into internal mapping */
	disable = args->debug0;
	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
		if (args->disable & disable_map[i])
			disable |= (1ULL << i);
	}

	/* identify the chipset, and determine classes of subdev/engines */
	if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) &&
	    !device->card_type) {
		map = ioremap(mmio_base, 0x102000);
		if (map == NULL)
			return -ENOMEM;

		/* switch mmio to cpu's native endianness */
#ifndef __BIG_ENDIAN
		if (ioread32_native(map + 0x000004) != 0x00000000)
#else
		if (ioread32_native(map + 0x000004) == 0x00000000)
#endif
			iowrite32_native(0x01000001, map + 0x000004);

		/* read boot0 and strapping information */
		boot0 = ioread32_native(map + 0x000000);
		strap = ioread32_native(map + 0x101000);
		iounmap(map);

		/* determine chipset and derive architecture from it */
		if ((boot0 & 0x0f000000) > 0) {
			device->chipset = (boot0 & 0xff00000) >> 20;
			switch (device->chipset & 0xf0) {
			case 0x10: device->card_type = NV_10; break;
			case 0x20: device->card_type = NV_20; break;
			case 0x30: device->card_type = NV_30; break;
			case 0x40:
			case 0x60: device->card_type = NV_40; break;
			case 0x50:
			case 0x80:
			case 0x90:
			case 0xa0: device->card_type = NV_50; break;
			case 0xc0: device->card_type = NV_C0; break;
			case 0xd0: device->card_type = NV_D0; break;
			case 0xe0:
			case 0xf0: device->card_type = NV_E0; break;
			default:
				break;
			}
		} else
		if ((boot0 & 0xff00fff0) == 0x20004000) {
			if (boot0 & 0x00f00000)
				device->chipset = 0x05;
			else
				device->chipset = 0x04;
			device->card_type = NV_04;
		}

		switch (device->card_type) {
		case NV_04: ret = nv04_identify(device); break;
		case NV_10: ret = nv10_identify(device); break;
		case NV_20: ret = nv20_identify(device); break;
		case NV_30: ret = nv30_identify(device); break;
		case NV_40: ret = nv40_identify(device); break;
		case NV_50: ret = nv50_identify(device); break;
		case NV_C0:
		case NV_D0: ret = nvc0_identify(device); break;
		case NV_E0: ret = nve0_identify(device); break;
		default:
			ret = -EINVAL;
			break;
		}

		if (ret) {
			nv_error(device, "unknown chipset, 0x%08x\n", boot0);
			return ret;
		}

		nv_info(device, "BOOT0  : 0x%08x\n", boot0);
		nv_info(device, "Chipset: %s (NV%02X)\n",
			device->cname, device->chipset);
		nv_info(device, "Family : NV%02X\n", device->card_type);

		/* determine frequency of timing crystal */
		if ( device->chipset < 0x17 ||
		    (device->chipset >= 0x20 && device->chipset < 0x25))
			strap &= 0x00000040;
		else
			strap &= 0x00400040;

		switch (strap) {
		case 0x00000000: device->crystal = 13500; break;
		case 0x00000040: device->crystal = 14318; break;
		case 0x00400000: device->crystal = 27000; break;
		case 0x00400040: device->crystal = 25000; break;
		}

		nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
	}

	if (!(args->disable & NV_DEVICE_DISABLE_MMIO) &&
	    !nv_subdev(device)->mmio) {
		nv_subdev(device)->mmio  = ioremap(mmio_base, mmio_size);
		if (!nv_subdev(device)->mmio) {
			nv_error(device, "unable to map device registers\n");
			return -ENOMEM;
		}
	}

	/* ensure requested subsystems are available for use */
	for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) {
		if (!(oclass = device->oclass[i]) || (disable & (1ULL << i)))
			continue;

		if (device->subdev[i]) {
			nouveau_object_ref(device->subdev[i],
					  &devobj->subdev[i]);
			continue;
		}

		ret = nouveau_object_ctor(nv_object(device), NULL,
					  oclass, NULL, i,
					  &devobj->subdev[i]);
		if (ret == -ENODEV)
			continue;
		if (ret)
			return ret;

		/* note: can't init *any* subdevs until devinit has been run
		 * due to not knowing exactly what the vbios init tables will
		 * mess with.  devinit also can't be run until all of its
		 * dependencies have been created.
		 *
		 * this code delays init of any subdev until all of devinit's
		 * dependencies have been created, and then initialises each
		 * subdev in turn as they're created.
		 */
		while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
			struct nouveau_object *subdev = devobj->subdev[c++];
			if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_inc(subdev);
				if (ret)
					return ret;
				atomic_dec(&nv_object(device)->usecount);
			} else
			if (subdev) {
				nouveau_subdev_reset(subdev);
			}
		}
	}

	return 0;
}

static void
nouveau_devobj_dtor(struct nouveau_object *object)
{
	struct nouveau_devobj *devobj = (void *)object;
	int i;

	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
		nouveau_object_ref(NULL, &devobj->subdev[i]);

	nouveau_parent_destroy(&devobj->base);
}

static u8
nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
{
	return nv_rd08(object->engine, addr);
}

static u16
nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
{
	return nv_rd16(object->engine, addr);
}

static u32
nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
{
	return nv_rd32(object->engine, addr);
}

static void
nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
{
	nv_wr08(object->engine, addr, data);
}

static void
nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
{
	nv_wr16(object->engine, addr, data);
}

static void
nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
{
	nv_wr32(object->engine, addr, data);
}

static struct nouveau_ofuncs
nouveau_devobj_ofuncs = {
	.ctor = nouveau_devobj_ctor,
	.dtor = nouveau_devobj_dtor,
	.init = _nouveau_parent_init,
	.fini = _nouveau_parent_fini,
	.rd08 = nouveau_devobj_rd08,
	.rd16 = nouveau_devobj_rd16,
	.rd32 = nouveau_devobj_rd32,
	.wr08 = nouveau_devobj_wr08,
	.wr16 = nouveau_devobj_wr16,
	.wr32 = nouveau_devobj_wr32,
};

/******************************************************************************
 * nouveau_device: engine functions
 *****************************************************************************/
static struct nouveau_oclass
nouveau_device_sclass[] = {
	{ 0x0080, &nouveau_devobj_ofuncs },
	{}
};

static int
nouveau_device_fini(struct nouveau_object *object, bool suspend)
{
	struct nouveau_device *device = (void *)object;
	struct nouveau_object *subdev;
	int ret, i;

	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_dec(subdev, suspend);
				if (ret && suspend)
					goto fail;
			}
		}
	}

	ret = 0;
fail:
	for (; ret && i < NVDEV_SUBDEV_NR; i++) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_inc(subdev);
				if (ret) {
					/* XXX */
				}
			}
		}
	}

	return ret;
}

static int
nouveau_device_init(struct nouveau_object *object)
{
	struct nouveau_device *device = (void *)object;
	struct nouveau_object *subdev;
	int ret, i;

	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_inc(subdev);
				if (ret)
					goto fail;
			} else {
				nouveau_subdev_reset(subdev);
			}
		}
	}

	ret = 0;
fail:
	for (--i; ret && i >= 0; i--) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS))
				nouveau_object_dec(subdev, false);
		}
	}

	return ret;
}

static void
nouveau_device_dtor(struct nouveau_object *object)
{
	struct nouveau_device *device = (void *)object;

	mutex_lock(&nv_devices_mutex);
	list_del(&device->head);
	mutex_unlock(&nv_devices_mutex);

	if (nv_subdev(device)->mmio)
		iounmap(nv_subdev(device)->mmio);

	nouveau_engine_destroy(&device->base);
}

static struct nouveau_oclass
nouveau_device_oclass = {
	.handle = NV_ENGINE(DEVICE, 0x00),
	.ofuncs = &(struct nouveau_ofuncs) {
		.dtor = nouveau_device_dtor,
		.init = nouveau_device_init,
		.fini = nouveau_device_fini,
	},
};

int
nouveau_device_create_(struct pci_dev *pdev, u64 name, const char *sname,
		       const char *cfg, const char *dbg,
		       int length, void **pobject)
{
	struct nouveau_device *device;
	int ret = -EEXIST;

	mutex_lock(&nv_devices_mutex);
	list_for_each_entry(device, &nv_devices, head) {
		if (device->handle == name)
			goto done;
	}

	ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
				     "DEVICE", "device", length, pobject);
	device = *pobject;
	if (ret)
		goto done;

	device->pdev = pdev;
	device->handle = name;
	device->cfgopt = cfg;
	device->dbgopt = dbg;
	device->name = sname;

	nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
	nv_engine(device)->sclass = nouveau_device_sclass;
	list_add(&device->head, &nv_devices);
done:
	mutex_unlock(&nv_devices_mutex);
	return ret;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <core/object.h>
	26	#include <core/device.h>
	27	#include <core/client.h>
9274f4a9 BS	28	#include <core/option.h>
	29
	30	#include <core/class.h>
	31
dded35de	32	#include <engine/device.h>
9274f4a9 BS	33
	34	static DEFINE_MUTEX(nv_devices_mutex);
	35	static LIST_HEAD(nv_devices);
	36
	37	struct nouveau_device *
	38	nouveau_device_find(u64 name)
	39	{
	40	struct nouveau_device device, match = NULL;
	41	mutex_lock(&nv_devices_mutex);
	42	list_for_each_entry(device, &nv_devices, head) {
	43	if (device->handle == name) {
	44	match = device;
	45	break;
	46	}
	47	}
	48	mutex_unlock(&nv_devices_mutex);
	49	return match;
	50	}
	51
	52	/******************************************************************************
	53	* nouveau_devobj (0x0080): class implementation
	54	*****************************************************************************/
	55	struct nouveau_devobj {
	56	struct nouveau_parent base;
	57	struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
9274f4a9 BS	58	};
	59
	60	static const u64 disable_map[] = {
	61	[NVDEV_SUBDEV_VBIOS] = NV_DEVICE_DISABLE_VBIOS,
206c38a9	62	[NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	63	[NVDEV_SUBDEV_GPIO] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	64	[NVDEV_SUBDEV_I2C] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	65	[NVDEV_SUBDEV_CLOCK] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	66	[NVDEV_SUBDEV_MXM] = NV_DEVICE_DISABLE_CORE,
9274f4a9	67	[NVDEV_SUBDEV_MC] = NV_DEVICE_DISABLE_CORE,
a10220bb	68	[NVDEV_SUBDEV_BUS] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	69	[NVDEV_SUBDEV_TIMER] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	70	[NVDEV_SUBDEV_FB] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	71	[NVDEV_SUBDEV_LTCG] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	72	[NVDEV_SUBDEV_IBUS] = NV_DEVICE_DISABLE_CORE,
9274f4a9	73	[NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_DISABLE_CORE,
206c38a9	74	[NVDEV_SUBDEV_VM] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	75	[NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	76	[NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	77	[NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	78	[NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	79	[NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO,
206c38a9 BS	80	[NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO,
9274f4a9 BS	81	[NVDEV_ENGINE_GR] = NV_DEVICE_DISABLE_GRAPH,
	82	[NVDEV_ENGINE_MPEG] = NV_DEVICE_DISABLE_MPEG,
	83	[NVDEV_ENGINE_ME] = NV_DEVICE_DISABLE_ME,
	84	[NVDEV_ENGINE_VP] = NV_DEVICE_DISABLE_VP,
	85	[NVDEV_ENGINE_CRYPT] = NV_DEVICE_DISABLE_CRYPT,
	86	[NVDEV_ENGINE_BSP] = NV_DEVICE_DISABLE_BSP,
	87	[NVDEV_ENGINE_PPP] = NV_DEVICE_DISABLE_PPP,
	88	[NVDEV_ENGINE_COPY0] = NV_DEVICE_DISABLE_COPY0,
	89	[NVDEV_ENGINE_COPY1] = NV_DEVICE_DISABLE_COPY1,
c42a7aec	90	[NVDEV_ENGINE_VIC] = NV_DEVICE_DISABLE_VIC,
206c38a9	91	[NVDEV_ENGINE_VENC] = NV_DEVICE_DISABLE_VENC,
9274f4a9 BS	92	[NVDEV_ENGINE_DISP] = NV_DEVICE_DISABLE_DISP,
	93	[NVDEV_SUBDEV_NR] = 0,
	94	};
	95
	96	static int
	97	nouveau_devobj_ctor(struct nouveau_object *parent,
	98	struct nouveau_object *engine,
	99	struct nouveau_oclass oclass, void data, u32 size,
	100	struct nouveau_object **pobject)
	101	{
	102	struct nouveau_client *client = nv_client(parent);
9274f4a9 BS	103	struct nouveau_device *device;
	104	struct nouveau_devobj *devobj;
	105	struct nv_device_class *args = data;
950fbfab MS	106	u32 boot0, strap;
950fbfab MS	107	u64 disable, mmio_base, mmio_size;
9274f4a9	108	void __iomem *map;
7234d023	109	int ret, i, c;
9274f4a9 BS	110
	111	if (size < sizeof(struct nv_device_class))
	112	return -EINVAL;
	113
	114	/* find the device subdev that matches what the client requested */
	115	device = nv_device(client->device);
	116	if (args->device != ~0) {
	117	device = nouveau_device_find(args->device);
	118	if (!device)
	119	return -ENODEV;
	120	}
	121
	122	ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL,
	123	(1ULL << NVDEV_ENGINE_DMAOBJ) \|
	124	(1ULL << NVDEV_ENGINE_FIFO) \|
	125	(1ULL << NVDEV_ENGINE_DISP), &devobj);
	126	*pobject = nv_object(devobj);
	127	if (ret)
	128	return ret;
	129
	130	mmio_base = pci_resource_start(device->pdev, 0);
	131	mmio_size = pci_resource_len(device->pdev, 0);
	132
	133	/* translate api disable mask into internal mapping */
	134	disable = args->debug0;
	135	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
	136	if (args->disable & disable_map[i])
	137	disable \|= (1ULL << i);
	138	}
	139
	140	/* identify the chipset, and determine classes of subdev/engines */
	141	if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) &&
	142	!device->card_type) {
	143	map = ioremap(mmio_base, 0x102000);
43b1e9c9 BS	144	if (map == NULL)
43b1e9c9 BS	145	return -ENOMEM;
9274f4a9 BS	146
	147	/* switch mmio to cpu's native endianness */
	148	#ifndef __BIG_ENDIAN
	149	if (ioread32_native(map + 0x000004) != 0x00000000)
	150	#else
	151	if (ioread32_native(map + 0x000004) == 0x00000000)
	152	#endif
	153	iowrite32_native(0x01000001, map + 0x000004);
	154
	155	/* read boot0 and strapping information */
	156	boot0 = ioread32_native(map + 0x000000);
	157	strap = ioread32_native(map + 0x101000);
	158	iounmap(map);
	159
	160	/* determine chipset and derive architecture from it */
	161	if ((boot0 & 0x0f000000) > 0) {
	162	device->chipset = (boot0 & 0xff00000) >> 20;
	163	switch (device->chipset & 0xf0) {
	164	case 0x10: device->card_type = NV_10; break;
	165	case 0x20: device->card_type = NV_20; break;
	166	case 0x30: device->card_type = NV_30; break;
	167	case 0x40:
	168	case 0x60: device->card_type = NV_40; break;
	169	case 0x50:
	170	case 0x80:
	171	case 0x90:
	172	case 0xa0: device->card_type = NV_50; break;
	173	case 0xc0: device->card_type = NV_C0; break;
	174	case 0xd0: device->card_type = NV_D0; break;
7b4f638b BS	175	case 0xe0:
7b4f638b BS	176	case 0xf0: device->card_type = NV_E0; break;
9274f4a9 BS	177	default:
	178	break;
	179	}
	180	} else
	181	if ((boot0 & 0xff00fff0) == 0x20004000) {
	182	if (boot0 & 0x00f00000)
	183	device->chipset = 0x05;
	184	else
	185	device->chipset = 0x04;
	186	device->card_type = NV_04;
	187	}
	188
	189	switch (device->card_type) {
	190	case NV_04: ret = nv04_identify(device); break;
	191	case NV_10: ret = nv10_identify(device); break;
	192	case NV_20: ret = nv20_identify(device); break;
	193	case NV_30: ret = nv30_identify(device); break;
	194	case NV_40: ret = nv40_identify(device); break;
	195	case NV_50: ret = nv50_identify(device); break;
	196	case NV_C0:
	197	case NV_D0: ret = nvc0_identify(device); break;
	198	case NV_E0: ret = nve0_identify(device); break;
	199	default:
	200	ret = -EINVAL;
	201	break;
	202	}
	203
	204	if (ret) {
	205	nv_error(device, "unknown chipset, 0x%08x\n", boot0);
	206	return ret;
	207	}
	208
	209	nv_info(device, "BOOT0 : 0x%08x\n", boot0);
2094dd82 BS	210	nv_info(device, "Chipset: %s (NV%02X)\n",
2094dd82 BS	211	device->cname, device->chipset);
9274f4a9 BS	212	nv_info(device, "Family : NV%02X\n", device->card_type);
	213
	214	/* determine frequency of timing crystal */
	215	if ( device->chipset < 0x17 \|\|
1f2285d4	216	(device->chipset >= 0x20 && device->chipset < 0x25))
9274f4a9 BS	217	strap &= 0x00000040;
	218	else
	219	strap &= 0x00400040;
	220
	221	switch (strap) {
	222	case 0x00000000: device->crystal = 13500; break;
	223	case 0x00000040: device->crystal = 14318; break;
	224	case 0x00400000: device->crystal = 27000; break;
	225	case 0x00400040: device->crystal = 25000; break;
	226	}
	227
	228	nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
	229	}
	230
	231	if (!(args->disable & NV_DEVICE_DISABLE_MMIO) &&
	232	!nv_subdev(device)->mmio) {
	233	nv_subdev(device)->mmio = ioremap(mmio_base, mmio_size);
	234	if (!nv_subdev(device)->mmio) {
	235	nv_error(device, "unable to map device registers\n");
43b1e9c9	236	return -ENOMEM;
9274f4a9 BS	237	}
	238	}
	239
	240	/* ensure requested subsystems are available for use */
10caad33	241	for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) {
9274f4a9 BS	242	if (!(oclass = device->oclass[i]) \|\| (disable & (1ULL << i)))
	243	continue;
	244
10caad33	245	if (device->subdev[i]) {
7234d023 BS	246	nouveau_object_ref(device->subdev[i],
7234d023 BS	247	&devobj->subdev[i]);
10caad33	248	continue;
9274f4a9 BS	249	}
9274f4a9 BS	250
10caad33 BS	251	ret = nouveau_object_ctor(nv_object(device), NULL,
	252	oclass, NULL, i,
	253	&devobj->subdev[i]);
	254	if (ret == -ENODEV)
	255	continue;
	256	if (ret)
	257	return ret;
	258
7234d023 BS	259	/* note: can't init any subdevs until devinit has been run
	260	* due to not knowing exactly what the vbios init tables will
	261	* mess with. devinit also can't be run until all of its
	262	* dependencies have been created.
	263	*
	264	* this code delays init of any subdev until all of devinit's
	265	* dependencies have been created, and then initialises each
	266	* subdev in turn as they're created.
	267	*/
	268	while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
	269	struct nouveau_object *subdev = devobj->subdev[c++];
	270	if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
	271	ret = nouveau_object_inc(subdev);
	272	if (ret)
	273	return ret;
10caad33 BS	274	atomic_dec(&nv_object(device)->usecount);
	275	} else
	276	if (subdev) {
	277	nouveau_subdev_reset(subdev);
9274f4a9 BS	278	}
9274f4a9 BS	279	}
9274f4a9 BS	280	}
	281
	282	return 0;
	283	}
	284
	285	static void
	286	nouveau_devobj_dtor(struct nouveau_object *object)
	287	{
	288	struct nouveau_devobj devobj = (void )object;
	289	int i;
	290
	291	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
	292	nouveau_object_ref(NULL, &devobj->subdev[i]);
	293
	294	nouveau_parent_destroy(&devobj->base);
	295	}
	296
9274f4a9	297	static u8
0a32241d	298	nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
9274f4a9 BS	299	{
	300	return nv_rd08(object->engine, addr);
	301	}
	302
	303	static u16
0a32241d	304	nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
9274f4a9 BS	305	{
	306	return nv_rd16(object->engine, addr);
	307	}
	308
	309	static u32
0a32241d	310	nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
9274f4a9 BS	311	{
	312	return nv_rd32(object->engine, addr);
	313	}
	314
	315	static void
0a32241d	316	nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
9274f4a9 BS	317	{
	318	nv_wr08(object->engine, addr, data);
	319	}
	320
	321	static void
0a32241d	322	nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
9274f4a9 BS	323	{
	324	nv_wr16(object->engine, addr, data);
	325	}
	326
	327	static void
0a32241d	328	nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
9274f4a9 BS	329	{
	330	nv_wr32(object->engine, addr, data);
	331	}
	332
	333	static struct nouveau_ofuncs
	334	nouveau_devobj_ofuncs = {
	335	.ctor = nouveau_devobj_ctor,
	336	.dtor = nouveau_devobj_dtor,
10caad33 BS	337	.init = _nouveau_parent_init,
10caad33 BS	338	.fini = _nouveau_parent_fini,
9274f4a9 BS	339	.rd08 = nouveau_devobj_rd08,
	340	.rd16 = nouveau_devobj_rd16,
	341	.rd32 = nouveau_devobj_rd32,
	342	.wr08 = nouveau_devobj_wr08,
	343	.wr16 = nouveau_devobj_wr16,
	344	.wr32 = nouveau_devobj_wr32,
	345	};
	346
	347	/******************************************************************************
	348	* nouveau_device: engine functions
	349	*****************************************************************************/
9aecbada	350	static struct nouveau_oclass
9274f4a9 BS	351	nouveau_device_sclass[] = {
	352	{ 0x0080, &nouveau_devobj_ofuncs },
	353	{}
	354	};
	355
066a5d09 BS	356	static int
	357	nouveau_device_fini(struct nouveau_object *object, bool suspend)
	358	{
	359	struct nouveau_device device = (void )object;
10caad33 BS	360	struct nouveau_object *subdev;
	361	int ret, i;
	362
	363	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
	364	if ((subdev = device->subdev[i])) {
	365	if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
	366	ret = nouveau_object_dec(subdev, suspend);
	367	if (ret && suspend)
	368	goto fail;
	369	}
	370	}
	371	}
	372
	373	ret = 0;
	374	fail:
	375	for (; ret && i < NVDEV_SUBDEV_NR; i++) {
	376	if ((subdev = device->subdev[i])) {
	377	if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
	378	ret = nouveau_object_inc(subdev);
	379	if (ret) {
	380	/* XXX */
	381	}
	382	}
	383	}
	384	}
	385
	386	return ret;
066a5d09 BS	387	}
	388
	389	static int
	390	nouveau_device_init(struct nouveau_object *object)
	391	{
	392	struct nouveau_device device = (void )object;
10caad33 BS	393	struct nouveau_object *subdev;
	394	int ret, i;
	395
	396	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
	397	if ((subdev = device->subdev[i])) {
	398	if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
	399	ret = nouveau_object_inc(subdev);
	400	if (ret)
	401	goto fail;
	402	} else {
	403	nouveau_subdev_reset(subdev);
	404	}
	405	}
	406	}
	407
	408	ret = 0;
	409	fail:
	410	for (--i; ret && i >= 0; i--) {
	411	if ((subdev = device->subdev[i])) {
	412	if (!nv_iclass(subdev, NV_ENGINE_CLASS))
	413	nouveau_object_dec(subdev, false);
	414	}
	415	}
	416
	417	return ret;
066a5d09 BS	418	}
066a5d09 BS	419
ebb945a9 BS	420	static void
	421	nouveau_device_dtor(struct nouveau_object *object)
	422	{
	423	struct nouveau_device device = (void )object;
	424
	425	mutex_lock(&nv_devices_mutex);
	426	list_del(&device->head);
	427	mutex_unlock(&nv_devices_mutex);
	428
dded35de BS	429	if (nv_subdev(device)->mmio)
dded35de BS	430	iounmap(nv_subdev(device)->mmio);
ebb945a9	431
dded35de	432	nouveau_engine_destroy(&device->base);
ebb945a9 BS	433	}
ebb945a9 BS	434
9274f4a9 BS	435	static struct nouveau_oclass
9274f4a9 BS	436	nouveau_device_oclass = {
dded35de	437	.handle = NV_ENGINE(DEVICE, 0x00),
9274f4a9	438	.ofuncs = &(struct nouveau_ofuncs) {
ebb945a9	439	.dtor = nouveau_device_dtor,
066a5d09 BS	440	.init = nouveau_device_init,
066a5d09 BS	441	.fini = nouveau_device_fini,
9274f4a9 BS	442	},
	443	};
	444
	445	int
	446	nouveau_device_create_(struct pci_dev pdev, u64 name, const char sname,
	447	const char cfg, const char dbg,
	448	int length, void **pobject)
	449	{
	450	struct nouveau_device *device;
	451	int ret = -EEXIST;
	452
	453	mutex_lock(&nv_devices_mutex);
	454	list_for_each_entry(device, &nv_devices, head) {
	455	if (device->handle == name)
	456	goto done;
	457	}
	458
dded35de	459	ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
9274f4a9 BS	460	"DEVICE", "device", length, pobject);
	461	device = *pobject;
	462	if (ret)
	463	goto done;
	464
9274f4a9 BS	465	device->pdev = pdev;
	466	device->handle = name;
	467	device->cfgopt = cfg;
	468	device->dbgopt = dbg;
	469	device->name = sname;
	470
	471	nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
9aecbada	472	nv_engine(device)->sclass = nouveau_device_sclass;
9274f4a9 BS	473	list_add(&device->head, &nv_devices);
	474	done:
	475	mutex_unlock(&nv_devices_mutex);
	476	return ret;
	477	}